Method and system for evaluating EDA tool

An evaluation method and tool technology, which is applied in the evaluation method and system field of EDA tools, can solve problems such as large workload, outdated supporting software, cumbersome FPGA software development, etc., and achieve the effect of meeting demand, fast and effective demand, and accelerating iteration cycle

Inactive Publication Date: 2017-03-15
HERCULES MICROELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the supporting software of domestic FPGA is obviously lagging behind
At the same time, the development of FPGA software is very cumbersome. It includes many tool chains, many intermediate files, and a large number of instances to be tested; and, every change in the EDA development process requires a regression test on the tested instances, which not only requires A lot of work and difficult to evaluate the progress of changes
Existing methods are difficult to speed up the iteration cycle of EDA tools and provide quantitative guidance for the development of EDA tools, so a faster and more effective development method is needed to meet the needs of domestic FPGAs for EDA tools

Method used

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  • Method and system for evaluating EDA tool
  • Method and system for evaluating EDA tool

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Embodiment Construction

[0017] The technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0018] An embodiment of the present invention provides an evaluation method of an EDA tool, figure 1 The schematic flow chart of the evaluation method of the EDA tool that the embodiment of the present invention provides, as figure 1 As shown, the method includes step S101-step S111: specifically:

[0019] In step S101, the developer updates the version in the background, and submits the source code of the updated version to the server, so that the server compiles the source code regularly to generate an executable file.

[0020] It should be noted that the above-mentioned timing compilation includes: compiling every time the developer updates the version, and / or compiling at regular intervals according to the source code currently received by the server.

[0021] Step S102, starting the configurable regression test,...

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Abstract

The invention relates to a method and a system for evaluating an EDA tool. The method provided by the embodiment of the invention comprises the following steps: compiling in a timing manner according to the source code of an updated version submitted by a developer by a server, and generating an executable file; starting configurable regression testing; distributing corresponding computing resources to a plurality of tasks according to a load condition; controlling automatic parallel running of the tasks through scripts, and acquiring running results; collecting the running results and generating a testing report according to the running result of each task; determining whether the function of version development is correct according to the received testing report by the developer, if the function is correct, storing the testing report in a report database; comparing the current testing report with history testing reports stored in the testing report database, and acquiring a comparison result; and judging whether the quality of the version meets the requirement or not according to the received comparison result by the developer, and if the quality of the version meets the requirement, releasing a new version. According to the method, the iteration cycle of the EDA tool can be quickened, and quantitative guidance is provided for the development of the EDA tool.

Description

technical field [0001] The invention relates to the field of EDA, in particular to an evaluation method and system of an EDA tool. Background technique [0002] With the rapid growth of my country's field-programmable gate array (Field-Programmable Gate Array, referred to as FPGA) military industry and information security business, the acceleration of import substitution in the communication field, the urgent need for localization of FPGA, the supporting electronic design automation (Electronic Design Automation, referred to as EDA ) tools are becoming more and more important as the FPGA scale increases. However, the supporting software of domestic FPGA is obviously lagging behind. At the same time, the development of FPGA software is very cumbersome. It includes many tool chains, many intermediate files, and a large number of instances to be tested; and, every change in the EDA development process requires a regression test on the tested instances, which not only requires ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/44G06F17/50
CPCG06F8/71G06F30/00
Inventor 苏攀王元鹏樊平
Owner HERCULES MICROELECTRONICS CO LTD
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