Method and apparatus for detecting a packet error in a wireless communications system with minimum overhead using tail bits in turbo code

Abstract

The need for separate CRC bits is eliminated by taking advantage of what has been determined to be an embedded error detection capability of the tail bits generated by the constituent encoders of a turbo coder to perform error detection following turbo decoding. Specifically, it has been recognized that the tail bits are similar to CRC bits that would be generated by a CRC encoder that uses as its generating polynomial the feedback polynomial used by the turbo encoder. At the turbo decoder, after a final turbo decoding iteration cycle, a check is performed on the decoded systematic information bits by calculating the tail bits from the decoded information bits using that generating polynomial and bit-by-bit comparing the calculated tail bits with the systematic tail bits decoded by the turbo decoder. If a mismatch occurs at one or more bit positions, an error is indicated and the packet is marked as having failed. Advantageously, by using the tail bits for error checking, no additional bits need to be allocated and transmitted for packet error detection purposes.

Description

TECHNICAL FIELD [0001] This invention relates to wireless communications, and more particularly, to detecting a turbo-coded packet error at the receiver in a wireless communications system. BACKGROUND OF THE INVENTION [0002] In wireless communications systems, such as those operating in accordance with 3GPP2 CDMA2000-1x standards and 3GPP UMTS W-CDMA standards, a turbo code has been adopted for data transmission on both the uplink and downlink due to its superior error correcting capabilities. To detect the residue errors that cannot be corrected by the turbo decoder, Cyclic Redundancy Check (CRC) code bits are appended to the packet data before the encoder at the transmitter. A CRC check is then performed at the receiver on the decoded packet to determine whether a pass or fail results. [0003]FIG. 1 shows a high-level block diagram of wireless communications system that uses turbo encoding for error correction and CRC for error detecting. This block diagram is applicable to both 3G...

AI Technical Summary

Benefits of technology

[0004] The inventors have recognized that advantage can be taken of the tail bits generated by the two constituent encoders of a turbo encoder. The two constituent encoders encode such tail bits after all information bits in a packet or block of data have been encoded and are generated to restore each encoder to an all-zero state so as to be ready to encode a next data packet. Specifically, the inventors have recognized that these tail bits as generated by the turbo encoder and when decoded by the turbo decoder are similar to CRC bits that would be generated by a CRC encoder that uses as its generating polynomial the feedback polynomial g0(D) in the transfer function used in the turbo encoder by each constituent encoder in generating each constituent code. At the turbo decoder, after a final turbo decoding iteration cycle, a CRC check is performed on the decoded systematic information bits by calculating the CRC-like tail bits from those decoded information bits using g0(D) as the generating polynomial. The resultant calculated tail bits are then bit-by-bit compared with the systematic tail bits decoded by the turbo decoder. If a mismatch occurs at one or more bit positions, an error is indicated and the packet is marked as having failed. Advantageously, by using the tail bits for error checking, no additional bits need to be allocated and transmitted for packet error detection purposes.

Problems solved by technology

Since only three tail bits are thus produced as output from each constituent encoder, the error detection capability afforded using these three bits alone is relatively weak for error detecting purposes.

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