The embodiment of the invention provides a logic design segmentation method and
system, and belongs to the technical field of logic array prototype
system verification, and the method specifically comprises the steps: collecting an RTL design file for describing a logic circuit; performing grammatical analysis
processing on the RTL design file, extracting an always object and an assign object in the logic model object, respectively packaging, constructing and generating a
hypergraph data structure, performing attribute analysis,
processing according to the
clock domain information to obtain operation frequency information, and performing associated storage on the
clock domain
information domain and the operation frequency information and corresponding nodes; and performing segmentation
processing to obtain corresponding grouped data. By means of the processing scheme, other processing at the back end of the process is not affected, the segmentation duration is shortened, the segmentation efficiency is improved, meanwhile, efficient, reasonable and correct segmentation processing is conducted on the
chip design logic content, the performance and efficiency of design segmentation aregreatly improved, then the process of user front-end function
verification is accelerated, and the appearance of
integrated circuit products is accelerated.