Disclosed is an overall FPGA automated
layout method based on an analytical method. The
layout method comprises the steps that S1, constraint information and circuit
netlist information are packed andinput through mapping; S2, time
delay information of user constraints is input through a static time
delay analyzer; S3, each circuit unit module is automatically laid out in corresponding positionsin a
physical design of a
chip according to physical constraints designated by a user, and an input and output
layout, a global
clock layout, an initial layout, an overall layout, a legitimation layout and a detailed layout are involved; according to the overall layout, a
conjugate gradient method based on a mixed step-length adjustment strategy is adopted for solving according to the initial positions of the circuit unit modules and circuit topological connection, a step-length calculation manner is dynamically adjusted aiming at the circuit unit modules of different levels and layout states,and the circuit unit modules are distributed; S4, the circuit
netlist information is output. By means of the layout method, rapid automated layout is conducted on a
chip layout, so that the
line length and time
delay of a network meet the user constraints; by adjusting a step-length optimization strategy of the overall layout, the quality and speed of the layout are optimized.