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70 results about "Description logic" patented technology

Description logics (DL) are a family of formal knowledge representation languages. Many DLs are more expressive than propositional logic but less expressive than first-order logic. In contrast to the latter, the core reasoning problems for DLs are (usually) decidable, and efficient decision procedures have been designed and implemented for these problems. There are general, spatial, temporal, spatiotemporal, and fuzzy descriptions logics, and each description logic features a different balance between DL expressivity and reasoning complexity by supporting different sets of mathematical constructors.

Debugging system for gate level IC designs

A register transfer level (RTL) IC design describing a IC as comprising a plurality of logic blocks communicating via signals and using a high level language to describe the logic blocks according to the logical relationships between signals they receive and signals they generate. A computer-aided synthesizer processes an RTL IC design to produce a gate level design for the IC describing its logic blocks as comprising instances of cells communicating via signals. A synthesizer or emulator processes the gate level design to produce a gate level dump file referencing signals of the gate level design and indicating how those signals behave in response to time-varying signals supplied as inputs to the IC. The gate level dump file is converted into an RTL dump file referencing signals of the RTL design and indicating how those signals behave. A debugger processes the RTL dump file to produce displays depicting the RTL design and behavior of signals indicated by the RTL dump file. Thus while the IC is simulated or emulated at the gate level of the design to produce waveform data for a debugger, the gate level-to-RTL dump file conversion process enables a designer debug the more familiar RTL design based on the gate level simulation or emulation results.
Owner:SYNOPSYS INC

Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit

A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached. In response to determining that a union of first set and the second set of m-ary decision representations do not describe the logic function, the first and second size limits are increased, and the steps of building the first and second set are repeated. In response to determining that the union of the first set of m-ary decision representations and the second set of m-ary decision representations describe the logic function, the union is reported.
Owner:GLOBALFOUNDRIES US INC

Chinese semantic proofreading method based on ontology consistency verification and reasoning

InactiveCN103593335AAccurately determine the cause of the errorNo ambiguitySpecial data processing applicationsLogical consistencyNatural language
A Chinese semantic proofreading method based on ontology consistency verification and reasoning includes: using the ontology learning technology to extract semantic contents from non-structural natural Chinese languages, and converting the extracted semantic contents into structural ontology forms; establishing field ontology databases, and using corresponding ontology databases according to different fields; building models integrating the formed Chinese semantic proofreading key technology, in a form of plug-in, into a grammar verifying tool or using other implementation forms such as independent Chinese semantic verification software; in the grammar verifying tool, using the consistency reasoning and verification mechanism based on description logic and contained in the ontology reasoning language to sequentially perform consistency verification and reasoning on the extracted semantic contents and correct field ontology database input into a reasoning machine according to preset orders, and labeling error labels on the Chinese semantic contents, with inconsistent logic, in the reasoning result. By the method, word-level and grammar-level Chinese proofreading can be achieved, and Chinese semantic proofreading in special fields can also be achieved.
Owner:姜赢

Logic design segmentation method and system

The embodiment of the invention provides a logic design segmentation method and system, and belongs to the technical field of logic array prototype system verification, and the method specifically comprises the steps: collecting an RTL design file for describing a logic circuit; performing grammatical analysis processing on the RTL design file, extracting an always object and an assign object in the logic model object, respectively packaging, constructing and generating a hypergraph data structure, performing attribute analysis, processing according to the clock domain information to obtain operation frequency information, and performing associated storage on the clock domain information domain and the operation frequency information and corresponding nodes; and performing segmentation processing to obtain corresponding grouped data. By means of the processing scheme, other processing at the back end of the process is not affected, the segmentation duration is shortened, the segmentation efficiency is improved, meanwhile, efficient, reasonable and correct segmentation processing is conducted on the chip design logic content, the performance and efficiency of design segmentation aregreatly improved, then the process of user front-end function verification is accelerated, and the appearance of integrated circuit products is accelerated.
Owner:S2C

High-accuracy computer automatic marking method for subjective items based on domain ontology

The invention discloses a high-accuracy computer automatic marking method for subjective items based on domain ontology. The method comprises the following steps: firstly, building a domain ontology structure suitable for automatically marking the subjective items, and explaining a domain relation into a sentence in a natural language for describing a domain event; secondly, building a subjective item bank structure based on the domain ontology and item description logic, requesting the items to accord with the subjective item bank structure, and then marking answer sheets of examinees according to the following steps: (1) obtaining single words and part-of-speech tagging in the answer sheet of each examinee; (2) tagging an ontology element; (3) generating an answer sheet semanteme based on the domain relation; (4) calculating based on the similarity of the answer of the domain relation and the answer sheet semanteme; (5) calculating the score of the answer sheet of the subjective items of each examinee. According to the method, the semanteme analyzing and processing flows of the natural language in each examinee answer sheet are greatly simplified; the semanteme of answer domain knowledge is relatively fully expressed; the accuracy for automatically marking the subjective items is ensured.
Owner:南京乐酷网络科技有限公司

Cloud manufacturing capability description method supporting use on demand and sharing circulation of manufacturing capability

The invention provides a cloud manufacturing capability description method supporting use on demand and sharing circulation of manufacturing capability. The method comprises the following steps of: extracting and classifying fuzzy information and dynamic behavior information in a knowledge-based manufacturing capability description model (namely a multi-dimension manufacturing capability information model); formalizing a fuzzy concept and a fuzzy role relationship according to a fuzzy description logic; describing service state change and dynamic combination flow according to a dynamic description logic; and giving an intelligent search and recommendation mechanism of the manufacturing capability based on the description method. According to the cloud manufacturing capability description method, the qualitative and quantitative properties of each dimension and each level of manufacturing capability can be taken into sufficient consideration, and a knowledge-based manufacturing capability language is provided, so that manufacturing capability services are stored in a cloud manufacturing service platform in an ontology mode, and a manufacturing capability service network is formed on the basis of various relationships among the services and supports the intelligent search and the use on demand of users.
Owner:BEIHANG UNIV

Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit

A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached. In response to determining that a union of first set and the second set of m-ary decision representations do not describe the logic function, the first and second size limits are increased, and the steps of building the first and second set are repeated. In response to determining that the union of the first set of m-ary decision representations and the second set of m-ary decision representations describe the logic function, the union is reported.
Owner:GLOBALFOUNDRIES U S INC

Dynamic hierarchical integrated data accessing method capable of guaranteeing semantic correctness

The invention discloses a dynamic hierarchical integrated data accessing method capable of guaranteeing semantic correctness and aims to solve the problem about how to provide data access with completely correct semantics under condition of integration of large-scale relation databases. The technical scheme includes that the dynamic hierarchical integrated data accessing method includes firstly, expanding to obtain a description logic subset DL-Lite, then layering the ontology TBox on the basis of the description logics, and establishing LAV (local as view) mapping and O-GAV (object-global as view) mapping between the relation database and the ontology; expanding and rewriting query request by means of SuperRef algorithm according to the T<Q> in layering of the TBox, and establishing a dynamic ABox A<Q> according to query results; and finally, refining the ABox A<Q>, and feeding back query response results. The dynamic hierarchical integrated data accessing method can provide data with the completely correct semantics for users and meet the requirement for correctness of the semantics in integrated data access. Further, calculating complexity can be reduced and expanding, query and rewriting efficiency can be improved.
Owner:NAT UNIV OF DEFENSE TECH
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