21 results about "Theorem provers" patented technology

System and methods are disclosed for providing unforgeable telemetry on computer platforms. Mathematical modeling and theorem proving are utilized to guarantee the integrity of telemetry probe execution flow and trigger, thereby preventing circumvention and tampering of logged probe data. In contrast to current state-of-the-art solutions that rely implicitly on the operating environment, this approach provides a sound and complete assurance of telemetry output. The system enables organizations to map unforgeable telemetry probe data to industry and government cybersecurity regulatory controls, ensuring compliance therewith. This invention addresses the shortcomings of existing solutions, including their vulnerability to sophisticated attacks, operational complexity, and inability to provide unforgeable telemetry data, thereby providing a reliable and accurate monitoring output in the presence of cyberattacks on computer platforms.

The invention discloses a large language model output quality guarantee method, device and system based on chain type deterministic reasoning verification, and belongs to the field of artificial intelligence safety, deterministic calculation and reasoning verification. The method comprises the following steps: classifying each reasoning step generated by LLM into a deterministic step (bT: deductive reasoning, verified facts and mathematical proof) or a non-deterministic step (bF: inductive reasoning, unverified references and creative guess), and accumulatively constructing a reasoning chain; chain certainty verification chain (chain) = foldr (AND, true, chain) and time complexity O (n) are carried out in each k steps; if the bF is returned, a chain pollution elimination theorem is applied to prove that once the chain contains non-deterministic steps, the whole chain loses deterministic guarantee; and a deterministic boundary report is generated, and a non-deterministic initial position is marked. The device comprises an inference classifier, a reference verifier, a mathematical checker and a chain verification engine, and all the modules can be independently realized (formalized verification / database query / rule engine / mixed mode).

The invention discloses a method for realizing a redundant function memory chip test, which relates to the technical field of memory chip test, and comprises the following steps: calculating hyperedge coupling strength based on a hypergraph fault model, and generating a test vector sequence and a memory unit test instruction by adopting a weighted flipping mode according to the hyperedge coupling strength; injecting the test vector sequence into a tested memory chip, executing memory unit test instructions one by one, and capturing a failure unit coordinate and a failure mode category at the same time; constructing a Hall triad based on the failure unit coordinates and the failure mode category, executing theorem proving on the Hall triad by using a theorem proving device to verify the test completeness, generating an increment test vector when the verification fails, executing theorem proving again, and recording the result of the test completeness; according to the method, the hypergraph fault model is established, so that the coverage rate of non-independent faults is increased, the number of redundant test instructions is reduced, the test time and resource consumption are reduced, and the defect detection efficiency is improved.

The application provides a kind of supervisory contract rule conflict detection method, it is related to blockchain technology field.The present application takes the supervisory contract code as input, the supervisory rules in supervisory contract are symbolized, and the supervisory rule conflict problem is converted into constraint solving problem using symbol analysis technology, theorem proving is carried out through SMT solver, and each type of conflict in supervisory rule is found, or it is proved that supervisory rule has no conflict.Specifically, it includes type analysis stage, supervisory rule symbolization stage and conflict detection stage.The present application can detect self-conflict, complete conflict, partial conflict and other rule conflict problems of supervisory contract in blockchain financial application, and provides effectiveness guarantee for realizing digitalization of supervisory rules.

The invention discloses an automatic rewriting conversion method from a function neural network operator / model to a C code, and belongs to the field of deep learning. A deep learning framework with tensor shape safety is constructed in a Coq theorem prover, and a corresponding C code is automatically generated. A neural network operator or a neural network model defined by the method can detect the tensor shape incompatibility problem and the parameter limitation incompatibility problem in the compiling stage, meanwhile, the C code is automatically generated, time-consuming and tedious manual derivation are avoided, and the development threshold is lowered.

System and methods are disclosed for providing unforgeable telemetry on computer platforms. Mathematical modeling and theorem proving are utilized to guarantee the integrity of telemetry probe execution flow and trigger, thereby preventing circumvention and tampering of logged probe data. In contrast to current state-of-the-art solutions that rely implicitly on the operating environment, this approach provides a sound and complete assurance of telemetry output. The system enables organizations to map unforgeable telemetry probe data to industry and government cybersecurity regulatory controls, ensuring compliance therewith. This invention addresses the shortcomings of existing solutions, including their vulnerability to sophisticated attacks, operational complexity, and inability to provide unforgeable telemetry data, thereby providing a reliable and accurate monitoring output in the presence of cyberattacks on computer platforms.

The invention discloses an automatic verification type code lifting method and device, and the method comprises the steps: obtaining an input source language code program, and then processing the input source language code program into Python program description which takes Python as an intermediate expression to generate a source program by using a preset GAI model; converting the Python program description into a specific grammar of a DSL (Digital Subscriber Line) based on preset pattern matching to generate a target code; the GAI model is further configured to generate an operator template of a target language according to a use manual of the target language provided in advance and the target language, and form an operator template library for pattern matching; after the target code is generated, a theorem prover is used for verifying the target code so as to check whether all program input of the target code is semantically equivalent to a source program or not; the method has the advantages that code lifting is more automatic, and generalization ability and correctness of different DSLs are higher.

The embodiment of the present disclosure discloses a method and device for formal analysis of autonomous positioning of a UAV. The method comprises: obtaining the same name image point coordinates, a preset homogeneous coordinate conversion matrix, a continuous homogeneous coordinate conversion matrix and a coordinate conversion formula, establishing a high-order logic expression of a ground target point in a geodetic coordinate system based on a high-order logic language; constructing a corresponding formal proposition based on the high-order logic expression, the formal proposition describing attribute constraint conditions in the high-order logic expression; verifying the formal proposition based on a theorem prover to determine whether the high-order logic expression meets the attribute constraint conditions. The high-order logic expression of the UAV for determining the non-homogeneous coordinates of the ground target point in the geodetic coordinate system is analyzed by the formal method, and the attribute constraint conditions that must be met by the high-order logic expression are verified, thereby ensuring the accuracy of the analysis result.

The application discloses a formal automatic theorem proving method based on an explicit mode node search tree, and has the characteristics that the method comprises the following steps: 1) formal theorem data acquisition and processing; 2) mode marking and training sample construction; 3) unified proving model training and candidate action probability under a selected proving mode; 4) construction of an explicit mode node search tree and generation of a candidate action under the selected proving mode; 5) execution and verification of a formal theorem prover; 6) updating of the unified proving model; and 7) use of the updated unified proving model for theorem proving tasks of higher difficulty levels and the like. Compared with the prior art, the application has the advantages of improving the adaptability of the model to different proving states, the solving capability in complex formal theorem proving tasks and the coordination between different levels of proving decisions, retaining high-level proving mode information in the search process, enhancing the structural expression capability of the proving process, and having good expansibility and application value.

The application discloses a kind of cooperation logic verification methods of multi-agent system, belong to artificial intelligence and formal verification technical field, to solve the technical problems in the cooperation logic verification of existing multi-agent system (especially multi-agent system), traditional simulation test exists scene coverage is not complete, deep logic defect is difficult to find, and existing formal verification method is poor in adaptability, prone to state explosion, conflict positioning is fuzzy, lack of repairable suggestion.The method is standardized formal modeling to multi-agent system, cooperation target and constraint condition are defined, and the correctness of cooperation logic is verified into a computable model checking problem, multi-dimensional verification is realized by combining theorem prover and model checking tool, and the conflict is accurately positioned for the verification failure scene and the repairable suggestion is provided, and the verification accuracy and efficiency are considered by means of distributed verification, abstract dimension reduction and other optimization methods.

System and methods are disclosed for providing unforgeable telemetry on computer platforms. Mathematical modeling and theorem proving are utilized to guarantee the integrity of telemetry probe execution flow and trigger, thereby preventing circumvention and tampering of logged probe data. In contrast to current state-of-the-art solutions that rely implicitly on the operating environment, this approach provides a sound and complete assurance of telemetry output. The system enables organizations to map unforgeable telemetry probe data to industry and government cybersecurity regulatory controls, ensuring compliance therewith. This invention addresses the shortcomings of existing solutions, including their vulnerability to sophisticated attacks, operational complexity, and inability to provide unforgeable telemetry data, thereby providing a reliable and accurate monitoring output in the presence of cyberattacks on computer platforms.

The invention discloses a formalized verification method of a memory management module and a related device, and relates to the technical field of operating system security, and the formalized verification method comprises the following steps: based on a demand document, a design document and a source code, sequentially constructing a demand layer formalized model, a design layer formalized model and an implementation layer formalized model in an interactive theorem prover, and on the basis of the demand document, constructing a demand layer formalized protocol in the interactive theorem prover, and completing the proving of the demand layer formalized protocol in the interactive theorem prover. And establishing a first refinement relationship between the design layer formalized model and the demand layer formalized model, and completing the certification of the first refinement relationship in the interactive theorem prover. And establishing a second refinement relationship between the implementation layer formalized model and the design layer formalized model, and completing the proof of the second refinement relationship in the interactive theorem prover. If the formalized specification, the first refinement relation and the second refinement relation are proved, it is judged that the memory management module passes formalized verification.

The invention relates to a formal verification method and system for RISC-V multi-core SBI firmware. The formal verification method and system are mainly an automatic verification process combining an Isabel / HOL theorem prover and a heuristic search strategy. The method specifically comprises the following steps: establishing a universal hardware abstraction layer to unify an underlying resource interface, and formally describing a multi-core concurrent model and synchronous logic in Isable / HOL to strictly define the system state and transition. A * search priority ranking is performed on the state space by using a heuristic function, so that a potential problem path is quickly positioned in the complex state space. And the suspicious path is strictly demonstrated by an Isabel / HOL calling theorem proving tool, and the feedback of a failure case is used for dynamically adjusting heuristic parameters and strategies. The verification efficiency and the automation level are improved, and the state space scale is effectively controlled.

The invention belongs to the field of formalized verification, and provides a MedTiny language formalized verification method based on theorem proof. According to the method, a target language similar to the MedTiny structure is designed in a theorem prover Isable, so that verification of the MedTiny program is realized; a theorem proving technology is used to enable a verification result to have strict mathematical guarantee; the Hall triad is simplified according to a preset Hall triad proving rule, so that the problem that the unbounded condition of the cycle index cannot be verified is avoided; according to the technical scheme of the invention, the simplified Hall triad is verified to verify whether the final value of the verification condition obtained through calculation is true or not and whether the weakest pre-condition is contained in the pre-conditions or not is judged, so that the high automation of the verification process is realized through the theorem prover, the manpower demand of experts is greatly reduced, and the verification efficiency and accuracy are remarkably improved.

The invention discloses a formalized language-based computer interlocking software development implementation method, which comprises the following steps of: S1, writing a formalized specification by using a formalized language Z language, defining an abstract state of a system through a mode, defining an initial state, writing a Z mode for each operation, and outputting a Z protocol document; s2, performing formalized verification and theorem certification on the Z protocol document generated in the previous step; s3, if the verification is not passed, redesigning the Z protocol document, and if the verification is passed, refining the Z protocol document for multiple times; and S4, automatically generating a test case, test input and expected output covering all boundary conditions by using a Z auxiliary tool CZT in combination with a user-defined test generator according to the verified and refined Z protocol document. According to the method, the defects that ambiguity and ambiguity are caused by adopting a direct development method based on a natural language, strict logical reasoning and proving cannot be carried out, and automatic verification cannot be carried out can be overcome.

The invention provides a theorem proving premise selection method and device, electronic equipment and a storage medium, and belongs to the technical field of formalized theorem proving, and the method comprises the steps: converting each theorem, definition and lemma in a theorem library into a first expression tree; converting a to-be-proved target expression into a second expression tree; determining a plurality of similarities between each first expression tree and the second expression tree; performing fusion processing on the plurality of similarities corresponding to each first expression tree to obtain a similarity score corresponding to each first expression tree; and selecting a plurality of first expression trees with the highest similarity score as proving preconditions of the target expression. According to the method, the accuracy and efficiency of theorem proving premise selection can be improved.

The invention discloses a heterogeneous metadata programmable, formalized and unified modeling method. The method comprises the steps of 1, feature decoupling and unified representation to form a standardized feature library, 2, programmable mode definition, 3, formalized semantic mapping and unified metadata model generation, and 4, model verification and evolution. According to the method, a heterogeneous metadata adaptation scene is improved through user-defined matching, conversion and constraint rules, an underlying framework does not need to be modified, the logic of a model is ensured and business rules are met by converting semantic description into a formalized language and combining model detection and theorem proof, the risk of data quality after integration is reduced, and the efficiency of data integration is improved. Through online incremental updating and version management, the method adapts to rapid changes of business requirements, avoids the cost problem caused by shutdown reconstruction of traditional modeling, automatically solves term conflicts through fusion of ontology reasoning and semantic embedding, and improves the efficiency of large-scale data integration.

The application discloses a kind of methods for realizing redundant function memory chip test, it is related to memory chip test technical field, including, based on hypergraph fault model calculation hyperedge coupling strength, according to hyperedge coupling strength using weighted flip mode generates test vector sequence and storage unit test instruction;Test vector sequence is injected into the memory chip to be measured, and storage unit test instruction is executed piece by piece, while capturing failure cell coordinates and failure mode category;Based on failure cell coordinates and failure mode category, Hall triplet is constructed, and theorem prover is used to execute theorem proof to Hall triplet to verify test completeness, when verification fails, generate incremental test vector, and re-execute theorem proof, record the result of test completeness;The application establishes hypergraph fault model, improves the coverage of non-independent failure, reduces the number of redundant test instructions, reduces test time and resource consumption, improves defect detection efficiency.

The application discloses a large model thinking chain evaluation method and system for formalized theorem proving, and the method comprises the following steps: constructing an original data set and training a large model to obtain a trained large model as a benchmark model; based on the original data set, a first data set and a second data set are constructed, benchmark intermediate data, first intermediate data and second intermediate data are generated, and the first performance of the benchmark model is determined; based on the comparison result of the benchmark attention data and third attention data, the second performance of the benchmark model is determined; based on the comparison result of the benchmark thinking chain prompt data and fourth benchmark thinking chain prompt data, the third performance of the benchmark model is determined; based on the first performance, the second performance and the third performance, the original data set is modified to obtain a modified training set and a training method; and the trained large model is trained again based on the modified training set to obtain a new trained large model.

The invention provides a structure-to-instance theorem automatic formalization method and device, and relates to the technical field of natural language process.The method comprises the steps that mathematical structure types of non-formalized problem description texts are recognized, and formalization files from structures to instances are generated for each mathematical structure type; performing type check on the generated code of the formalized file, and when the check is not passed, correcting the generated code according to a preset error correction strategy to obtain a skeleton file lacking theorem proof; calling a large model to generate a certification code of each theorem certification, and synthesizing the certification codes into the skeleton file to obtain a formalized code file; and translating the formalized code file back to obtain a formalized problem description text corresponding to the problem description text. The method is used for solving the problems that in the prior art, automatic formalization work lacks the structural understanding ability for mathematical knowledge, and the automatic formalization deduction process from the structure to the theorem is difficult to achieve.