34 results about "Theorem provers" patented technology

Verifying large language model responses involves obtaining a query and its corresponding answer from a large language model. This conversational text is then fed into a second large language model, which translates the answer into first-order logic. The verification process uses an automated theorem prover. It checks the validity of this logic translation by determining the unsatisfiability of two scenarios: one where the negation of the logic translation and domain-specific logic formulas are combined, and another where the logic translation itself is combined with these formulas. Based on this analysis, the theorem prover ascertains whether the translated answer is valid, invalid, or neither. The final step is communicating this verification status through an appropriate output medium, such as a graphical user interface, a database, or a report, providing a structured and methodical approach to assessing the accuracy and reliability of language model responses.

Verifying large language model responses involves obtaining a query and its corresponding answer from a large language model. This conversational text is then fed into a second large language model, which translates the answer into first-order logic. The verification process uses an automated theorem prover. It checks the validity of this logic translation by determining the unsatisfiability of two scenarios: one where the negation of the logic translation and domain-specific logic formulas are combined, and another where the logic translation itself is combined with these formulas. Based on this analysis, the theorem prover ascertains whether the translated answer is valid, invalid, or neither. The final step is communicating this verification status through an appropriate output medium, such as a graphical user interface, a database, or a report, providing a structured and methodical approach to assessing the accuracy and reliability of language model responses.

System and methods are disclosed for providing unforgeable telemetry on computer platforms. Mathematical modeling and theorem proving are utilized to guarantee the integrity of telemetry probe execution flow and trigger, thereby preventing circumvention and tampering of logged probe data. In contrast to current state-of-the-art solutions that rely implicitly on the operating environment, this approach provides a sound and complete assurance of telemetry output. The system enables organizations to map unforgeable telemetry probe data to industry and government cybersecurity regulatory controls, ensuring compliance therewith. This invention addresses the shortcomings of existing solutions, including their vulnerability to sophisticated attacks, operational complexity, and inability to provide unforgeable telemetry data, thereby providing a reliable and accurate monitoring output in the presence of cyberattacks on computer platforms.

The invention relates to the technical field of intelligent law education and law reasoning, and discloses a law immersive education system based on artificial intelligence, and the system comprises an input processing module which is configured to carry out the multistage semantic analysis of a law text inputted by a user, and generates a structured law fact representation; the legal knowledge graph construction module is connected with the input processing module and is used for receiving the structured legal facts and constructing and updating a legal knowledge graph; and the automatic theorem proving module is connected with the legal knowledge graph construction module and is used for executing multi-hop reasoning on the legal knowledge graph based on probabilistic reasoning. According to the technical scheme, the self-adaptive optimization module and the dynamic reasoning mechanism are combined, the technical effects of adjusting the priority of the legal rule in real time and automatically optimizing the reasoning path are achieved, the defects that the reasoning process is stiff, the adaptability is poor, and reasoning errors are likely to be caused are overcome, and the intelligent decision-making capacity of the system is remarkably improved.

The invention discloses a large language model output quality guarantee method, device and system based on chain type deterministic reasoning verification, and belongs to the field of artificial intelligence safety, deterministic calculation and reasoning verification. The method comprises the following steps: classifying each reasoning step generated by LLM into a deterministic step (bT: deductive reasoning, verified facts and mathematical proof) or a non-deterministic step (bF: inductive reasoning, unverified references and creative guess), and accumulatively constructing a reasoning chain; chain certainty verification chain (chain) = foldr (AND, true, chain) and time complexity O (n) are carried out in each k steps; if the bF is returned, a chain pollution elimination theorem is applied to prove that once the chain contains non-deterministic steps, the whole chain loses deterministic guarantee; and a deterministic boundary report is generated, and a non-deterministic initial position is marked. The device comprises an inference classifier, a reference verifier, a mathematical checker and a chain verification engine, and all the modules can be independently realized (formalized verification / database query / rule engine / mixed mode).

The invention discloses a method for realizing a redundant function memory chip test, which relates to the technical field of memory chip test, and comprises the following steps: calculating hyperedge coupling strength based on a hypergraph fault model, and generating a test vector sequence and a memory unit test instruction by adopting a weighted flipping mode according to the hyperedge coupling strength; injecting the test vector sequence into a tested memory chip, executing memory unit test instructions one by one, and capturing a failure unit coordinate and a failure mode category at the same time; constructing a Hall triad based on the failure unit coordinates and the failure mode category, executing theorem proving on the Hall triad by using a theorem proving device to verify the test completeness, generating an increment test vector when the verification fails, executing theorem proving again, and recording the result of the test completeness; according to the method, the hypergraph fault model is established, so that the coverage rate of non-independent faults is increased, the number of redundant test instructions is reduced, the test time and resource consumption are reduced, and the defect detection efficiency is improved.

The invention discloses an interactive theorem proving system and method based on a large language model, and the system comprises a strategy suggestion module which is used for analyzing a plurality of candidate strategies of a to-be-proven target based on LLM; the proving search module is used for performing deep reasoning based on a rule base and a plurality of candidate strategies when a to-be-proved target is a complex theorem needing multi-step strategy combination proving, and determining a complete proving path; the premise selection module is used for determining a premise sequence corresponding to the to-be-proved target based on similarity calculation when the premise needs to be cited in the proving process of the to-be-proved target, and performing theorem proving based on the premise selected by the user in the premise sequence; a reasoning strategy can be dynamically generated by utilizing a large language model, the proving process of a complex theorem is intelligently guided, manual intervention is remarkably reduced, and the automation level is improved; the reasoning path is dynamically adjusted according to the theorem target context, mathematical special situations and cross-domain proving tasks are flexibly coped, and the proving success rate and efficiency are improved.

The invention relates to the technical field of block chains, and provides an EVM instruction set abstract semantic description method and device based on a theorem prover, electronic equipment and a computer program product. The method comprises the steps of obtaining a to-be-processed EVM instruction set; and converting the EVM instruction set into a corresponding abstract semantic description based on an inductive definition method in the theorem prover. According to the method, a theorem prover with high credibility is utilized, and instruction behaviors during operation of the EVM instruction set can be accurately and completely described mathematically, so that the accuracy of abstract semantic description for the EVM instruction set is improved, and a solid mathematical basis is provided for automatic reasoning and formalized verification of the smart contract.

The application provides a kind of supervisory contract rule conflict detection method, it is related to blockchain technology field.The present application takes the supervisory contract code as input, the supervisory rules in supervisory contract are symbolized, and the supervisory rule conflict problem is converted into constraint solving problem using symbol analysis technology, theorem proving is carried out through SMT solver, and each type of conflict in supervisory rule is found, or it is proved that supervisory rule has no conflict.Specifically, it includes type analysis stage, supervisory rule symbolization stage and conflict detection stage.The present application can detect self-conflict, complete conflict, partial conflict and other rule conflict problems of supervisory contract in blockchain financial application, and provides effectiveness guarantee for realizing digitalization of supervisory rules.

The invention discloses an automatic rewriting conversion method from a function neural network operator / model to a C code, and belongs to the field of deep learning. A deep learning framework with tensor shape safety is constructed in a Coq theorem prover, and a corresponding C code is automatically generated. A neural network operator or a neural network model defined by the method can detect the tensor shape incompatibility problem and the parameter limitation incompatibility problem in the compiling stage, meanwhile, the C code is automatically generated, time-consuming and tedious manual derivation are avoided, and the development threshold is lowered.

System and methods are disclosed for providing unforgeable telemetry on computer platforms. Mathematical modeling and theorem proving are utilized to guarantee the integrity of telemetry probe execution flow and trigger, thereby preventing circumvention and tampering of logged probe data. In contrast to current state-of-the-art solutions that rely implicitly on the operating environment, this approach provides a sound and complete assurance of telemetry output. The system enables organizations to map unforgeable telemetry probe data to industry and government cybersecurity regulatory controls, ensuring compliance therewith. This invention addresses the shortcomings of existing solutions, including their vulnerability to sophisticated attacks, operational complexity, and inability to provide unforgeable telemetry data, thereby providing a reliable and accurate monitoring output in the presence of cyberattacks on computer platforms.

The invention discloses an automatic verification type code lifting method and device, and the method comprises the steps: obtaining an input source language code program, and then processing the input source language code program into Python program description which takes Python as an intermediate expression to generate a source program by using a preset GAI model; converting the Python program description into a specific grammar of a DSL (Digital Subscriber Line) based on preset pattern matching to generate a target code; the GAI model is further configured to generate an operator template of a target language according to a use manual of the target language provided in advance and the target language, and form an operator template library for pattern matching; after the target code is generated, a theorem prover is used for verifying the target code so as to check whether all program input of the target code is semantically equivalent to a source program or not; the method has the advantages that code lifting is more automatic, and generalization ability and correctness of different DSLs are higher.

The embodiment of the present disclosure discloses a method and device for formal analysis of autonomous positioning of a UAV. The method comprises: obtaining the same name image point coordinates, a preset homogeneous coordinate conversion matrix, a continuous homogeneous coordinate conversion matrix and a coordinate conversion formula, establishing a high-order logic expression of a ground target point in a geodetic coordinate system based on a high-order logic language; constructing a corresponding formal proposition based on the high-order logic expression, the formal proposition describing attribute constraint conditions in the high-order logic expression; verifying the formal proposition based on a theorem prover to determine whether the high-order logic expression meets the attribute constraint conditions. The high-order logic expression of the UAV for determining the non-homogeneous coordinates of the ground target point in the geodetic coordinate system is analyzed by the formal method, and the attribute constraint conditions that must be met by the high-order logic expression are verified, thereby ensuring the accuracy of the analysis result.

The application discloses a formal automatic theorem proving method based on an explicit mode node search tree, and has the characteristics that the method comprises the following steps: 1) formal theorem data acquisition and processing; 2) mode marking and training sample construction; 3) unified proving model training and candidate action probability under a selected proving mode; 4) construction of an explicit mode node search tree and generation of a candidate action under the selected proving mode; 5) execution and verification of a formal theorem prover; 6) updating of the unified proving model; and 7) use of the updated unified proving model for theorem proving tasks of higher difficulty levels and the like. Compared with the prior art, the application has the advantages of improving the adaptability of the model to different proving states, the solving capability in complex formal theorem proving tasks and the coordination between different levels of proving decisions, retaining high-level proving mode information in the search process, enhancing the structural expression capability of the proving process, and having good expansibility and application value.

The invention discloses an operating system concurrency control C code verification system and method based on model check, and relates to the technical field of verification, the system comprises a code conversion module and a verification module; the code conversion module converts a concurrency control C code of the target operating system into a BTOR2 model, and then converts the BTOR2 model into an AIGER model; the verification module is connected with the code conversion module and calls the model inspection tool to verify the AIGER model, so that verification of the concurrency control C code of the operating system is achieved, the C code is gradually converted into the BTOR2 model and then converted into the AIGER model through the model conversion tool chain so as to be compatible with an existing model inspection tool; a traditional theorem proving method is replaced, manual intervention is reduced, verification efficiency is improved, a counter-example path can be automatically generated, and system defects can be accurately positioned; the blank that the multi-core operating system code is verified by using a model checking method is filled, and the application of a model checking technology in the field of software is expanded.

The application discloses a kind of cooperation logic verification methods of multi-agent system, belong to artificial intelligence and formal verification technical field, to solve the technical problems in the cooperation logic verification of existing multi-agent system (especially multi-agent system), traditional simulation test exists scene coverage is not complete, deep logic defect is difficult to find, and existing formal verification method is poor in adaptability, prone to state explosion, conflict positioning is fuzzy, lack of repairable suggestion.The method is standardized formal modeling to multi-agent system, cooperation target and constraint condition are defined, and the correctness of cooperation logic is verified into a computable model checking problem, multi-dimensional verification is realized by combining theorem prover and model checking tool, and the conflict is accurately positioned for the verification failure scene and the repairable suggestion is provided, and the verification accuracy and efficiency are considered by means of distributed verification, abstract dimension reduction and other optimization methods.

System and methods are disclosed for providing unforgeable telemetry on computer platforms. Mathematical modeling and theorem proving are utilized to guarantee the integrity of telemetry probe execution flow and trigger, thereby preventing circumvention and tampering of logged probe data. In contrast to current state-of-the-art solutions that rely implicitly on the operating environment, this approach provides a sound and complete assurance of telemetry output. The system enables organizations to map unforgeable telemetry probe data to industry and government cybersecurity regulatory controls, ensuring compliance therewith. This invention addresses the shortcomings of existing solutions, including their vulnerability to sophisticated attacks, operational complexity, and inability to provide unforgeable telemetry data, thereby providing a reliable and accurate monitoring output in the presence of cyberattacks on computer platforms.

The invention discloses a CIRCT dialect form semantic construction method oriented to hardware design and a multi-layer abstract intermediate language. A K framework is used as an implementation basis of CIRCT dialect form semantics. Configuration items in the K framework can conveniently define a semantic model and a state quantity; a rewriting rule in the K framework can conveniently define operation semantics based on the state quantity; the matching logics in the K framework are parallel, so that the K framework can well adapt to concurrent simulation of each circuit instance in hardware design; rich types and rules are allowed to be defined in the K framework and can be used for adding debugging information or controlling an execution process; meanwhile, the K framework provides a python interface, so that a batch test process can be simplified, and encapsulation is provided for analog simulation of formal semantics and interaction with an external interface; the K framework provides a built-in theorem prover which can be directly used for subsequent formal verification work based on formal semantics, and the usability and application potential of the formal semantics are enhanced.

The invention discloses a formalized verification method of a memory management module and a related device, and relates to the technical field of operating system security, and the formalized verification method comprises the following steps: based on a demand document, a design document and a source code, sequentially constructing a demand layer formalized model, a design layer formalized model and an implementation layer formalized model in an interactive theorem prover, and on the basis of the demand document, constructing a demand layer formalized protocol in the interactive theorem prover, and completing the proving of the demand layer formalized protocol in the interactive theorem prover. And establishing a first refinement relationship between the design layer formalized model and the demand layer formalized model, and completing the certification of the first refinement relationship in the interactive theorem prover. And establishing a second refinement relationship between the implementation layer formalized model and the design layer formalized model, and completing the proof of the second refinement relationship in the interactive theorem prover. If the formalized specification, the first refinement relation and the second refinement relation are proved, it is judged that the memory management module passes formalized verification.

The present invention discloses a memory security verification method in automatic Java code generation based on Event‑B. Firstly, the functional requirements, environmental requirements and security requirements of the memory management system are clarified. Then, the memory management system is abstractly modeled and the core functions of the system are defined, including memory allocation, recycling and state management. The memory management process is formally described to ensure the verifiability of the system behavior. The refinement strategy starts from the initial abstract model and gradually introduces different functional requirements and security requirements for refinement. In each step of the refinement process, the model is verified. The security conversion rules from Event‑B to JML and then to Java code are constructed, and the Isabelle / HOL theorem prover is used to verify the semantics of the system behavior, so as to ensure the correctness of the memory operation in the code conversion process and realize the security conversion from Event‑B model to Java code.

The invention relates to a formal verification method and system for RISC-V multi-core SBI firmware. The formal verification method and system are mainly an automatic verification process combining an Isabel / HOL theorem prover and a heuristic search strategy. The method specifically comprises the following steps: establishing a universal hardware abstraction layer to unify an underlying resource interface, and formally describing a multi-core concurrent model and synchronous logic in Isable / HOL to strictly define the system state and transition. A * search priority ranking is performed on the state space by using a heuristic function, so that a potential problem path is quickly positioned in the complex state space. And the suspicious path is strictly demonstrated by an Isabel / HOL calling theorem proving tool, and the feedback of a failure case is used for dynamically adjusting heuristic parameters and strategies. The verification efficiency and the automation level are improved, and the state space scale is effectively controlled.

The invention relates to the technical field of block chains, and provides an EVM (Error Vector Magnitude) implementation layer semantic description method and device based on a theorem prover, electronic equipment and a computer program product. The method comprises the following steps: acquiring an EVM execution engine code to be processed; the method comprises the following steps: respectively converting execution logic of each EVM instruction of an EVM execution engine code into corresponding realization layer semantic description based on a theorem prover according to predefined data structures and instruction behaviors of various EVM instructions; according to the method, high-fidelity formalized modeling is performed on an implementation layer of an EVM execution engine code in a high-credibility theorem prover according to defined data structures and instruction behaviors of various EVM instructions, so that high-accuracy semantic description of the implementation layer can be obtained.

The invention belongs to the field of formalized verification, and provides a MedTiny language formalized verification method based on theorem proof. According to the method, a target language similar to the MedTiny structure is designed in a theorem prover Isable, so that verification of the MedTiny program is realized; a theorem proving technology is used to enable a verification result to have strict mathematical guarantee; the Hall triad is simplified according to a preset Hall triad proving rule, so that the problem that the unbounded condition of the cycle index cannot be verified is avoided; according to the technical scheme of the invention, the simplified Hall triad is verified to verify whether the final value of the verification condition obtained through calculation is true or not and whether the weakest pre-condition is contained in the pre-conditions or not is judged, so that the high automation of the verification process is realized through the theorem prover, the manpower demand of experts is greatly reduced, and the verification efficiency and accuracy are remarkably improved.

The invention discloses a formalized language-based computer interlocking software development implementation method, which comprises the following steps of: S1, writing a formalized specification by using a formalized language Z language, defining an abstract state of a system through a mode, defining an initial state, writing a Z mode for each operation, and outputting a Z protocol document; s2, performing formalized verification and theorem certification on the Z protocol document generated in the previous step; s3, if the verification is not passed, redesigning the Z protocol document, and if the verification is passed, refining the Z protocol document for multiple times; and S4, automatically generating a test case, test input and expected output covering all boundary conditions by using a Z auxiliary tool CZT in combination with a user-defined test generator according to the verified and refined Z protocol document. According to the method, the defects that ambiguity and ambiguity are caused by adopting a direct development method based on a natural language, strict logical reasoning and proving cannot be carried out, and automatic verification cannot be carried out can be overcome.

The invention provides a theorem proving premise selection method and device, electronic equipment and a storage medium, and belongs to the technical field of formalized theorem proving, and the method comprises the steps: converting each theorem, definition and lemma in a theorem library into a first expression tree; converting a to-be-proved target expression into a second expression tree; determining a plurality of similarities between each first expression tree and the second expression tree; performing fusion processing on the plurality of similarities corresponding to each first expression tree to obtain a similarity score corresponding to each first expression tree; and selecting a plurality of first expression trees with the highest similarity score as proving preconditions of the target expression. According to the method, the accuracy and efficiency of theorem proving premise selection can be improved.

The present invention relates to a formal verification method for PPTLI theorem proof based on PVS, comprising: S101: obtaining the basic timing type of PPTLI and the index expression type of PPTLI through PVS construction, and equivalently representing the linear temporal logic according to the index expression type of PPTLI; S102: obtaining the PPTLI theorem proving system through PVS construction according to the basic timing type of PPTLI and the index expression type of PPTLI; S103: expressing the PPTLI timing property to be proved as a theorem, and using the PVS interactive proof command to use the PPTLI theorem proving system to prove the PPTLI timing property to be proved. The method of the present invention uses PPTLI, a temporal logic with strong expression ability and comprehensive unity, to describe and prove the expected properties of a computer system, which can make up for the shortcomings of existing theorem proving technology to ensure the security and reliability of the system.

The invention discloses an analog circuit formalized verification method based on a Coq theorem prover, and belongs to the field of formalized verification. An analog circuit graph page developed by the invention supports drawing of a basic analog circuit composed of a power supply, a resistor and a capacitor, and interacts with a rear end by using a jsofocaml technology; the back end calls an Ocaml function to convert the analog circuit diagram information into circuit text description, and general description of an analog circuit is generated; automatically generating a template based on a predefined Coq code, and further generating Coq description from the circuit description; and introducing a circuit theorem into Coq, and carrying out circuit correctness and equivalence proving. The method supports symbolic analysis of the property of the analog circuit, ensures that the behavior of the circuit design meets the expectation, helps a user to find and eliminate potential defects in the design as early as possible, and also supports simplification of the circuit design by proving the equivalence of the circuit.

The invention discloses a heterogeneous metadata programmable, formalized and unified modeling method. The method comprises the steps of 1, feature decoupling and unified representation to form a standardized feature library, 2, programmable mode definition, 3, formalized semantic mapping and unified metadata model generation, and 4, model verification and evolution. According to the method, a heterogeneous metadata adaptation scene is improved through user-defined matching, conversion and constraint rules, an underlying framework does not need to be modified, the logic of a model is ensured and business rules are met by converting semantic description into a formalized language and combining model detection and theorem proof, the risk of data quality after integration is reduced, and the efficiency of data integration is improved. Through online incremental updating and version management, the method adapts to rapid changes of business requirements, avoids the cost problem caused by shutdown reconstruction of traditional modeling, automatically solves term conflicts through fusion of ontology reasoning and semantic embedding, and improves the efficiency of large-scale data integration.

The application discloses a kind of methods for realizing redundant function memory chip test, it is related to memory chip test technical field, including, based on hypergraph fault model calculation hyperedge coupling strength, according to hyperedge coupling strength using weighted flip mode generates test vector sequence and storage unit test instruction;Test vector sequence is injected into the memory chip to be measured, and storage unit test instruction is executed piece by piece, while capturing failure cell coordinates and failure mode category;Based on failure cell coordinates and failure mode category, Hall triplet is constructed, and theorem prover is used to execute theorem proof to Hall triplet to verify test completeness, when verification fails, generate incremental test vector, and re-execute theorem proof, record the result of test completeness;The application establishes hypergraph fault model, improves the coverage of non-independent failure, reduces the number of redundant test instructions, reduces test time and resource consumption, improves defect detection efficiency.