14 results about "Data descriptor" patented technology

Provided in the embodiments of the present disclosure are a data processing method, apparatus and system. The method is applied to a data transmission device, and comprises: in response to a data sending notification of a data processing device, acquiring a target data descriptor of target message data; when it is determined, on the basis of the target data descriptor, that the target message data requires order preservation, placing the target data descriptor in a target buffer area for ordering, so as to obtain an ordering result; and on the basis of the ordering result, acquiring the target message data from a target memory address corresponding to the target data descriptor. A message order-preserving mode is changed to reordering based on a target data descriptor, and the size of the target data descriptor is much smaller than the size of target message data, so that the usage requirements of hardware resources are effectively reduced while an order-preserving capability that accommodates a higher CPU processing latency is achieved, thereby ensuring message order-preserving and performance requirements under high-latency CPU processing.

The application belongs to the technical field of electronic evidence, and particularly relates to a full-link adaptive parallel data stream acceleration method and device and a storage medium, which comprises the following steps: monitoring the data stream state of a multi-protocol interface in real time; adopting an intelligent prefetch engine and an asynchronous decoupling pipeline to perform data reading scheduling; performing hardware parallel analysis on the data from different protocol interfaces in the physical layer and the link layer, extracting effective data load and address information, and reconstructing into a unified format data descriptor; storing the unified format data descriptor into a cache matrix; if the output rate of a device connected with the protocol interface is greater than the processing rate of a host, dynamically expanding the cache capacity of the cache matrix; when detecting that the host side is idle, initiating burst data transmission according to the maximum effective bandwidth of a PCIe interface connected with the host, and simultaneously adopting a write pointer lag control strategy to smoothly output the data stream; and through a DMA mechanism, directly writing the burst transmission data stream into the host memory bypassing the host CPU. The scheme realizes efficient electronic evidence.

The invention provides a citrus pulp feed bionic digestible energy value prediction method and system based on federal learning, and relates to the technical field of machine learning, and the method comprises the steps: obtaining a local data descriptor of each node, constructing digestion dynamic characteristics through chemical composition and three-dimensional representation, and obtaining a digestion dynamic value of each node; and initializing the physical information neural network by solving the partial differential equation of the electrical response constraint. And performing federal aggregation on the distributed parameters by adopting a geometric manifold technology to obtain a global consensus model parameter base. And generating a virtual sample through physical rule constraint, and calculating a physical consistency residual error in combination with local real data to perform model calibration. And deconstructing the predicted physical determinacy and data probabilistic part of each node to obtain final energy value prediction and uncertainty measurement. According to the method, on the premise of protecting data privacy, a physical mechanism and data driving are effectively fused, and the accuracy and reliability of prediction of the digestible energy value of the citrus pulp feed are remarkably improved.

The application provides a data message processing method and related device, the method comprises the following steps: obtaining a target descriptor and a descriptor format, and analyzing target description information in the target descriptor according to the descriptor format; obtaining a target message corresponding to the target description information, and performing offloading processing on the target message to obtain an offloaded message. In the implementation process of the above scheme, the message format corresponding to different types of device interfaces is described by using the descriptor format, and the message description information parsed from the data descriptor by using the descriptor format is used to obtain target messages of different formats, so that the offloading device can perform offloading processing on target messages of different formats, thereby effectively improving the compatibility of the offloading device.

A storage system includes a storage device including a nonvolatile memory device and a host device including a file system to generate and update a file system metadata to manage data stored in the nonvolatile memory device. The file system of the host device determines a relocation of a plurality of data blocks and transfers, to the storage device, a synchronous move request including a move data descriptor indicating information on a storage location of the plurality of data blocks and a metadata descriptor indicating information on a change in the file system metadata according to the relocation. The storage device performs a data move operation to change the storage location of the plurality of data blocks based on the move data descriptor, and a metadata update operation to write a new file system metadata according to the relocation in the nonvolatile memory device based on the metadata descriptor.

The invention provides data descriptor management of cache units, in which a control component comprises a first data descriptor RAM and can use a plurality of cache units, data block descriptors corresponding to the cache units are stored in the first data descriptor RAM, the data block descriptors comprise at least one data descriptor, and the data descriptors correspond to the cache units. The data descriptors indicate address spaces in the corresponding cache units; the control component obtains a cache unit index of a cache unit allocated for each storage command of the IO write command; determining an address of a data block descriptor corresponding to the cache unit index in the first data descriptor RAM based on the first data descriptor mapping table; obtaining all data descriptors according to the addresses of the data block descriptors; and according to the address space in the cache unit indicated by each data descriptor corresponding to the storage command, moving the corresponding data to the cache unit. According to the method, the data descriptor can be obtained without intervention of a processor, and the data descriptor can be generated without occupying extra time.

A method and system for a secured data transaction are disclosed. The method can include receiving, by a server system, transaction data and a data descriptor. The data descriptor includes information about the transaction data and a digital signature of the data descriptor. The method can further include looking up, by the server system, a public key based on the data descriptor. The method can further include determining, by the server system, whether the digital signature of the data descriptor was signed by a private key corresponding to the public key. The method can further include in response to determining that the digital signature of the data descriptor was signed by the private key corresponding to the public key, allowing, by the server system, the receipt of the transaction data.

The present application provides an address mapping unit that efficiently looks up a data descriptor of a cache unit. The address mapping unit comprises a plurality of register groups, the plurality of register groups correspond to a plurality of data block descriptor groups, the plurality of data block descriptor groups correspond to a plurality of cache unit groups, and each cache unit group comprises at least one cache unit; each register group comprises a group base address register, a group base index register and a data block descriptor mode register, and the address mapping unit accesses one of the plurality of register groups according to a group serial number of a cache unit group where the cache unit index is located to obtain a first group base address, a first group base index and a first data block descriptor mode; and calculating a data descriptor address corresponding to the cache unit index according to the cache unit index, the first group of base addresses, the first group of base indexes and the first data block descriptor mode. According to the application, mapping from the cache unit index to the data descriptor address can be realized based on the address mapping unit, hardware resources are reasonably utilized, and the cost is controlled.

The invention provides a method and a system for executing calculation in a multi-dimensional array carrying process. The method comprises the following steps: receiving a data descriptor and a carrying calculation descriptor of a multi-dimensional array issued by a superior processing core; analyzing the data descriptor to obtain array structure information; analyzing the carrying calculation descriptor to obtain a carrying starting position, a carrying block size, a carrying mode, a target address, a calculation mode and a feedback mode; generating a reading address of the source data block in the source memory according to the array structure information, the carrying starting position and the carrying mode; reading the original data block corresponding to the size of the carrying block from the source memory according to the reading address, and performing quantization or inverse quantization calculation on the original data block in the carrying process; and writing the calculated data into the target memory according to the target address. According to the method, carrying data and calculation are fused, so that the operator implementation complexity is effectively reduced, and meanwhile, the operator performance is improved in order of magnitude.

This application is directed to managing firmware control data stored in a memory device of an electronic device. The electronic device obtains a current data descriptor map (DDM) corresponding to a current version of a firmware program, and identifies, in the memory device, a prior DDM and a prior control data structure corresponding to a prior version of the firmware program. Each of the prior and current DDMs maps a plurality of data descriptors to a plurality of locations in a respective control data structure. The prior control data structure stores a plurality of prior control data items identified by a plurality of prior data descriptors. A current control data structure is automatically generated for the current version of the firmware program based on the prior control data structure, the current DDM, and the prior DDM, and stores a plurality of current control data items identified by the data descriptors.

The application discloses a communication method and device of a 4G module, computer equipment and a storage medium, and comprises the following steps: obtaining a device connection request, wherein the device connection request comprises a data descriptor; judging the device type of the current device based on the data descriptor; if the device type is a man-machine interaction device, initializing the communication mode of the current device, and using a first processing logic to perform data communication on the 4G module; if the device type is a 4G module, using a second processing logic to perform data communication on the 4G module. The technical scheme realizes the management and control of the 4G module and the man-machine interaction device, and at the same time, the communication mode of the current device is initialized to the mode most suitable for the data communication of the 4G module by initializing the communication mode of the current device, so that the data transmission rate of the 4G module is improved.

The invention discloses a composite index card generation method and system based on data descriptors and dynamic layout, and the method comprises the steps: firstly obtaining a component metadata set, constructing a unified data request load based on the data descriptors, and obtaining data in parallel through a data gateway based on an FPGA to generate an aggregated data response body; component space occupation is initialized according to layout constraint information, and dragging position calibration is achieved through an intelligent positioning algorithm of a physical and mechanical model and an FPGA coprocessor; visual drawing is carried out by using an FPGA rendering pipeline through a layered rendering architecture comprising a background layer and a dynamic layer, and finally data is mapped to a component to generate a composite index card. By means of FPGA hardware acceleration, efficient and unified acquisition and intelligent dynamic layout of multi-index data are achieved, and the problems that a traditional scheme is low in data request efficiency and poor in layout calculation real-time performance are solved.

Techniques for validating and modifying file records are disclosed. A reference specification is obtained, indicating valid data labels and data points, where each data point is classified into a data label. A semantic assessment is performed between a file record and the reference specification to determine semantically conforming data descriptors and data labels. It is then determined whether aspects of data elements associated with the data descriptors conform with correlated aspects of data points linked to the data labels. Based on the determination, a data modification workflow is triggered to transform non-conforming aspects of data elements. The file record is subsequently modified to include the transformed data elements. The present subject matter may enable automated validation and modification of file records to ensure conformity with the reference specification.

The invention discloses a DMA descriptor management-based implementation method, a management device and a readable storage medium, which are applied to DMA scenes such as PCIe and the like. A DMA descriptor is divided into a data descriptor used for big data transmission, an immediate data descriptor carrying data not larger than 16 bytes and a block descriptor used for linking descriptor blocks, and a descriptor cache FIFO and a BITMAP register indexed according to descriptor serial numbers are arranged in a DMA controller. Requests and transmissions of multiple descriptors overlap in time in conjunction with pre-fetch in advance when descriptor caches are insufficient and pipelined processing of descriptor data requesting and transmitting actions. And when it is detected that the occupied bit, the request completion bit and the sending completion bit corresponding to a certain descriptor number are all set, the number is released for cyclic multiplexing. By adopting the method, the waiting time for accessing the memory can be reduced, the DMA transmission efficiency and the bandwidth utilization rate are improved, and the method is suitable for various DMA designs on a chip and an FPGA (Field Programmable Gate Array).