7 results about "Index register" patented technology

The invention discloses low power wake-up mode detection for multiple data streams. The present application describes a technique for wakeup mode-data flow correlation by a detector to provide a trigger condition for a microcontroller in a wakeup receiver (WuRX). For example, a detector (118) includes a data packet layer (200) having a plurality of index registers (202) that are updated by sampling of a data stream (208). A sampling clock [204] is coupled to each of the plurality of index registers to independently activate each of the plurality of index registers. The shared comparator (212) then compares the updated plurality of index registers with corresponding shift registers (210) that are initialized with the alternate wake-up mode bits (220). Based on the number of matching results, the detector generates a trigger signal (228) that facilitates a change in the low-power mode of operation to the high-power mode of operation.

The present application provides an address mapping unit that efficiently looks up a data descriptor of a cache unit. The address mapping unit comprises a plurality of register groups, the plurality of register groups correspond to a plurality of data block descriptor groups, the plurality of data block descriptor groups correspond to a plurality of cache unit groups, and each cache unit group comprises at least one cache unit; each register group comprises a group base address register, a group base index register and a data block descriptor mode register, and the address mapping unit accesses one of the plurality of register groups according to a group serial number of a cache unit group where the cache unit index is located to obtain a first group base address, a first group base index and a first data block descriptor mode; and calculating a data descriptor address corresponding to the cache unit index according to the cache unit index, the first group of base addresses, the first group of base indexes and the first data block descriptor mode. According to the application, mapping from the cache unit index to the data descriptor address can be realized based on the address mapping unit, hardware resources are reasonably utilized, and the cost is controlled.

Disclosed herein are vector index registers for storing or loading indexes of true and / or false results of comparison operations in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors.

The present application relates to the technical field of quantum communication, and provides a method and system for detecting quantum attacks on continuous variable quantum key distribution, the method comprising: processing normal signals and various typical attack signals sent by a sending end at a receiving end to obtain feature vectors; in a training stage, mapping the feature vectors to quantum states through amplitude coding, introducing index registers and label registers, and constructing quantum superposition states of training samples; in a prediction stage, constructing quantum superposition states of prediction samples, calculating Gaussian kernel similarity based on inner products between the quantum superposition states of the training samples and the quantum superposition states of the prediction samples; selecting the first K training samples with the largest similarity; reading the label registers corresponding to the first K training samples with the largest similarity, and outputting final attack detection results. The method improves the security and stability of a CVQKD system.

Embodiments detailed herein relate to reduction operations on a plurality of data element values. In one embodiment, a process comprises decoding circuitry to decode an instruction and execution circuitry to execute the decoded instruction. The instruction specifies a first input register containing a plurality of data element values, a first index register containing a plurality of indices, and an output register, where each index of the plurality of indices maps to one unique data element position of the first input register. The execution includes to identify data element values that are associated with one another based on the indices, perform one or more reduction operations on the associated data element values based on the identification, and store results of the one or more reduction operations in the output register.

A processor circuit may execute a program at a current one of a plurality of privilege levels. The processor circuit may include an LSU circuit and an MMU circuit. The LSU circuit may issue memory access instructions that include load / store unprivileged instructions to be performed based on particular permissions that correspond to an unprivileged level. The MMU circuit may receive, from the LSU circuit, an address associated with a particular load / store unprivileged instruction associated with the program. Code for the particular program may be stored in a particular region of the memory circuit. Based on a determination that the current privilege level is the particular privilege level, the MMU circuit may use particular indices to determine permissions for the particular load / store unprivileged instruction. The particular indices may be specified in one or more registers associated with the particular privilege level.

A processor circuit may execute a program at a current one of a plurality of privilege levels. The processor circuit may include an LSU circuit and an MMU circuit. The LSU circuit may issue memory access instructions that include load / store unprivileged instructions to be performed based on particular permissions that correspond to an unprivileged level. The MMU circuit may receive, from the LSU circuit, an address associated with a particular load / store unprivileged instruction associated with the program. Code for the particular program may be stored in a particular region of the memory circuit. Based on a determination that the current privilege level is the particular privilege level, the MMU circuit may use particular indices to determine permissions for the particular load / store unprivileged instruction. The particular indices may be specified in one or more registers associated with the particular privilege level.