16 results about "Index register" patented technology

The invention discloses a fault processing method and device and a storage medium, and relates to the technical field of digital information transmission, and the method comprises the steps: when a communication link between a first EtherCAT slave station and a previous EtherCAT station is detected to be interrupted, when a message frame in a preset format is received, sending the message frame to a first EtherCAT slave station; judging whether a message index corresponding to the message frame is written into a message initial index register of the first EtherCAT slave station or not; if yes, modifying a circular flag bit field in the message frame from 0 to 1 to obtain a modified circular flag bit field; and the modified message frame is sent to a second EtherCAT slave station, so that the second EtherCAT slave station carries out discarding operation on the message frame based on the modified circular flag bit field, and the second EtherCAT slave station is an EtherCAT slave station which is located at the downstream of the first EtherCAT slave station and has the smallest distance from the first EtherCAT slave station. The technical problem that when link interruption occurs between slave stations in an EtherCAT protocol scene, the message continuously oscillates in a disconnected loop is solved, so that continuous oscillation of the message is prevented, and the stability and reliability of a system are improved.

The invention provides an immediate operand instruction fusion method, an immediate operand instruction fusion device, electronic equipment and a computer program product. In a renaming stage, aiming at a RAW instruction having data read-after-write RAW correlation with a first loading immediate operand instruction, according to a source logic register number index register mapping table of the RAW instruction, the first loading immediate operand instruction is subjected to data read-after-write RAW correlation; obtaining a first status bit and a first table item of a source operand of the RAW instruction; and obtaining a fusion instruction by combining the RAW instruction with a first immediate value of a first loading immediate number instruction stored in the first table item under the condition that the table item storage content corresponding to the source logic register number is determined to be the immediate value according to the first status bit. Therefore, the immediate operand is directly fused to the RAW instruction in the renaming stage by utilizing the extended register mapping table, so that the dependence of instruction fusion on the adjacent program sequence is broken, a consumer instruction can obtain the operand without waiting for the execution of the immediate operand loading instruction, and the instruction execution delay is remarkably reduced.

Provided is a processor enabling assembly code of a direct-addressing conditional-jump subroutine to be reduced. The processor includes a logic circuit executing a conditional-jump instruction of assembly code, and logically configured to: store, into an index register, an index register number that is an index to a jump-destination effective address; store jump-destination effective addresses differing from one another, or address offsets to jump-destination effective addresses differing from one another, into plural reference registers, respectively; fetch and decode a conditional jump instruction that is one instruction that quotes the index register; and then execute (S1) acquiring a jump-destination effective address or an address offset from the reference register corresponding to the index register number of the content of the index register and (S2) setting the acquired jump-destination effective address, or a jump-destination effective address calculated from the address offset, to a register serving as the program counter.

The invention discloses low power wake-up mode detection for multiple data streams. The present application describes a technique for wakeup mode-data flow correlation by a detector to provide a trigger condition for a microcontroller in a wakeup receiver (WuRX). For example, a detector (118) includes a data packet layer (200) having a plurality of index registers (202) that are updated by sampling of a data stream (208). A sampling clock [204] is coupled to each of the plurality of index registers to independently activate each of the plurality of index registers. The shared comparator (212) then compares the updated plurality of index registers with corresponding shift registers (210) that are initialized with the alternate wake-up mode bits (220). Based on the number of matching results, the detector generates a trigger signal (228) that facilitates a change in the low-power mode of operation to the high-power mode of operation.

Disclosed herein are vector index registers for storing or loading indexes of true and / or false results of conditional operations in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors in various types of operations.

The present application provides an address mapping unit that efficiently looks up a data descriptor of a cache unit. The address mapping unit comprises a plurality of register groups, the plurality of register groups correspond to a plurality of data block descriptor groups, the plurality of data block descriptor groups correspond to a plurality of cache unit groups, and each cache unit group comprises at least one cache unit; each register group comprises a group base address register, a group base index register and a data block descriptor mode register, and the address mapping unit accesses one of the plurality of register groups according to a group serial number of a cache unit group where the cache unit index is located to obtain a first group base address, a first group base index and a first data block descriptor mode; and calculating a data descriptor address corresponding to the cache unit index according to the cache unit index, the first group of base addresses, the first group of base indexes and the first data block descriptor mode. According to the application, mapping from the cache unit index to the data descriptor address can be realized based on the address mapping unit, hardware resources are reasonably utilized, and the cost is controlled.

The invention discloses a method and apparatus for performing a reduction operation on a plurality of data element values. Embodiments detailed herein pertain to reduction operations on a plurality of data element values. In one embodiment, a processor includes a decode circuit to decode an instruction and an execution circuit to execute the decoded instruction. The instruction specifies a first input register including a plurality of data element values, a first index register including a plurality of indexes, where each index of the plurality of indexes maps to one unique data element position of the first input register, and an output register. Performing includes: identifying data element values associated with each other based on an index; performing one or more reduction operations on the associated data element values based on the identification; and storing results of the one or more reduction operations in an output register.

The application provides a binary search method and system. The method comprises the following steps: providing a storage device with M entries, each of which stores a value; providing index register registers including N registers, wherein the N registers divide the storage device into N-1, N or N+1 search areas; wherein M and N are integers and N

Disclosed herein are vector index registers for storing or loading indexes of true and / or false results of comparison operations in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors.

This application describes a technique for wake-up pattern-data stream correlation by a detector to provide a trigger condition for a microcontroller in a wake-up receiver (WuRX). For example, the detector (118) includes a packet layer (200) having a plurality of index registers (202) that are updated by samples of a data stream (208). A sample clock [204] is coupled to each of the plurality of index registers to independently activate each of the plurality of index registers. A shared comparator (212) then compares the updated plurality of index registers to a corresponding shift register (210) that is initialized with a rotating wake-up pattern bit (220). Based on a number of matches, the detector generates a trigger signal (228) that facilitates a change from a low-power mode of operation to a high-power mode of operation.

The present application relates to the technical field of quantum communication, and provides a method and system for detecting quantum attacks on continuous variable quantum key distribution, the method comprising: processing normal signals and various typical attack signals sent by a sending end at a receiving end to obtain feature vectors; in a training stage, mapping the feature vectors to quantum states through amplitude coding, introducing index registers and label registers, and constructing quantum superposition states of training samples; in a prediction stage, constructing quantum superposition states of prediction samples, calculating Gaussian kernel similarity based on inner products between the quantum superposition states of the training samples and the quantum superposition states of the prediction samples; selecting the first K training samples with the largest similarity; reading the label registers corresponding to the first K training samples with the largest similarity, and outputting final attack detection results. The method improves the security and stability of a CVQKD system.

Disclosed herein are vector index registers for storing or loading indices of true and / or false results of compare operations in a vector processor. Each of the vector index registers stores a plurality of addresses for accessing a plurality of locations in an operand vector.

The invention relates to the technical field of quantum communication, and provides a quantum attack method and system for detecting continuous variable quantum key distribution. The quantum attack method for detecting continuous variable quantum key distribution comprises the following steps: processing a normal signal and a plurality of typical attack signals sent by a sending end at a receiving end to obtain a feature vector; in a training stage, mapping the feature vector into a quantum state through amplitude coding, introducing an index register and a tag register, and constructing a quantum superposition state of a training sample; in a prediction stage, constructing a quantum superposition state of a prediction sample, and calculating Gaussian kernel similarity based on an inner product between the quantum superposition state of the training sample and the quantum superposition state of the prediction sample; selecting the first K training samples with the maximum similarity; and reading the tag registers corresponding to the first K training samples with the maximum similarity, and outputting a final attack detection result. And the safety and the stability of the CVQKD system are improved.

Embodiments detailed herein relate to reduction operations on a plurality of data element values. In one embodiment, a process comprises decoding circuitry to decode an instruction and execution circuitry to execute the decoded instruction. The instruction specifies a first input register containing a plurality of data element values, a first index register containing a plurality of indices, and an output register, where each index of the plurality of indices maps to one unique data element position of the first input register. The execution includes to identify data element values that are associated with one another based on the indices, perform one or more reduction operations on the associated data element values based on the identification, and store results of the one or more reduction operations in the output register.

A processor circuit may execute a program at a current one of a plurality of privilege levels. The processor circuit may include an LSU circuit and an MMU circuit. The LSU circuit may issue memory access instructions that include load / store unprivileged instructions to be performed based on particular permissions that correspond to an unprivileged level. The MMU circuit may receive, from the LSU circuit, an address associated with a particular load / store unprivileged instruction associated with the program. Code for the particular program may be stored in a particular region of the memory circuit. Based on a determination that the current privilege level is the particular privilege level, the MMU circuit may use particular indices to determine permissions for the particular load / store unprivileged instruction. The particular indices may be specified in one or more registers associated with the particular privilege level.

A processor circuit may execute a program at a current one of a plurality of privilege levels. The processor circuit may include an LSU circuit and an MMU circuit. The LSU circuit may issue memory access instructions that include load / store unprivileged instructions to be performed based on particular permissions that correspond to an unprivileged level. The MMU circuit may receive, from the LSU circuit, an address associated with a particular load / store unprivileged instruction associated with the program. Code for the particular program may be stored in a particular region of the memory circuit. Based on a determination that the current privilege level is the particular privilege level, the MMU circuit may use particular indices to determine permissions for the particular load / store unprivileged instruction. The particular indices may be specified in one or more registers associated with the particular privilege level.