Variable reordering (Mux) instructions for parallel table lookups from registers
a technology of registers and variable reordering, applied in the field of computer instruction sets, can solve problems such as limit performance in applications, video processing, encryption, etc., and achieve the effect of widening and more parallel data processors, simple and more economical
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[0020]A one-instruction segment of a program 100, shown in FIG. 1, evaluates a function y=f(x) for sixteen values of x held together in an 64-bit “index” register R11. The function y=f(x) is evaluated by accessing a look-up Table I, which has sixteen 4-bit entries (y) at respective 4-bit addresses (x). The entries of Table I are arranged in a 64-bit “table” register R10 in little endian order, i.e., with the entry at the lowest address located at the least-significant nibble (four bits) of register R10.
[0021]The function is evaluated using a variable multiplexing instruction, MuxV 4,R10,R11,R12. As indicated by the arrows from index register R11 to table register R10, each nibble location (4-bit subword location) of index register R11 holds a table address, and thus points to a nibble location of table register R10 that holds the entry for that address. As indicated by the arrows from index register R11 to 64-bit result register R12, each nibble location of register R11 corresponds ...
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