Variable reordering (Mux) instructions for parallel table lookups from registers

a technology of registers and variable reordering, applied in the field of computer instruction sets, can solve problems such as limit performance in applications, video processing, encryption, etc., and achieve the effect of widening and more parallel data processors, simple and more economical

Inactive Publication Date: 2008-09-09
HEWLETT-PACKARD ENTERPRISE DEV LP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0013]The present invention leverages a trend in computer architectures toward wider and more parallel data processors. In consonance with this trend, it is easier (e.g., simpler and more economical) to add additional computational functional units than it is to add memory units. Where tables are placed in memory, throughput is constrained by the n

Problems solved by technology

While such lookups can be implemented at very high speeds, they can still limit performance in applications, s

Method used

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  • Variable reordering (Mux) instructions for parallel table lookups from registers
  • Variable reordering (Mux) instructions for parallel table lookups from registers
  • Variable reordering (Mux) instructions for parallel table lookups from registers

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Embodiment Construction

[0020]A one-instruction segment of a program 100, shown in FIG. 1, evaluates a function y=f(x) for sixteen values of x held together in an 64-bit “index” register R11. The function y=f(x) is evaluated by accessing a look-up Table I, which has sixteen 4-bit entries (y) at respective 4-bit addresses (x). The entries of Table I are arranged in a 64-bit “table” register R10 in little endian order, i.e., with the entry at the lowest address located at the least-significant nibble (four bits) of register R10.

[0021]The function is evaluated using a variable multiplexing instruction, MuxV 4,R10,R11,R12. As indicated by the arrows from index register R11 to table register R10, each nibble location (4-bit subword location) of index register R11 holds a table address, and thus points to a nibble location of table register R10 that holds the entry for that address. As indicated by the arrows from index register R11 to 64-bit result register R12, each nibble location of register R11 corresponds ...

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Abstract

Parallel table lookups are implemented using variable Mux instructions to reorder data. Table data can be represented in a “table” register, while the desired ordering can be represented in an “Index” register. A direct variable Mux instruction can specify the table register and the index register as arguments, along with a result register. The instruction writes at least some of the data from the table register into the result register as specified in the index register. If the entire table cannot fit within a single register, entries can be divided between two or more table registers. An indirect variable Mux instruction can specify both a table-register-select register and a subword-location-select register. Both the direct and indirect Mux instructions can be used with entry data that is divided in accordance with significance between registers. In that case, plural Mux instructions are used with UnPack instructions that concatenate portions of the table entries.

Description

BACKGROUND OF THE INVENTION[0001]The present invention relates to computers and, more particularly, to computer instruction sets. A major objective of the invention is to improve computer performance when performing large numbers of table lookups.[0002]Digital video, encryption, and code conversion are three applications in which functions of the form y=f(x) are applied repeatedly to a large number of input values. Generally, the functions applied can be expressed as mathematic expressions, but it is often more convenient to implement some functions in the form of lookup tables, with the independent variable (e.g., x) corresponding to the address and the dependent variable (e.g., y) corresponding to the contents at that address.[0003]Lookup tables are conventionally held in main memory. A table is typically organized in memory as an array of elements, where each element holds the value of one table entry. Instructions then simply specify the desired memory locations, the contents of...

Claims

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Application Information

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IPC IPC(8): G06F9/312G06F9/315G06F9/44G06T1/20
CPCG06F9/3004G06F9/30032
Inventor LEE, RUBY B.MORRIS, DALE
Owner HEWLETT-PACKARD ENTERPRISE DEV LP
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