Long Instruction Word Controlling Plural Independent Processor Operations

Abstract

This invention is a data processing apparatus which operates on instruction controlling plural processor actions. Each instruction includes a data unit section and a data transfer section. These instruction sections are independent and may include differing options. In the preferred embodiment, each instruction is 64 bits. The data unit section includes a data operation field that indicates the type of arithmetic logic unit operation and six operand fields. The six operand fields include four source data register fields and two destination register fields. The data unit (110) includes a multiplication unit (220) and an arithmetic logic unit (230). The data unit (110) may include a barrel rotator (235) for one input of the arithmetic logic unit (230). The rotated data may be stored in the first destination register instead of the multiply result. The address unit (120) operations according to the data transfer operation field. This could be a load, a store or a register to register move. Operations may be conditional based upon conditions stored in a status register (210). The status register (210) is set by a prior output of the arithmetic logic unit (230) and the instruction may specify some of the status bits protect from change. The address unit (120) preferably includes a plurality of base address registers (611), a full adder (615) and a left shifter (614). The full adder (615) may add an index as scaled by the left shifter to the base address or subtract the scaled index from the base address. The full adder (615) output may update the base address register (611), either before supply of the address or following supply of the address. The index may be recalled from an index register (612) or an immediate value. In the preferred embodiment of this invention, the data unit (110) including the data registers (200), the multiplication unit (220) and the arithmetic logic unit (230), the address unit (120) and the instruction decode logic (250, 660) are embodied in at least one digital image / graphics processor (71, 72, 73, 74) as a part of a multiprocessor (100) formed in a single integrated circuit used in image processing.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application relates to improvements in the inventions disclosed in the following copending U.S. patent applications, all of which are assigned to Texas Instruments: [0002] U.S. patent application Ser. No. 07 / 933,865 filed Aug. 21, 1992 entitled “MULTI-PROCESSOR WITH CROSSBAR LINK OF PROCESSORS AND MEMORIES AND METHOD OF OPERATION”, a continuation of U.S. patent application Ser. No. 435,591 filed Nov. 17, 1989 and now abandoned; [0003] U.S. Pat. No. 5,212,777, issued May 18, 1993, filed Nov. 17, 1989 and entitled “SIMD / MIMD RECONFIGURABLE MULTI-PROCESSOR AND METHOD OF OPERATION”; [0004] U.S. patent application Ser. No. 07 / 895,565 filed Jun. 5, 1992 entitled “RECONFIGURABLE COMMUNICATIONS FOR MULTI-PROCESSOR AND METHOD OF OPERATION,” a continuation of U.S. patent application Ser. No. 437,856 filed Nov. 17, 1989 and now abandoned; [0005] U.S. patent application Ser. No. 07 / 437,852 filed Nov. 17, 1989 entitled “REDUCED AREA OF CROSSBAR...

AI Technical Summary

Problems solved by technology

First, the computer system processor was not particularly designed for handling bit mapped graphics.

Design choices that are very reasonable for general purpose computing are unsuitable for bit mapped graphics systems.

In addition, it was quickly discovered that the processing needed for image manipulation of bit mapped graphics was so loading the computational capacity of the system processor that other operations were also slowed.

However, a useful graphics computer system often requires many functions besides those few that are implemented in such a hardware graphics controller.

Typically these hardware graphics controllers allow the system processor only limited access to the bit map memory, thereby limiting the degree to which system software can augment the fixed set of functions of the hardware graphics controller.

Each of these fields presents unique problems, but image data compression and decompression are common themes.

The amount of transmission bandwidth and the amount of storage capacity required for images and particular full motion video is enormous.

Without efficient video compression and decompression that result in acceptable final image quality, these applications will be limited by the costs associated with transmission bandwidth and storage capacity.

Images