Gate-level power consumption analysis device and gate-level power consumption analysis method based on hardware platform

Abstract

A gate-level power consumption analysis device comprises a vector capture module, a control module, a storage module and a power consumption analysis module, wherein the vector capture module, the control module and the storage module are arranged on a hardware platform, and the power consumption analysis module is arranged in a principal computer; the control module supplies a clock control signal to the work and the signal capture of the hardware platform, the vector capture module captures a real-time signal state under the clock control, the storage module is used for storing a captured signal, and the power consumption analysis module generates a gate-level waveform conversion file according to the captured signal, establishing a gate-level power consumption model and completing the power consumption analysis. Correspondently, the invention also provides a power consumption analysis method based on an on-chip system verification platform. The power consumption analysis device can evaluate the running state of the entire system before the realization of the rear end of a system on chip (SoC), can estimate the power consumption level of a tested module in real time and finally gives an entire performance index of the system. The success rate of a SoC disposable chip can be greatly improved.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a hardware platform-based gate-level power consumption analysis device and method. Background technique [0002] The power consumption of very large-scale (VLSI) integrated circuits has doubled with the development of integrated circuit manufacturing technology, and power consumption and heat dissipation have always been important factors restricting the design of integrated circuits. It not only affects the continuous working time of batteries and heat dissipation The quantity determines the cost and reliability of the chip to a large extent, and low power consumption has become an equally important design goal with area and performance. [0003] In the chip design process, power consumption analysis can be divided into several levels, from bottom to top are layout level, transistor level, gate level, register transfer level (RTL), structure level and algorithm level. T...

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Problems solved by technology

[0004] In view of the problem that the power consumption analysis tool proposed above is not perfect

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