Compression method for test data of irrational number storage test vector

Abstract

The invention discloses a compression method for test data of an irrational number storage test vector and relates to a fault coverage guided compression method for the test data of the irrational number storage test vector. The compression method comprises the following steps of firstly, generating a fault list according to a circuit structure of an integrated circuit to be tested; secondly, running an automatic test vector generation tool for faults to generate test vectors of corresponding faults; thirdly, counting the lengths of runs; fourthly, performing preliminary estimation on corresponding ranges of irrational numbers; fifthly, dichotomising the ranges of the irrational numbers, and successively approximating; sixthly, filling independent bits; seventhly, performing random test; eighthly, judging whether the fault list in the seventh step is empty or not, if the fault list is empty, turning to the ninth step, and otherwise, turning to the second step; ninthly, ending, and returning all records such as integers m and l corresponding to all the irrational numbers. According to the compression method disclosed by the invention, the coding of the irrational numbers and the generation of the automatic test vectors are combined, so that on one hand, coding numbers, corresponding to the test vectors, of easily-detected fault points are reduced, and on the other hand, the fault coverage is improved.

Description

technical field [0001] The invention relates to a method for compressing test data of irrational number storage test vectors in integrated circuit test technology, especially for built-out self-test (Built-Out Self-Test, System-on-a-Chip, SoC) The test data compression method in the BOST) method is specifically a test data compression method for irrational number storage test vectors guided by fault coverage. Background technique [0002] The development of integrated circuit technology makes it possible to integrate hundreds of millions of devices in one chip, and can integrate pre-designed and verified IP, such as memory, microprocessor, DSP, etc. This diversified integrated chip has become an integrated system capable of processing various information, and is called a system-on-chip or system-on-a-chip. SoC greatly reduces the system cost, shortens the design cycle, and speeds up the time to market, but the testing of SoC products faces more and more challenges, such as:...

AI Technical Summary

Problems solved by technology

[0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, it can only be tested through the limited input / output pins of the chip, and the internal nodes of the chip are difficult to directly control or observe through macroscopic mechanical devices;

[0004] 2. Automatic test equipment (ATE) is expensive, and the development speed of chip design and manufacturing technology is faster than that of ATE. The clock frequency of the chip has exceeded the frequency of the most advanced ATE at present, and full-speed testing cannot be performed;

[0005] 3. The amount of test data is large. The more IP integrated in the SoC, the greater the amount of test data required

Yet exist in this invention: (1) before searching for irrational number, just all irrelevant bits are filled, reduce the flexibility of algorithm, also reduce the probability of finding the irrational number; The calculation method has a large amount of calculation and a long running time; (3) the irrational number encoding is not combined with the automatic test vector generation

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