The present invention relates to the field of
chip testing technology, and in particular to a test generation method, device, equipment and storage medium for eliminating redundant faults, wherein the method determines whether redundant fault
elimination is currently required through
system operation data, thereby increasing the success rate of dynamic streamlining in test generation, reducing the generated test vectors, and when the
test vector is generated, all faults in a
fault list are judged through a
single fault test generator, and when the selected main fault cannot generate a test cube, the main fault is eliminated, and when the main fault can generate a test cube, a test cube is generated for the main fault, and a fault is randomly selected from the remaining faults in the
fault list as a secondary fault, and bits are filled in the test cube through the secondary fault to generate a
test vector, thereby solving the current test generation scheme. Since redundant faults are not eliminated, the
system has a low ability to streamline vectors, resulting in a long
running time and a large number of test vectors.