Automatic reliability evaluation system and evaluation method based on Zynq FPGA

A technology for evaluating systems and reliability, applied in fault hardware testing methods, detecting faulty computer hardware, instruments, etc., can solve problems such as expensive equipment, inability to obtain statistical conclusions, and few faults, and achieve the effect of fast fault injection process.

Active Publication Date: 2020-12-01
HOHAI UNIV CHANGZHOU
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  • Application Information

AI Technical Summary

Problems solved by technology

Software-based fault injection technology needs to modify the code executed in the processor to support fault injection and fault observation, and the speed is limited by the operating frequency of the processor, which is intrusive to the code
Fault injection techniques base

Method used

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  • Automatic reliability evaluation system and evaluation method based on Zynq FPGA
  • Automatic reliability evaluation system and evaluation method based on Zynq FPGA
  • Automatic reliability evaluation system and evaluation method based on Zynq FPGA

Examples

Experimental program
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Embodiment 1

[0049] Take the 1024-point FFT implemented on the STM32F407ZGT6 processor as an example, such as figure 2 As shown, an automated reliability evaluation system based on ZynqFPGA is designed and tested, and the system framework for reliability evaluation of 1024-point FFT is as follows: figure 1 As shown, it includes the test system, FPGA control unit and PC-side fault reading module. The test system includes an on-chip debugger based on the JTAG interface, wherein the JTAG interface is used to link to the control unit JTAG controller; the on-chip debugger based on the JTAG interface includes four parts: data registers, instruction registers, interface ports and control modules. Each data register is associated with some part of the circuit. These data registers read information from the relevant circuit parts or provide input data. The test command loaded into the instruction register indicates the action to be performed and selects the data register to be used. . Data and ...

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PUM

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Abstract

The invention discloses an automatic reliability evaluation system and evaluation method based on a Zynq FPGA. The system comprises a test system, a Zynq FPGA control unit and a PC terminal fault reading module. The test system comprises an on-chip debugger based on a JTAG interface. The on-chip debugger is connected with a JTAG controller in the Zynq FPGA control unit through a JTAG interface; the Zynq FPGA control unit comprises a fault list module, a standard result module, a JTAG controller, a fault injection controller and a debugging instruction module. And the PC end fault reading module is connected with the fault injection controller through the PS end of the Zynq FPGA control unit and is used for reading and counting fault classification results stored in the fault controller. According to the invention, the communication between the test system and the software debugging tool is not necessary, so that the fault injection process is faster; a test system does not need to be modified in the fault injection method, so that the method is non-invasive; and the JTAG is one of the most common on-chip debugging interfaces, so that the JTAG can be applied to various different processors.

Description

technical field [0001] The invention relates to an automatic reliability evaluation system and evaluation method based on Zynq FPGA, belonging to the field of integrated circuit reliability research. Background technique [0002] For applications that work in harsh environments and have high requirements for safety, it is very important to ensure their reliability. With the advent of ultra-deep submicron process technologies, reliability assurance has also become an issue for a growing number of applications that are affected by radiation even at the Earth's surface. Therefore, hardening is required during the circuit design process, including protection measures against SEU effects, and reliability evaluation is a key factor to measure the effectiveness of all hardening techniques and find sensitive areas of the circuit. The so-called sensitive area refers to the single event upset fault (SEU) caused by space radiation in the outer space environment. This fault will cause ...

Claims

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Application Information

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IPC IPC(8): G06F11/22G06F11/263
CPCG06F11/221G06F11/2273G06F11/263Y02P90/02
Inventor 王海滨刘骏杨黄镱陈旭
Owner HOHAI UNIV CHANGZHOU
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