The present application provides a
chip verification system, method and
verification device based on a generative constraint model. After the model generation module of the
system obtains a
test case in text form, it determines the generative constraint model by
parsing the
test case. The model includes constraint conditions for testing the to-be-tested functions of the
chip and register configuration values of the registers for executing the to-be-tested functions. The register configuration module configures the register configuration values into the registers according to the constraint conditions so that the
chip design module can execute the to-be-tested functions. The
data transmission module receives the result after executing the to-be-tested functions and compares the result with the
standard result for each sub-module. The entire
simulation process runs on a hardware accelerator, and a
simulation report is generated after the operation ends. Through the present application, the testing of the chip functions can be realized, and the test cases applied are in text form, so that the test cases can be obtained without compiling the code, improving the efficiency of obtaining the test cases and correspondingly improving the efficiency of chip
verification.