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Random number validation method for processor arithmetic logic unit instruction

A technology of arithmetic logic unit and verification method, which is applied in the field of random number verification of processor arithmetic logic unit instructions, and can solve the problems of low random pertinence, low error coverage, etc.

Active Publication Date: 2015-03-25
NO 771 INST OF NO 9 RES INST CHINA AEROSPACE SCI & TECH
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  • Abstract
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AI Technical Summary

Problems solved by technology

[0003] Processor off-line random verification is currently the mainstream method for processor verification. Its higher-level implementation has an irreplaceable position at the system-level verification level. It will lead to low error coverage, and the development of a large number of verification use cases will also bring great verification costs

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  • Random number validation method for processor arithmetic logic unit instruction
  • Random number validation method for processor arithmetic logic unit instruction
  • Random number validation method for processor arithmetic logic unit instruction

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Embodiment Construction

[0021] The present invention will be further described in detail below in conjunction with specific embodiments, which are explanations of the present invention rather than limitations.

[0022] see figure 1 , the random number verification method of the present invention comprises:

[0023] Step 1, divide the W bit / word length of the operand storage unit according to the operation instruction operand length L and the test workload, and select the data background;

[0024] For W=2 n bit / word memory, take log 2 W+1 data background, if W≠2 n ,Pick Bit / word data background, and select the W bit in this group of data background;

[0025] Step 2. According to the "word"-oriented March C-algorithm principle, the selected data background is reversed. The March algorithm repeatedly reads / writes 0 or 1 for each address, and according to the data background generation principle, selects The data background and its inverted data ensure that the test codes between each two bytes ap...

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Abstract

Disclosed is a random number validation method for a process arithmetic logic unit instruction. Firstly, according to the length of operands of the arithmetic instruction, a March element sequence is selected, an operand storage unit is divided, then, the March element sequence is used for carrying out full-permutation filling on an operand unit, a set of alternative random numbers are generated, secondly, the alternative random numbers are used, an operand combination is generated according to the arithmetic logical operation instruction format, the generated operand combination is instantiated into arithmetic logical operation instruction codes, an arithmetic logical operation standard result is generated, and automatic comparison validation is carried out. According to the writing-in and reading-out relation of a test case, the random numbers are selected in a targeted manner to cover fault codes inconsistent in writing-in and reading-out, a processor is analogized as a storage to be tested, a mature storage test method is introduced into a processor test, pertinence of the random number validation is improved, and the validation cost is reduced at the same time.

Description

technical field [0001] The invention relates to a method for verifying off-line functions of a processor, in particular to a method for verifying random numbers used for instructions of a processor arithmetic logic unit. Background technique [0002] At present, the design and application of SoC has become the main focus and direction of IC development. Domestic SoC technology is developing rapidly, and a series of domestic SoC chips have been successfully designed. However, domestic SoC chips must be recognized and promoted by the domestic industry. More in-depth and comprehensive test verification is still required in terms of functional reliability, especially the functional verification of the processor instruction set should be put at the top of the reliability verification work. [0003] Processor off-line random verification is currently the mainstream method for processor verification. Its higher-level implementation has an irreplaceable position at the system-level ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/22
Inventor 宁宁游军许辉勇宫瑶
Owner NO 771 INST OF NO 9 RES INST CHINA AEROSPACE SCI & TECH
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