Generation and verification method of test vector

Abstract

The invention relates to a generation and verification method of a test vector. A simulation environment is established by utilizing hardware description language, the changes of signals to be recorded can directly recorded into a designated file according to the requirements of vector format of an automatic test device during the simulation, corresponding input excitation can be added to a hardware model by reading back the contents of the file, output is compared to realize verification on a recorded test vector, the test vector required by ATE (automatic test equipment) is directly generated during the simulation and verified by simulation, and manual processing is not required, therefore, the whole process is simplified, the production efficiency is improved and the generation and verification method can be used for testing a digital integrated circuit.

Description

technical field [0001] The invention belongs to the field of integrated circuit testing, and in particular relates to the generation and verification of functional test vectors for testability design. Background technique [0002] At present, usually for integrated circuit testing, functional test vectors need to be provided when performing functional testing on ATE. The existing technology is to use the VCD file generated during functional simulation, perform format conversion and manual processing through certain tools, and generate the VCD files for ATE. required test vectors. Since the VCD file is based on event recording, any flip of the signal during the simulation process will be recorded in the VCD file, so some glitches during the simulation process will also be recorded. However, ATE is limited by the length of the test cycle, and these glitches are not allowed in the test vector. These burrs need to be removed through manual processing of VCD files, which is slo...

AI Technical Summary

Problems solved by technology

Although scripts such as perl can be used to process, but for different projects, the number of signal names is different, the ATE and test environment used are different, the versatility of the script is poor, and there is still a large workload

Except for the actual use of the test vectors generated by the VCD file, it is impossible to verify whether the test vectors are converted correctly. In the application, the time of the ATE machine may be wasted due to the problem of the test vectors, and the work efficiency is low.

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