52 results about "Functional simulation" patented technology

A computer-implemented method for simulating an aircraft system in a closed-loop functional simulation environment is disclosed. The computer-implemented method may include: receiving, at a computer system, one or more control inputs from an interface; processing, by a control system model, the one or more control inputs to generate one or more system command signals; applying the one or more system command signals to one or more virtual system models; simulating a physical response of the aircraft based on output generated by the one or more virtual system models in response to application of the one or more system command signals; generating, responsive to monitoring the output generated by the one or more virtual system models, sensor data; transmitting the sensor data to the control system model; and outputting simulation results, wherein the simulation results at least comprise an indication of the physical response of the aircraft.

The invention provides a communication satellite verification system based on a general virtual test environment. The communication satellite verification system comprises a service subsystem and virtual test equipment, the service subsystem comprises a power supply and distribution subsystem ground device, a measurement and control and comprehensive electronic subsystem ground device, a thermistor equivalent device, a general control device with an MTP server and the like, and the general control device is responsible for telemetering data processing and remote control instruction scheduling; and the virtual test equipment is connected with the service subsystem, is used for simulating a satellite-borne software operation environment and a satellite-borne load to form a closed-loop test, comprises a plurality of simulation modules such as orbit and attitude dynamics, and respectively realizes orbit attitude parameter calculation, software code operation simulation and circuit box function simulation so as to test a satellite or a verification platform. The invention further provides a satellite-borne software verification method. Therefore, communication satellite verification can be carried out under the virtual condition, the test comprehensiveness can be ensured, and the test cost can be reduced.

A method for generating a real-time test environment activity view for a functional simulation is described. In some embodiments, the method includes retrieving a unique identifier (ID) associated with each of a plurality of testbench components present in a test environment from a real-time test environment activity viewer log file. The method further includes iteratively fetching from the real-time test environment activity viewer log file, a set of information corresponding to an activity associated with each of the plurality of testbench components based on the associated unique ID. The method further includes contemporaneously generating at each iteration, a real-time test environment activity view for each of the plurality of testbench components based on the associated set of information. The method further includes contemporaneously rendering at each iteration, the real-time test environment activity view for each of the plurality of testbench components via a Graphical User Interface (GUI).

This application relates to the technical field of voltage regulation function testing for power banks. It discloses a voltage regulation function simulation testing system and method. This application constructs a voltage regulation function simulation testing system including a simulation clock and a simulation cycle counter. At the software level, it directly simulates the passage of time and the accumulation of charge-discharge cycles during long-term battery use based on user-configured test parameters. The core algorithm layer uses simulation time and / or the number of simulated full-charge cycles to simulate the charging voltage of the power bank over time and the accumulation of charge-discharge cycles, thus completing the voltage regulation function simulation test of the power bank. This method of completing the voltage regulation function simulation test of a power bank through software simulation algorithms greatly reduces the physical testing time required without changing the physical testing environment or replacing the tested object. This significantly shortens the testing cycle while ensuring the test results accurately reflect real-world usage scenarios and have high reliability.

The application belongs to the technical field of intelligent driving and provides a simulation scene generalization method and system for adaptive intelligent driving functions and an application, which comprises the following steps: obtaining an initial data set of scene dimension parameters based on the type of an intelligent driving function and querying a mapping table; taking the initial data set and first feedback information as inputs, generating a candidate scene parameter set of a current iteration round through a weighted Gaussian distribution; wherein, the first feedback information is initial feedback information at the first iteration; the first feedback information is updated feedback information dynamically generated according to the simulation result of the last iteration round at the non-first iteration; performing multidimensional scene effectiveness evaluation on the candidate scene parameter set of the current iteration round, and screening out effective scene parameters; generating an executable scene file based on the effective scene parameters, performing intelligent driving function simulation, and obtaining a current round simulation result. The application can solve the problem that the existing simulation scene generalization method cannot adaptively generate scenes for intelligent driving functions.

The application discloses a kind of dynamic generation method, device, computer equipment and storage medium of insurance data, applied in the field of financial technology, can optimize the premium of group clothing insurance and the problem of responsibility identification.The method comprises: generating body shape risk index matched with body clothing according to human feature data;According to human posture data, generate posture compliance rate under quasi posture;According to the image of trying on, generate evidence chain data corresponding to loss determination;According to the functional simulation cooperation data of many people trying on, generate interactive wear and tear risk index for determining responsibility data;According to the body shape risk index, posture compliance rate, evidence chain data and interactive wear and tear risk index, dynamically generate the required insurance data.The application makes premium pricing more suitable for real risk, avoids the imbalance of interests between the two parties caused by previous extensive evaluation, reduces disputes and time consumption in claim settlement, makes responsibility division have rules to follow, and resolves long-term disputes caused by previous rule ambiguity.

The invention discloses a transformer area JP cabinet training device, which belongs to the technical field of power system operation and maintenance training, and comprises a cabinet body, and a main circuit module and a compensation metering and control module which are integrated in the cabinet body, and the main circuit module and the compensation metering and control module are fixed in the cabinet body through a fixing frame and a fixing plate. The fixing plate is fixed at the bottom of the cabinet body through bolts. The core of the device is that full-function simulation layout is adopted, quick replacement of core devices is achieved through modular quick replacement design so as to adapt to JP cabinets of different models, and the problems that in traditional training, authenticity is insufficient, safety is poor, the device cannot adapt to equipment of multiple models, and fault setting is single are solved; efficient and safe whole-process operation and maintenance skill training close to actual combat is realized.

The present disclosure provides a chip verification method, system, storage medium and computer program product. The chip verification method comprises: creating a flow control text and setting a parsing sequence in a test case, wherein the parsing sequence corresponds to the flow control text, the flow control text comprises an operation command and a control parameter corresponding to the operation command; executing the test case in a simulation environment to perform functional simulation verification on a chip under test, and adding a simulation checkpoint in the process of the functional simulation verification; after the simulation ends, in the case where the test case needs to be modified, modifying at least one of the operation command and the control parameter in the flow control text to obtain a modified flow control text; and starting from the simulation checkpoint, executing the test case again, and in the process of executing the test case, parsing the modified flow control text by using the parsing sequence, so as to execute the test case based on the modified flow control text.

This invention discloses a simulation method and system for the operation of a variable frequency drive unit in a refrigerated container. The method includes constructing a simplified simulation model and setting initial system parameters; periodically calculating the real-time values ​​of evaporation and condensation pressures based on refrigerant flow balance using the simplified simulation model; determining the target evaporation pressure based on the operating mode and the container temperature, and dynamically adjusting the opening value of the electronic expansion valve using a proportional-integral (PI) control algorithm based on the real-time evaporation pressure to bring the evaporation pressure close to the target evaporation pressure; calculating the periodic change in the container temperature based on the compressor speed, evaporator fan speed, and container temperature control deviation, and obtaining the return air temperature and supply air temperature based on the container temperature; and finally displaying the results through a human-machine interface. This invention effectively overcomes the problems of high maintenance and testing costs, unintuitive teaching simulations, lack of process control logic, and difficulties in simulating advanced functions in existing technologies.

Currently, complex FPGA designs typically contain multiple sub-modules below the top-level module. These modules ensure correct functional implementation, but because they are integral parts of the design, they are also subjected to gate-level behavioral simulation during simulation. If a module under test has one top-level module and nine sub-modules, seven of which are library or mature modules, and only two are newly designed modules, then only 30% of the gate-level behavioral simulation computation performed by EDA tools is truly for the part we want to verify. However, due to the existence of the top-level code and the need to verify the interface relationships between modules, the verification of sub-modules cannot replace the verification of the top-level module. If we could allow gate-level behavioral simulation to skip library and mature modules, it would significantly reduce the computational load of gate-level behavioral simulation and improve the speed of FPGA code functional simulation. This invention, for functional verification of FPGA code containing multiple sub-modules, uses a C model to replace the library IP modules or mature modules, preventing these modules from participating in the gate-level behavioral simulation during functional simulation execution, thereby significantly shortening the functional simulation execution time and accelerating the functional verification speed of FPGA code.

A method of function simulation for electronic devices and a functional simulation system using the same method are provided. The method includes: obtaining a computer aided design file of the electronic device, wherein the computer aided design file includes a three-dimensional object; segmenting a first face of the three-dimensional object into a plurality of first meshes; identifying the three-dimensional object as a functional component according to the plurality of first meshes; and outputting information of the functional component.

The utility model belongs to the technical field of aircraft ground tests, and particularly relates to a multifunctional simulation test platform. Comprising a socket, a first coupler, a second coupler, a box-type coupler and a test turntable, the socket, the first coupler and the second coupler are sequentially connected through a bus cable and are used for 1553B bus communication; the sub-line end of the second coupler is connected with inertial navigation, so that the simulation test of the inertial navigation scene without going to the rotary table is realized; the bus end of the second coupler is connected with a box-type coupler, the box-type coupler is connected with a 1553B interface under the rotary table, the 1553B interface on the rotary table is connected with a bus interface at one end of the box-type coupler on the rotary table, a bus interface at the other end of the box-type coupler on the rotary table is connected with a terminal resistor, and the sub-line end of the box-type coupler on the rotary table is connected with an inertial navigation. The simulation test of the inertial navigation upper turntable scene is realized. According to the utility model, hardware resources and preparation time before test are saved, and project development requirements are ensured.

The embodiment of the invention discloses a command scheduling strategy verification method and device, equipment, a medium and a product, and relates to the field of chip verification. The method is applied to the computer equipment and comprises the steps that in the function simulation stage of chip verification, multiple target commands scheduled by memory control logic of a memory controller are determined, and the target commands are obtained by scheduling memory read-write commands by the memory control logic according to a command scheduling strategy; the memory read-write command is used for simulating a command sent to the memory controller by the command sending component; under the condition that multiple target commands scheduled by the memory control logic of the memory controller meet a scheduling optimization condition, it is determined that the command scheduling strategy is successfully verified, and the scheduling optimization condition is a condition for optimizing the memory read-write performance between the memory and a command sending assembly; and under the condition that at least one target command scheduled by the memory control logic of the memory controller does not meet the scheduling optimization condition, determining that the command scheduling strategy verification fails.

The application discloses a simulation verification system and method supporting multiple verification scenes, and relates to the technical field of chip design verification.The system comprises: a unified verification environment, which is constructed based on the same verification methodology, is connected with design code through an interface, and provides test excitation; a mode configuration module, which is used for receiving user instructions, controls the simulation verification system to switch between register transfer level function simulation mode, zero-delay gate level simulation mode and gate level post-simulation mode with timing reverse markers, and realizes mode switching through predefined macro definition; an environment reuse module, which is used for reusing the verification environment and test cases in different simulation modes; and a result analysis and comparison module, which is used for collecting and comparing simulation results in different simulation modes.The application can integrate multiple simulation modes, realize seamless switching and high reuse of the verification environment, simultaneously consider simulation speed and timing accuracy, and significantly improve the verification efficiency and quality of complex chip design.

The invention provides a distributed virtual-real fusion remote debugging verification system and method. The system comprises an all-digital environment, a semi-physical environment, a distributed data exchange system, a virtual-real simulation cooperative control system and a remote development debugging system. Respectively executing software function simulation and hardware-in-the-loop test in the full-digital environment and the semi-physical environment; the distributed data exchange system realizes data exchange between each environment and an external simulation node; the virtual-real simulation cooperative control system uses a synchronization command and a response mechanism to ensure time sequence synchronization; the remote development and debugging system adopts a cloud-edge-end framework to realize remote control of an all-digital environment and a semi-physical environment. The virtual-real fusion simulation system realizes remote centralized management and cooperative control, breaks through regional restrictions, improves the resource utilization rate and cooperation efficiency, can be seamlessly integrated to an automatic development process, and solves the technical problems that an existing virtual-real fusion simulation system is difficult in remote cooperation, dispersive in resource management and incapable of being fused into the automatic development process.

The utility model provides a visual portable multifunctional product simulator. The visual portable multifunctional product simulator comprises a structural shell, a display screen, a button and a control circuit board arranged in the structural shell, the control circuit board at least comprises a bottom plate, a display control unit, a button input unit, a power supply unit, a debugging interface and at least one function simulation unit; the function simulation unit at least comprises a power supply signal detection circuit, a pulse signal detection circuit, a detection and control linkage resistance voltage output circuit, a communication detection circuit and a control module. Through arrangement of the function simulation module, electrical performance parameters of a real product are met, signal receiving and outputting conditions of the product in a real test process are completely simulated, and potential hazards of dangerous parts are avoided; meanwhile, a visual operation interface design is adopted, so that the accuracy of each electrical parameter can be observed in the whole machine joint debugging process, and the visualization of the electrical parameters in the joint test process is realized; the device can be repeatedly used, and the test cost is reduced.

The application discloses a kind of based on MBSE joint simulation technology's cabin ventilation system design method, first obtain the heat and air consumption parameter of ship cabin equipment, synchronization to the SysML system model based on MBSE construction;System function and performance requirement are analyzed by requirement modeling, and parameter modeling obtains the ventilation and cabin target environment parameter requirement;Design system physical architecture, complete function decomposition and sub-equipment distribution, and the architecture feasibility is verified by function simulation;Performance simulation model is constructed, and the optimal scheme is selected by simulating actual working condition, and the performance feasibility is verified by long-time simulation;Finally complete system three-dimensional digital design and space arrangement, and complete design after verifying space feasibility.The application realizes cabin ventilation system whole-process model-driven design, significantly improves design efficiency and reliability, reduces design rework risk.

This invention relates to the field of enzyme network analysis technology, specifically a robust system for analyzing the functional balance of a multifunctional enzyme regulatory network. The system includes a network topology analysis module, a graph generation module, a flux balance analysis module, a functional simulation module, a robustness curve fitting module, and a report generation module. It identifies key nodes and vulnerable paths in the target regulatory network; constructs a structural feature association graph; performs flux balance analysis on the target regulatory network to obtain functional flux distribution data; simulates the functional operation of the target regulatory network and quantifies the output efficiency of the simulation results to obtain the core function maintenance degree; fits the perturbation trend of the core function maintenance degree to obtain a functional balance robustness curve; and analyzes the decay mode of the functional balance robustness curve to generate a robustness analysis report of the target regulatory network. This invention can improve the efficiency of functional balance robustness analysis of a multifunctional enzyme regulatory network.

The application discloses a kind of craniofacial prosthesis systems based on digital simulation, specifically relates to digital simulation technical field, can preliminary predict and fine adjustment the three-dimensional image of bone defect area by mirror flip, functional area division and adjustment based on functional index, to more accurately reflect actual bone defect situation, provide strong support for subsequent repair scheme design;Through simulation simulation craniofacial movement and function, predict the functional recovery after bone defect repair, and output function simulation quality index, so that user can intuitively understand the repair effect, provide basis for treatment decision;Joint analysis surface smoothness index, function simulation quality index and simulation bone quality evaluation index, output bone reconstruction availability coefficient Ks;Judge the relationship between bone reconstruction availability coefficient and corresponding threshold Tza;Solve the problem that prior art cannot scientifically provide decision support for craniofacial prosthesis.

The application discloses a kind of simulation flight data determinacy communication demonstration system based on time sensitive network, including by end system and switch form airborne network, demonstration manager and network tester.Demonstration manager is used to set the simulation parameter of end system and switch.Simulation end system has flight simulation application module, interface service module and network driver module;It is the interaction of simulating the flight data stream of real end system in time sensitive network;Through simulating periodic flight data, the flight state synchronization interaction of application layer is simulated, the data frame of data link layer is configured and encapsulated guarantee, and the communication function of simulation end system is simulated.Simulation switch has switching module and TSN protocol configuration module;It is according to scheduling or forwarding logic processing data frame.

This disclosure provides a method and system for large-scale model-assisted logic function simulation and verification for hardware design, relating to the fields of artificial intelligence and hardware design technology. The method includes: performing logical perception analysis on hardware design specifications to generate a structured design analysis report; based on the design analysis report and design specifications, using a generator agent to initially generate a testbench, obtaining an initial test platform and a reference design under test set; simulating the initial test platform and the reference design under test set, and verifying the initial test platform using a consensus verification mechanism based on confidence levels; iteratively refining the test platform using a corrector agent based on a structured reflection report to obtain the final optimal test platform; and automatically generating a retrieval knowledge base precisely aligned with hardware semantics using a reflexive domain knowledge mining method, achieving fully automated construction of the hardware domain knowledge base. This disclosure achieves fully automated system-level hardware design testbench generation and verification.

This invention introduces a simulator supporting asynchronous communication interfaces, relating to the field of chip simulation and debugging. The simulator comprises four parts: a chip function debugging module, a chip function simulation module, a register module, and a timing interface module. It reuses the chip's system RAM to store data transmitted and received by the communication interface. The addition of the register module and timing interface module implements a parallel master interface for asynchronous communication. The simulator adopts an asynchronous parallel interface design with master-slave device handshaking, ensuring compatibility with interface devices of various speeds while maximizing communication speed. This invention designs a simulator supporting asynchronous communication interfaces, enabling interface expansion for debugging functions, accelerating chip program debugging, and improving development efficiency.

The invention discloses a simulation verification system and method supporting multiple verification scenes, and relates to the technical field of chip design verification, and the system comprises a unified verification environment which is constructed based on the same verification methodology and is used for being connected with a design code through an interface and providing test excitation; the mode configuration module is used for receiving a user instruction and controlling the simulation verification system to be switched among a register transfer level function simulation mode, a zero delay gate level simulation mode and a gate level post-simulation mode with a time sequence inverse mark, and the mode configuration module realizes mode switching through predefined macro definition; the environment multiplexing module is used for multiplexing a verification environment and a test case in different simulation modes; and the result analysis and comparison module is used for collecting and comparing simulation results in different simulation modes. According to the method, multiple simulation modes can be integrated, seamless switching and high multiplexing of verification environments can be realized, the simulation speed and the time sequence precision are considered, and the verification efficiency and quality of complex chip design are remarkably improved.

The embodiment of the application discloses a kind of based on function simulation architecture vulnerability factor calculation method and device, the method comprises: according to circuit design source file, circuit compilation is generated simulation data and circuit topology chart;According to test excitation and simulation data, function simulation is formed at each simulation time simulation result data;Simulation result data is backfilled into circuit topology chart, determines the visible input end information of each signal node in circuit under each simulation time;The visible input end information of each signal node under each simulation time is summarized and analyzed, determines the target time window that each signal node corresponding soft error can be observed;For each signal node, the proportion of its corresponding target time window in entire simulation period is calculated as the architecture vulnerability factor data of this signal node.The application greatly reduces the time overhead required for AVF data calculation, effectively improves the calculation efficiency of AVF data.

The invention discloses a cranio-maxillofacial repair system based on digital simulation, particularly relates to the technical field of digital simulation, and can preliminarily predict and finely adjust a three-dimensional image of a bone defect area through mirror image overturning, functional area division and adjustment based on functional indexes, so that the actual bone defect condition is reflected more accurately. Powerful support is provided for the design of a subsequent repair scheme; by simulating the movement and function of a craniomaxillofacial surface, the function recovery condition after bone defect repair is predicted, and a function simulation quality index is output, so that a user can intuitively understand the repair effect, and a basis is provided for treatment decision making; performing conjoint analysis on the surface smoothness index, the functional simulation quality index and the simulation bone quality evaluation index, and outputting a bone reconstruction availability coefficient Ks; judging the relationship between the bone reconstruction availability coefficient and a corresponding threshold Tza; the problem that decision support cannot be scientifically provided for craniomaxillofacial repair in the prior art is solved.

The invention provides a cardio-pulmonary resuscitation dummy control method and system based on AED, and relates to the technical field of dummy training. The AED-based cardio-pulmonary resuscitation simulation human control system comprises an upper computer, the upper computer is in bidirectional connection with a data transmission module, the data transmission module is in bidirectional connection with a simulation human body and an AED training machine, the simulation human body is in bidirectional connection with a function simulation module and a data detection module, and the AED training machine is in bidirectional connection with the function simulation module and the data detection module. The upper computer comprises a data acquisition module and an analog control module, and the data acquisition module is connected with a data analysis module. By adopting a form of combining a simulation person main body with a plurality of different data detection modules, all related data of a defibrillation process and a subsequent cardio-pulmonary resuscitation process of the AED training machine can be detected and collected, whether related operations of a trainer in the whole operation process meet requirements or not is judged, simulation of the whole training process is realized, and the training efficiency is improved. And when the whole device is used, the application range is wider, and the practicability is higher.

This invention relates to the field of ophthalmology, and more particularly to a method, software system, device, and storage medium for constructing a digital twin eye model. The construction method includes: acquiring multi-source input data of the target eye; performing three-dimensional reconstruction to obtain the anterior and posterior segment three-dimensional structures; constructing a virtual three-dimensional structure of the intermediate segment based on axial length data and the anterior and posterior segment three-dimensional structures as constraints; fusing these data to form a full-eye three-dimensional geometric model; and mapping relevant characteristic measurements to corresponding regions in the full-eye three-dimensional geometric model to construct the digital twin eye model. This invention systematically solves three core problems: "full-eye modeling," "gold standard replacement," and "functional simulation," ultimately producing a complete, accurate, usable, and reliable digital twin eye model, providing a revolutionary technical means for precise research, in vitro simulation, disease prediction, and prevention of ophthalmic diseases.

Embodiments of the present application provide a circuit test method and device. The method comprises: compiling a to-be-tested circuit to obtain first compilation information, the first compilation information comprising a plurality of first resource positions corresponding to the to-be-tested circuit; compiling a reference circuit corresponding to the to-be-tested circuit to obtain second compilation information, the second compilation information comprising a plurality of second resource positions corresponding to the reference circuit; determining functional difference information between the to-be-tested circuit and the reference circuit according to the first compilation information and the second compilation information; and determining a test result corresponding to the to-be-tested circuit according to a target function corresponding to the to-be-tested circuit, a reference function corresponding to the reference circuit, and the functional difference information. The test result corresponding to the to-be-tested circuit can be determined only through functional simulation verification. Therefore, the verification efficiency of the to-be-tested circuit is improved and the verification period is shortened.

This invention relates to a camera function testing method, and more particularly to a simulation testing method for intelligent vehicle camera functions in strong light environments. First, based on camera parameters, the correspondence between the position of the strong light source in the world coordinate system and the pixel position in the image coordinate system is determined. Second, the influence radius of the light source is determined based on the geometric characteristics of strong light. Finally, the pixel positions affected by strong light are output as the strong light influence area. A camera imaging physical model is established according to the "light-electricity-digital" signal propagation process. The specific numerical values ​​of the strong light environment's influence on pixel intensity are determined based on the physical characteristics of the strong light source. Based on the geometric model, a more realistic strong light influence area is simulated by combining a strong light pixel threshold. Based on the strong light influence area and the corresponding pixel values, this is superimposed onto a non-strong light image captured by the actual vehicle to synthesize a strong light simulation image, which is then used to test the camera function. This method has the advantages of low testing cost, high testing efficiency, and precise and controllable simulation parameters.

The present document relates to a method for verifying multiple simulation models for a collision avoidance (CA) function, and a system therefor. The proposed simulation model verification method includes: performing software in the loop simulation (SILS) in which simulation of a CA functional module is performed; performing integrated SILS in which an integrated test between the CA functional module verified through the SILS and another module is performed; and performing hardware in the loop simulation (HILS) in which an integrated module verified through the integrated SILS is verified in an actual ship operating environment.