In-memory calculation method based on coarse-grained reconfigurable array

A coarse-grained, array technology, applied in the field of in-memory computing architecture design solutions based on coarse-grained reconfigurable arrays, which can solve non-in-memory processing accelerators with long transfer times, high performance and power consumption, and inflexible memory access. problem, to achieve obvious area and power consumption advantages, improve efficiency, and improve the effect of flexibility

Inactive Publication Date: 2021-03-09
SHANGHAI JIAO TONG UNIV
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Problems solved by technology

[0026] 1. For data-intensive applications, non-in-memory processing accelerators take a long time to transfer data, and memory access is not flexi

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  • In-memory calculation method based on coarse-grained reconfigurable array
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  • In-memory calculation method based on coarse-grained reconfigurable array

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specific Embodiment approach

[0095] The final system of the present invention is implemented in conjunction with C ++ and Python, and C ++ implements a specific structural configuration, Python provides parameter interface, but the present invention is not limited to C ++ and Python language. DETAILED DESCRIPTION

[0096] Step 1 Realize the simulation of CPU, DRAM, bus, etc. in C ++ and Python.

[0097] Step 2 image 3 Attach Figure 4 The solution achieves the processing unit of the reconstructed array.

[0098] Step 3 According to the attachment figure 2 Implement the PE combination as a reconfigurable array.

[0099] Step 4 follow Figure 5 The structure implements global instruction memory.

[0100] Step 5 follow Figure 7 The structure implementation instruction interconnection structure.

[0101] Step 6 follow figure 2 with Figure 6 The structure is directly connected to DRAM to design 3D stacking mode, and achieve near memory processing through Through Silicon VIA technology.

[0102] Step 7 follow f...

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Abstract

The invention relates to an in-memory processing system based on CGRA. The method is characterized by comprising a central processing unit, a main memory, a reconfigurable array and a global instruction register; a 3D stacking mode is adopted, each main memory block corresponds to a logic layer, and the logic layers and a memory chip are directly connected through the TSV technology; the processing unit of the reconfigurable array is configured as a storage unit or an arithmetic logic unit; the storage unit is used for exchanging data with the memory; and an arithmetic logic unit is used for performing calculating according to the register data, the nearby storage unit data and the configuration information. The in-memory processing system has the beneficial effects that the in-memory processing system has obvious performance advantages and wide application advantages, can realize the function simulation of the architecture under a simulation platform, is applied to a specific data intensive algorithm, adapts to more algorithm applications, and has higher flexibility; the reconfigurable array global instruction memories are all designed asymmetrically; and the transmission efficiency of the internal configuration data of the reconfigurable array is greatly improved.

Description

Technical field [0001] The present invention relates to a highly efficient design of an embodiment in the field of interior computing architecture, and more particularly to the interior calculation architecture design scheme implemented based on coarse granularity reconfigurable arrays. Background technique [0002] As the data explosive growth in today's society and the increasing demand for data analysis, traditional computing architecture facing huge challenges in performance and flexibility. Traditional computing architecture is accessed from memory. When facing large-scale data, since memory bandwidth cannot be expanded with the expansion of application data size, this has become a bottleneck point for restrictive performance. Data movement occupies a large number of runtime and energy consumption, and the cost of handling data is more expensive than calculations, this series of issues makes people think about the possibility of processing big data in memory. [0003] Advanc...

Claims

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Application Information

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IPC IPC(8): G06F15/78
CPCG06F15/7867
Inventor 绳伟光刘硕蒋剑飞景乃锋王琴毛志刚
Owner SHANGHAI JIAO TONG UNIV
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