The invention is a vertical bilateral diffusion field-effect transistor (FET) compatible routine FET making method, a BCD process method for making high voltage integrated circuits, adopting silicon slice to make VDMOS, making high concentration P+1 injection in the periphery of a chip and extending junction depth; making PWELL1 injection in low voltage region, making NWELL injection in low voltage region, preoxidizing grid of the whole chip, injecting P impurity into the whole slice and oxidizing, etching thick oxide layer, then oxidizing the whole slice, depositing, doping and etching on the whole polycrystalline silicon slice, after etching, retaining voltage dividing field plate, making PWELL2 B injection in VDMOS region, and extending junction depth; making N+ As injection in a region used to make VDMOS source, and NMOS source/drain and PMOS substrate bias of CMOS, substrate bias of PMOS, and making B injction 'P+2' in the positions of PMOS source/drain and NMOS substrate bias of CMOS, making contact hole etching, evaporating aluminum on the whole chip, corroding aluminum to form meal leads, and etching pressure point.