The invention relates to the technical field of
FPGA architecture, in particular to an SM4
hardware acceleration and anti-side-channel protection method and
system of a domestic FPGA, which comprises the following steps of: performing
data type identification operation on bright-
ciphertext batch data by utilizing an acceleration block to obtain a
data type, and according to a pre-constructed parallelization strategy and the
data type, performing data type identification operation on the SM4
hardware acceleration and anti-side-channel protection on the SM4
hardware acceleration and anti-side-channel protection on the SM4 hardware acceleration and anti-side-channel
protection system; performing
dynamic resource configuration on the
plaintext-
ciphertext batch data to obtain resource configuration information, and performing configuration according to the resource configuration information, the key-mode parameter and the
dynamic control instruction to obtain a configured SM4
algorithm; according to the configured SM4
algorithm, performing
encryption processing on the
plaintext-
ciphertext batch data to obtain to-be-protected encrypted data; and performing protection operation based on
physical layer leakage suppression, logic layer
confusion association and
system layer dynamic response on key-mode parameters,
dynamic control instructions,
plaintext-ciphertext batch data and
encryption processing by using the protection block, and converting to-be-protected encrypted data into protected encrypted data. According to the invention, the
encryption processing performance and security can be improved.