121 results about "Hardware abstraction layer" patented technology

The invention relates to the technical field of deep learning, in particular to a PyTorch framework-based compatibility expansion system, which comprises a cross-framework model converter, a heterogeneous hardware abstraction layer, a hybrid computational graph execution engine, an intelligent distributed trainer and a self-adaptive optimizer, the cross-frame model converter converts input model formats of different frames into PyTorch executable formats, the heterogeneous hardware abstraction layer supports rear ends of various hardware and automatically selects an optimal calculation path, and the hybrid calculation graph execution engine fuses dynamic graph flexibility and static subgraph optimization and supports dynamic control function execution flow. An intelligent distributed trainer automatically selects a parallel scheme and is compatible with multi-protocol communication, a self-adaptive optimizer performs dynamic optimization based on hardware characteristics and a PyTorch tensor, a cross-frame model converter supports model conversion of multiple deep learning frames, the cost of migration among different frames by a user is reduced, and the universality of the PyTorch frame is improved.

The invention provides a VirtIO interface-based ubiquitous hardware equipment virtualization supporting method and system, according to a VirtIO interface standard, bottom layer physical hardware is abstracted into virtual equipment, a VirtIO virtual equipment driver is divided into a front end and a rear end, data interaction is carried out through a sharing mechanism to form a virtual hardware abstraction layer, and the virtual hardware abstraction layer is used for supporting virtual hardware. Upwards providing state information of virtual equipment and interface information of operation equipment for an application program, shielding heterogeneity of bottom-layer physical equipment, and downwards butting local and / or far-end physical equipment to carry out actual I / O operation; and calling a migration interface through the virtual hardware abstraction layer, establishing a link with a far-end virtual device driver, transmitting the state of the local virtual device to a far end, and recovering and reconstructing the virtual device by the far-end driver. According to the method, heterogeneous hardware in a ubiquitous scene can obtain more efficient resource abstraction and management, the resource utilization rate is improved, and meanwhile the resource dynamic configuration and flexible expansion capacity is provided.

Implementations are described herein for detecting deepfakes in digital media while preserving the privacy of the source computing device. In various implementations, sensor fingerprints and / or security tokens that signal software-introduced alterations, e.g., introduced by hardware abstraction layers (HALs) or virtual machines (VMs) may be utilized to detect such deepfakes. These signals may be used, separately and / or in combination, for various purposes, such as flagging digital content to a user as being a deepfake, preventing or blocking receipt and / or playback of digital content deemed to be a deepfake, allowing an end user to disable aspect(s) (e.g., layers) of digital content that are determined to be synthetic, etc.

The invention relates to the technical field of unmanned aerial vehicle control and management, in particular to an unmanned aerial vehicle parameter consistency configuration method based on template management, which adopts a structured parameter configuration template in a JSON format, comprises four blocks of metadata, parameter definition, constraint rules and digital signatures, establishes an MAVLink communication link with an unmanned aerial vehicle flight controller through a template management terminal, and provides an unmanned aerial vehicle parameter consistency configuration method. And executing an automatic configuration process based on a finite-state machine, and ensuring parameter logic consistency by using a difference comparison and constraint verification mechanism. According to the method, temporary storage, batch writing and atomic submission of parameter changes are achieved through the atomization transaction submission protocol, the integrity of the configuration process is guaranteed, the digital signature auditing log containing the timestamp, the device identifier, the template hash and the change details is generated after configuration is completed, whole-process tracing is supported, and the method is high in practicability and easy to popularize. Headless mode operation, parameter white list control and hardware abstraction layer adaptation are supported, and high automation, standardization and safety of unmanned aerial vehicle parameter configuration can be achieved.

The invention discloses a multi-machine multi-card distributed training optimization system and method oriented to a credential heterogeneous environment, and relates to the technical field of distributed training. In order to solve the defects existing in distributed training in a credential and credential heterogeneous environment, the system comprises an application layer for receiving a training task; the core system layer comprises a self-adaptive task scheduling module, a hybrid communication topological optimization module and a dynamic check point and elastic recovery control module, and the scheduling module generates a performance portrait and an optimal scheme based on a training task and adjusts the scheme according to a node fault; the optimization module executes the scheme, firstly detects node topology, constructs a hierarchical path, loads and initializes an optimal communication rear end for target equipment, and synchronizes the path to the target equipment; the control module periodically stores a complete training context and realizes reliable recovery of a training process; the credential hardware abstraction layer is used for providing a uniform interface for realizing underlying resource access and data acquisition; and the hardware resource layer comprises heterogeneous computing nodes and an RoCE network switch.

The invention belongs to the technical field of aviation airborne system design, and provides a helicopter airborne system-oriented novel software architecture and a construction method thereof, and the architecture comprises a hardware abstraction layer, a framework resource layer, an intelligent platform service layer and an application software layer from bottom to top. And the hardware abstraction layer realizes decoupling of hardware and basic software of an operating system. The framework resource layer supports operation of a hybrid key operating system, supports and isolates tasks and application programs with different key levels, software bases and computing power requirements, and provides basic computing communication resources and AI computing power resources. The intelligent platform service layer comprises middleware, a servitization function unit and a servitization management unit, and the servitization function unit comprises atomic services and enhanced services. And the application layer interacts with the intelligent platform service layer and is decoupled from a bottom software and hardware environment. The framework is suitable for unmanned / manned helicopters, and generalization of platform support and maximum reuse of software assets are achieved.

The invention discloses an IO processing method and device, a medium and equipment, and relates to the field of virtualization, and the method comprises the steps: obtaining an IO request which is sent by an application program and aims at shared hardware equipment; after an IO frame layer of the virtual machine processes the IO request, hijacking the IO request to a hardware adaptation layer corresponding to the virtual machine, so that the hardware adaptation layer performs preset processing on the IO request to obtain a target IO request; the hardware adaptation layer sends the target IO request to a shared hardware abstraction layer, so that the shared hardware abstraction layer performs decision processing of processing opportunity on the target IO request to obtain a decision result; and under the condition that the decision result indicates that the target IO request meets the instant processing condition, the shared hardware abstraction layer sends the target IO request to a driving program corresponding to the virtual machine so as to drive shared hardware equipment to execute a read operation or a write operation indicated by the target IO request. According to the method, the processing performance of the hardware equipment in the virtualization process can be improved.

The invention discloses a test case editing scheme oriented to the automatic test industry, and the scheme realizes efficient editing, analysis and execution of test cases through layered architecture design. The scheme comprises the following steps: (1) dividing a test case into a measurement abstraction layer and a hardware abstraction layer; (2) in the measurement abstraction layer, constructing a test index sequence and a corresponding index operation sequence to form a test process file; (3) in the hardware abstraction layer, establishing a mapping relation between the operation keyword and the underlying instrument driver, and forming an instrument configuration file; and (4) the test process file and the instrument configuration file are converted into objectified description, so that flexible editing and automatic script conversion of the test case are realized. The method has the beneficial effects that (1) the readability and editing efficiency of the test case are improved, and the workload of manual script conversion is reduced; (2) the generalization ability of the test scheme is enhanced, and the method is suitable for various test devices and test scenes; and (3) flexible configuration and efficient reuse of test resources are realized through a layered architecture and a standardized file format.

The invention relates to the technical field of computers, and discloses a multi-FPGA collaborative deep neural network parallel acceleration method. According to the method, unified compiling and automatic calculation graph segmentation mapping based on a dynamic programming algorithm are carried out on a deep neural network model through a host control node, a heterogeneous strategy fusing data, the model and assembly line parallel is generated, and the problems of single FPGA computing power resource limitation and memory wall are effectively solved; direct communication between the FPGAs is achieved through a high-speed point-to-point internet, an asynchronous assembly line execution mechanism and a hardware-level data packaging technology are combined, communication delay is reduced, assembly line bubbles are eliminated, and a multi-FPGA cluster reaches a near-linear speed-up ratio; computing distribution is optimized in real time through a global load balancing unit, and the equipment utilization rate is increased; and meanwhile, a transparent deployment interface is provided through the hardware abstraction layer, so that the super-large-scale neural network can efficiently run on a multi-FPGA platform with low delay, and the overall calculation efficiency is improved.

The invention is suitable for the technical field of computer system starting, and provides an OpenSBI starting method and system of an RISC-V SoC based on an FPGA, the system comprises a hardware abstraction layer, a boot loading layer, a privilege management layer and a kernel execution layer, and each layer realizes data interaction and process connection through a standardized interface; through the hierarchical design of FPGA hardware initialization, SPL / U-Boot firmware loading, OpenSBI privileged mode configuration and kernel startup, modular management of a startup process is realized, the system coupling degree is reduced, multiple storage medium and operating system types are supported, hardware abstraction is realized through an OpenSBI standard interface, subsequent extension of new peripherals or upgrading of an RISC-V architecture version is facilitated, and the development of the RISC-V architecture is facilitated. The standardized starting process reduces the adaptation workload of hardware and firmware, and debugging and rapid iterative development are facilitated.

There is provided a gaming input provider (500) for an automotive operation system, AOS, system (100), which operates according to an AOS, the AOS including a AOS standard gaming input application programming interfaces, APIs, block (502) requiring, in input, a gaming input signal (512) of a pre-defined format and providing, to a higher layer gaming engine (204), a standardized version of the gaming input signal (212) of the pre-defined format, the gaming communication controller comprising: a communication service (102) to wirelessly receive a gaming input signal (302) from a mobile device (300); a hardware abstraction layer, HAL, block (202) to convert the gaming input signal (302, 112) onto the pre-defined format.

The application relates to the technical field of industrial measurement and control software, and discloses a nationwide state-oriented measurement and control platform which adopts a layered architecture and comprises the following: an application service layer for providing a man-machine interactive interface and executing business logic; a unified business message layer for providing a standardized data communication interface; a multithreaded time sequence scheduling engine for parallel receiving, scheduling and processing real-time tasks; a unified hardware abstraction layer for encapsulating the differences of different field bus drivers and providing a unified device operation interface; a domestication adaptation layer constructed on a Qt core framework and used for providing a unified driving abstraction across domestic chips and operating systems; and a hardware access layer for directly interacting with physical hardware devices.The application realizes 'one-time development and cross-domestic platform deployment', significantly improves the real-time performance, maintainability and expandability of the system under the domestic ecological environment, and meets the dual requirements of self-controllability and high performance.

This disclosure relates to a fingerprint recognition processing method, apparatus, electronic device, and storage medium thereof. The fingerprint recognition processing method includes: when it is determined that the anti-mistouch recognition result of the fingerprint unlocking area in the electronic device is a mis-touch of a non-fingerprint object, determining the number of mis-touches of the non-fingerprint object based on the hardware abstraction layer of the electronic device; if it is determined based on the number of mis-touches that the electronic device does not meet the anti-mistouch detection retry conditions, then the application framework layer of the electronic device receives the mis-touch result information reported by the hardware abstraction layer; in response to the mis-touch result information meeting preset conditions, triggering a fingerprint lockout mechanism to not respond to fingerprint unlocking commands for a preset time period. This disclosure can avoid frequent lockouts of electronic devices.

The invention provides an EtherCAT slave station gateway for semiconductor temperature control equipment. The EtherCAT slave station gateway comprises a hardware layer and a software layer, wherein the hardware layer comprises an embedded semiconductor industrial equipment communication gateway, an integrated power supply module, a main control module, an Ethernet communication module, an EtherCAT slave station module and a 24V input and output port module; the software layer is an embedded software system with a layered architecture, is divided into an application layer, a protocol layer and a hardware abstraction layer, and realizes business logic processing, communication protocol conversion and software and hardware interaction decoupling. Through cooperative work of hardware and software, data transmission based on the EtherCAT protocol between the semiconductor production equipment host and the Chiller can be achieved, the real-time performance, accuracy and system maintainability of data transmission are improved, and the requirements of semiconductor production for high precision and high stability of temperature control are met.

The application provides a VISA library running method and device based on an ARM embedded platform, and relates to the technical field of testing and measurement, and comprises the following steps: initializing a layered architecture of a VISA library; the layered architecture of the VISA library comprises an application layer, an API interface layer, a core logic layer, a hardware abstraction layer and a driver layer; discovering and establishing a communication session connection with at least one measuring instrument; wherein a session attribute and a preset attribute associated with a data reading operation are included in a session structure body of the communication session; setting at least one preset attribute for the VISA library; sending at least one control command to a target measuring instrument; wherein the target measuring instrument comprises at least one; reading response data for the control command from the target measuring instrument based on the preset attribute and writing the response data into a buffer; and closing the communication session established with the at least one measuring instrument, so as to alleviate the technical problem that the VISA library is difficult to meet the requirements of an embedded application scenario in high performance.

The invention relates to the technical field of embedded software radio, in particular to a remote procedure call (RPC) system and method based on MHAL / MOCB. The SCA platform software architecture is used for an SCA platform software architecture core framework comprising a server side and a client side; and the core framework client establishes connection with the core framework server by means of the RPC middleware based on the MHAL / MOCB remote procedure call. The server and the client among the nodes are communicated on the SRIO bus by adopting a protocol based on a hardware abstraction layer (MHAL / MOCB), and the communication speed is higher than that of the traditional Ethernet based on TCP / IP (Transmission Control Protocol / Internet Protocol).

The invention relates to the technical field of robot control, in particular to a control system and method for a general window-cleaning robot, and the system comprises an equipment driving layer, a hardware abstraction layer, an application logic layer and an RTOS system layer, the hardware abstraction layer is connected with the equipment driving layer, and the application logic layer is connected with the hardware abstraction layer and the RTOS system layer; the equipment driving layer provides an underlying hardware interaction interface with the motor, the sensor and the communication module; the hardware abstraction layer abstracts the hardware difference of the bottom layer, provides a unified hardware access interface for the upper layer, and adapts to different hardware forms by replacing the hardware abstraction layer; the application logic layer comprises core business logic of a path planning mechanism, a state machine management mechanism, a task scheduling mechanism and an exception handling mechanism; in this way, the technical problems that in the prior art, a window cleaning robot control mode is difficult to be suitable for a round window cleaning robot and a square window cleaning robot at the same time, so that the development cost is high, the system reusability and maintainability are poor, and the development efficiency is low are solved.

The embodiment of the invention provides a BootROM architecture for a storage control chip, and relates to the technical field of storage. The BootROM architecture comprises a function library, a hardware abstraction layer, a Boot module and a processor driving module, the function library is used for storing various basic processing functions; the hardware abstraction layer comprises a hardware operation function, and the hardware operation function is used for operating various hardware units of a control component of the storage equipment; the Boot module is used for loading and operating a loading guider and setting a hardware driving function interface according to the identified guiding mode; the processor driving module comprises a processor driving function; and a basic processing function of a hardware unit which is provided by the function library and needs to operate the control component calls a hardware operation function provided by the hardware abstraction layer through a hardware driving function interface provided by the Boot module so as to operate the hardware unit in the storage equipment. According to the BootROM architecture, after a chip is upgraded, a function interface of operation hardware is set by modifying a Boot module to adapt to an invariable function library and a changed hardware abstraction layer.

The application discloses a multimodal large model integrated deployment and heterogeneous unmanned system control method and device. The method comprises the following steps: receiving a natural language instruction, decomposing the natural language instruction into an ordered standardized subtask sequence through a task semantic analysis engine, inputting the ordered standardized subtask sequence and observation data collected and converted by a hardware abstraction layer into a visual-language-action large model reasoning engine for fusion reasoning, generating a bottom layer action instruction sequence, converting the action instruction sequence into a bottom layer control protocol message recognizable by a target heterogeneous unmanned system and issuing the bottom layer control protocol message for execution, generating platform standard feedback data through the hardware abstraction layer according to sensor feedback messages generated in the execution, and feeding back the platform standard feedback data to the front end through a scheduling center. The technical scheme of the application can directly drive the heterogeneous unmanned system to execute tasks by using the natural language instruction, reduce the cross-device development and adaptation cost, improve the end-side reasoning and control response efficiency, and realize the standardized feedback and visual monitoring of the execution state.

The invention relates to the technical field of power electronic control, and provides a general control platform and method for an SST modular power unit and a readable storage medium. The hardware layer comprises a general computing unit supporting multi-type signal processing, a configurable interface module adapted to different external devices, and a power management unit providing general power supply for hardware; the software layer runs on the hardware layer, and the software layer comprises a hardware abstraction layer used for shielding hardware differences, a control algorithm module dynamically configured to adapt to various SST topologies, and a communication mechanism supporting unified data interaction; the software layer and the hardware layer are cooperatively arranged through the hardware abstraction layer. The problems of long research and development period and high cost are solved, and technology multiplexing and platform sharing of different SST product lines are realized; when topology or parameters change, a control system does not need to be modified or redesigned on a large scale, SST technology iteration is accelerated, and large-scale application is guaranteed.

The invention relates to a flight control program intelligent adaptation method and system oriented to a heterogeneous processing architecture, and solves the technical problems of low efficiency, strategy solidification, difficulty in knowledge reuse and the like when a flight control program is manually transplanted to a domestic or novel chip in the prior art. And automatically generating a customization strategy containing environment configuration, a peripheral list, a test path and branch planning. Accordingly, a debugging environment is automatically deployed, a drive code is generated, and parallel development branches are initialized. An event-driven and dependent sensing mechanism is adopted, verification tasks are dynamically scheduled, code integration is coordinated, hardware abstraction layer configuration and interface codes are intelligently adjusted, a flight control program image is finally and automatically constructed, and efficient and reliable heterogeneous chip flight control program intelligent adaptation is achieved. The method has the following technical effects that automatic intelligent adaptation of the flight control program to the heterogeneous chip is realized, the transplantation efficiency and the code quality are greatly improved, and reusable adaptive knowledge assets are formed.

This invention relates to a method and apparatus for implementing an EtherCAT master system without an operating system. The method includes: adapting the SOEM protocol stack to the hardware abstraction layer of the EtherCAT master by using byte order processing based on bitmasks and a phased shift strategy, and EtherCAT frame transmission and reception control based on circular buffer index management; adapting the SOEM protocol stack to the operating system abstraction layer of the EtherCAT master by using non-real-time task priority scheduling based on hardware timers, a single-threaded event-driven main loop, and a blocking communication synchronization mechanism combined with timer timeout monitoring; and adapting the EtherCAT master application layer through network scanning and communication parameter configuration, a memory management mechanism based on CoE standard mapping, and the periodic position mode of slave stations. This invention achieves an operating system-free EtherCAT master system and microsecond-level communication jitter by optimizing and adapting the SOEM protocol stack.

The embodiment of the invention provides a flash lamp control method and device, a medium and a program product, and relates to the technical field of control or the technical field of electronic equipment. The method is applied to the electronic equipment and comprises the following steps: collecting multi-scene event data through a service layer; inputting structured feature information in the multi-scene event data into a priority judgment model, performing weighted fusion on event types, time dimension features and user historical behavior features through an attention mechanism of the priority judgment model, performing priority judgment on the scene event data, and generating an event queue containing scene identifiers and priorities; dynamically allocating flash lamp hardware resources through a hardware abstraction layer based on the scene identifier and the priority in the event queue, and generating a lamp effect task queue; and controlling the flash lamp to execute the corresponding lamp effect according to the lamp effect task queue. The method is used for achieving the effects of realizing flexible priority scheduling and improving flash lamp resource scheduling and personalized scene matching accuracy through the priority judgment model.

The invention provides a hardware abstraction layer reconstruction method and device based on a programmable logic platform, and the method comprises the steps: obtaining a GPIO pin level combination of an extension module, decoding the GPIO pin level combination to obtain an equipment type identifier, activating a corresponding peripheral sub-module in a unified peripheral IP logic module, carrying out the drive mapping table searching and initialization configuration of a target peripheral logic unit, and carrying out the hardware abstraction layer reconstruction. And finally, parameter configuration is carried out through an AXI-Lite control bus, and data transmission is carried out through an AXI-Stream data bus and an AXI-DMA module. According to the method, a complete closed-loop process of plug-and-identification, identification-and-drive and drive-and-use is realized, the technical problems that in a traditional programmable logic platform, manual drive configuration is needed for module expansion, and a unified hardware abstraction mechanism is lacked are solved, and a solution which is efficient, low in cost and friendly to beginners is provided for teaching.

The present invention provides an off-line software-in-the-loop simulation development system and an off-line software-in-the-loop simulation method. A general firmware architecture is compiled to generate a chip control program. The general firmware architecture includes an application layer and a hardware abstraction layer. The application layer has a setup header file and a product program. Processing programs required by peripheral modules are added to the hardware abstraction layer at compile time. The chip control program is provided to a controller chip or circuit simulation software to control product-related circuits by controlling peripheral modules.

This invention proposes a GPU computing power scheduling method based on a cloud-based multi-core heterogeneous computing platform. The method includes the following steps: Step S1: Heterogeneous resource registration and modeling. A resource registration module is used to access hardware devices containing multiple types of GPUs, collecting device model, memory capacity, and performance index data to construct a resource feature database containing topological relationships, supporting mixed chip access; Step S2: Virtualization resource reconstruction. Hardware abstraction layer technology is used to pool physical GPUs into virtual GPU resources. Containerization technology is used to achieve memory isolation and computing unit partitioning. Each virtual GPU instance is equipped with an independent driver stack and security sandbox; Step S3: Multimodal task submission. CUDA / OpenCL computing tasks submitted by users are received, and task requirement parameters, including the number of computing cores, memory usage, and data throughput threshold, are parsed to generate a task descriptor containing priority tags.

The invention relates to the technical field of software development. The invention discloses a modularized code-free platform, which adopts a five-layer architecture and comprises an application presentation layer, a test report presentation layer and a test report presentation layer, the configuration engine layer is used for analyzing the structured configuration file and generating an executable process model; the test execution layer is used for scheduling and executing a test flow defined by the process model; the hardware abstraction layer is used for providing a unified instrument operation interface and managing a mapping relation between a logic signal and physical hardware; and the equipment driving layer is used for realizing communication with specific instrument equipment. According to the method, a configuration-as-a-service mode is adopted, so that business personnel can quickly construct an application on the premise of not writing codes, the technical threshold is remarkably reduced, and the response speed is increased; business personnel only need to edit Excel to complete configuration of a complex instrument control process, and codes do not need to be written.

The application discloses a simulation system supporting fast large-scale brain simulation, and belongs to the technical field of brain simulation.The simulation system comprises a hardware device layer, which provides a plurality of hardware device resources; a data communication layer, which provides a plurality of types of communication modes between the computing nodes; an operation abstraction layer, which provides a plurality of types of neuron models, synapse models, connection rules and learning rules; an API layer, which provides an API interface and receives user requirements through the API interface; a hardware abstraction layer, which calls corresponding hardware kernels; and a network abstraction layer, which firstly records the topological structure of a brain simulation network, performs resource allocation and neuron cluster mapping, then creates the brain simulation network on the hardware device, and finally performs training or execution of the brain simulation network.The application fully utilizes cluster hardware resources to realize faster and larger-scale brain simulation, and solves the problems of lack of resource scheduling and resource allocation, insufficient utilization of device parallelism, too long communication time consumption, and limited support of hardware and interfaces.

This invention discloses an in-situ inspection system and method for aero-engine blades based on SLAM fusion, belonging to the field of aero-engine inspection technology. The system comprises a probe module, a hardware abstraction layer module, a middleware layer module, and an application layer module. By using GPU processing to compute view information detected by the endoscopic camera sensor, it efficiently processes and computes graphic and image data. Furthermore, by employing multi-sensor fusion, it achieves real-time localization and map construction for in-situ inspection of aero-engine blades, solving the localization challenges in environments with sparse internal engine textures and reflective lighting. The system is simple, economical, and highly practical.

The invention provides a multi-dimensional self-adaptive large model inference engine method and system, and relates to the technical field of artificial intelligence, and the method comprises the steps: collecting hardware identification information of calculation hardware, and calling a hardware fingerprint database for matching to generate a hardware type result and a hardware characteristic parameter; constructing a hardware abstraction layer, loading a hardware abstraction driving plug-in according to a hardware type result, and virtualizing computing hardware into a unified logic computing power unit through a hardware abstraction interface; when a large model reasoning task is triggered, dynamically routing to a back-end executor according to a hardware type result by querying a back-end registry; on the basis of hardware characteristic parameters and a hardware abstract interface, a hardware compiling tool chain is called through a rear-end executor, graph optimization and operator fusion are executed on a large model calculation graph, and therefore self-adaptive deployment and efficient reasoning of a large model on heterogeneous hardware can be achieved; the problems that in the prior art, heterogeneous hardware is insufficient in compatibility, configuration is tedious and rigid, and compilation optimization barriers and performance losses are caused during model cross-platform migration are solved.