Visual programming implementation method and device of programmable logic device

Abstract

The invention relates to a visual programming implementation method and device of a programmable logic device, computer equipment, a storage medium and a computer program product. The method comprises the steps that logic association configuration data and identifiable data path configuration data of the programmable logic device are obtained, mapping between a physical layer and a logic layer of the programmable logic device is established according to the data path configuration data and the logic association configuration data, the logic layer comprises a plurality of instantiated logic blocks, and the logic blocks are used for storing the logic blocks. The identifiable data path configuration data is obtained by converting initial data path configuration data generated by the visual development platform by the connected embedded platform. By adopting the method, decoupling and configurability of the physical layer and the logic layer can be realized, the data updating efficiency is improved, and the method can be suitable for engineering sites with complex and changeable functional requirements and is higher in flexibility and universality.

Description

Technical Field

[0001] The present application relates to the technical field of digital circuits, and in particular to a method, apparatus, computer equipment, storage medium and computer program product for implementing visual programming of a programmable logic device. Background Art

[0002] With the development of embedded programmable logic device technology, the control link delay of the DC grid flexible control system can be achieved at the 100 microsecond level. The ability to achieve this functional performance level mainly lies in the strong real-time application functions running in programmable logic devices.

[0003] In the field of power DC, application functions are usually implemented in FPGA (Field-Programmable Gate Array), and current mainstream manufacturers all use function-oriented design for FPGA.

[0004] However, the requirements of engineering sites change frequently, and there are many situations of on-site parameter adjustment and functional logic combination. It is often necessary to adjust and modify the FPGA software application functions on-site, which is time-consuming and labor-intensive. At the same time, each engineering site has different functional versions and functional interface definitions, and the FPGA program version is relatively specialized. When faced with diverse functional requirements, a large amount of data modification and data updating is required, and the computer needs to perform multiple data processing operations, which makes the on-site data update efficiency low. Summary of the invention

[0005] Based on this, it is necessary to provide an efficient visual programming implementation method, device, computer equipment, computer-readable storage medium and computer program product for programmable logic devices that can meet various engineering needs in order to solve the above technical problems.

[0006] In a first aspect, the present application provides a method for implementing visual programming of a programmable logic device. The method comprises:

[0007] Acquiring logic-related configuration data and identifiable data path configuration data of a programmable logic device;

[0008] Establishing a mapping between a physical layer and a logical layer of a programmable logic device according to the data path configuration data and the logic association configuration data;

[0009] The logic layer includes a plurality of instantiated logic blocks, and the identifiable data path configuration data is obtained by converting the initial data path configuration data generated by the visualization development platform by the connected embedded platform.

[0010] In the technical solution of the embodiment of the present application, unlike the traditional method of converting the language of the written logic code through the synthesis tool to obtain the connection relationship configuration data of the programmable logic device, the identifiable data path configuration data is directly obtained by converting the initial data path configuration data generated by the visual development platform by the embedded platform, without the need for language conversion. In addition, by pre-building instantiated logic blocks, it is possible to establish a mapping between the physical layer and the logical layer based on the logical association configuration data and the data path configuration data, separate the underlying hardware devices from the upper-level application programs, and realize the decoupling and configurability of the physical layer and the logical layer. When the functional requirements change, the application function can be changed by modifying the configuration items of the logic blocks, thereby improving the data update efficiency and being applicable to engineering sites with complex and changeable functional requirements, with greater flexibility and versatility.

[0011] In some embodiments, establishing a mapping between a physical layer and a logical layer of a programmable logic device according to the data path configuration data and the identifiable logic association configuration data includes:

[0012] According to the data path configuration data and the logic association configuration data, the mapping between the physical mapping layer, the communication interface layer and the data exchange interface layer and the logic layer is established; the physical layer includes the physical mapping layer, the communication interface layer and the data exchange interface layer.

[0013] In the technical solution of the embodiment of the present application, by dividing the physical layer into a physical mapping layer, a communication interface layer and a data exchange interface layer, and establishing a mapping between the physical mapping layer, the communication interface layer and the data exchange interface layer and the logical layer, the coupling degree between the modules can be reduced, making the modules more reusable and achieving higher resource utilization.

[0014] In some embodiments, the instantiated logic block includes a communication logic block, and the logic-associated configuration data includes input and output parameters and parameter models of the communication logic block, and protocol parameters and protocol channel data of the communication interface layer;

[0015] According to the data path configuration data and the logic association configuration data, establishing the mapping between the communication interface layer and the logic layer includes:

[0016] According to the data path configuration data, the input and output parameters and parameter model of the communication logic block are associated with the protocol parameters and protocol channel parameters of the communication interface layer, and a mapping between the communication interface layer and the communication logic block is established, wherein the parameter model is associated with the logic association configuration data.

[0017] In the technical solution of the embodiment of the present application, by associating the input and output parameters and parameter model of the communication logic block with the protocol parameters and protocol channel parameters of the communication interface layer, a mapping between the communication interface layer and the communication logic block is established, which facilitates the modification, expansion and reconstruction of the communication logic block and the communication interface layer, and ensures good compatibility between different platforms or systems.

[0018] In some embodiments, the instantiated logic block includes a functional logic block, and the logic-associated configuration data includes input and output parameters and parameter models of the functional logic block, and signal data and data lines of a data exchange interface layer;

[0019] According to the data path configuration data and the logic association configuration data, establishing the mapping between the data exchange interface layer and the logic layer includes:

[0020] The input and output parameters of the functional logic block are associated with the data transceiver channel of the communication logic block, and the input and output parameters and parameter model of the functional logic block are associated with the signal data and data lines of the data exchange interface layer to establish a mapping between the data exchange interface layer and the logic layer.

[0021] In the technical solution of the embodiment of the present application, by establishing a mapping between the data exchange interface layer and the communication function logic block, data transmission and processing functions are realized, so that each component has a high cohesion, the coupling degree of the system is reduced, and the maintainability of the system is improved.

[0022] In some embodiments, the physical mapping layer includes a configuration data block, a monitoring data block, a sampling data block, a control command data block, and an application function data block;

[0023] According to the data path configuration data and the logical association configuration data, establishing the mapping between the physical mapping layer and the logical layer includes:

[0024] According to the logical function resource configuration data and data path configuration data of each data block in the logical association configuration data, the mapping relationship between the configuration data block, the monitoring data block, the sampling data block, the control command data block and the application function data block and the logical layer is established respectively.

[0025] In the technical solution of the embodiment of the present application, by establishing a mapping relationship between the configuration data block, the monitoring data block, the sampling data block, the control command data block and the application function data block and the logical layer, the design and implementation complexity of the system can be simplified, the development efficiency can be improved, and flexible configuration and adjustment can be performed for different application scenarios.

[0026] In some embodiments, the configuration data block performs data read and write operations through a RAM (Random Access Memory).

[0027] In the technical solution of the embodiment of the present application, by caching the data of the configuration data block into the RAM, the number of data exchanges with external devices can be reduced, and high-speed, low-latency data transmission and processing can be achieved. In addition, the size of the RAM, read and write speed and other parameters can be configured as needed to meet the needs of different application scenarios.

[0028] In some embodiments, the monitoring data block, the sampling data block, the control command data block, and the application function data block perform data reading and writing operations through FIFO (First-In-First-Out).

[0029] In the technical solution of the embodiment of the present application, data reading and writing operations are performed in a FIFO manner, which can better control and synchronize data flow, and can also dynamically adjust the storage capacity and data transmission rate according to the needs of the application, thereby enhancing flexibility.

[0030] In some embodiments, the method further comprises:

[0031] Obtaining hierarchical partitioning data of programmable logic devices;

[0032] According to the hierarchical division data, the interface layer of the programmable logic device is divided into a physical layer, a logical association layer and a logical layer.

[0033] In the technical solution of the embodiment of the present application, the programmable logic device is divided into a physical layer, a logical association layer and a logical layer by hierarchical division data, and the logical association layer is used as a bridge to achieve mapping and decoupling of the physical layer and the logical association layer.

[0034] In a second aspect, the present application also provides a visual programming implementation device for a programmable logic device.

[0035] The device comprises:

[0036] A data acquisition module, used to acquire logic-related configuration data and identifiable data path configuration data of a programmable logic device;

[0037] A data mapping module, used to establish a mapping between a physical layer and a logical layer of a programmable logic device according to data path configuration data and logic association configuration data;

[0038] The logic layer includes a plurality of instantiated logic blocks, and the identifiable data path configuration data is obtained by converting the initial data path configuration data generated by the visualization development platform by the connected embedded platform.

[0039] In a third aspect, the present application further provides a computer device, which includes a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps in the visual programming implementation method of the programmable logic device when executing the computer program.

[0040] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps in the above-mentioned method for implementing visual programming of a programmable logic device when executed by a processor.

[0041] In a fifth aspect, the present application further provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the steps in the visual programming implementation method of the programmable logic device are implemented.

[0042] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is an application environment diagram of a method for implementing visual programming of a programmable logic device in some embodiments of the present application;

[0044] Figure 2 A flowchart of a method for implementing visual programming of a programmable logic device in some embodiments of the present application;

[0045] Figure 3 A flowchart of steps for establishing mapping between the physical layer and the logical layer in other embodiments of the present application;

[0046] Figure 4 A detailed schematic diagram of a method for implementing visual programming of a programmable logic device in some other embodiments of the present application;

[0047] Figure 5 A schematic diagram of establishing a mapping between a communication function logic block, a function logic block and a logic layer in some embodiments of the present application;

[0048] Figure 6 This is a visualization implementation framework diagram of FPGA abstraction layering in some embodiments of the present application;

[0049] Figure 7 A detailed flowchart of a method for implementing visual programming of a programmable logic device in some other embodiments of the present application;

[0050] Figure 8A structural block diagram of a visual programming implementation device for a programmable logic device in some embodiments of the present application;

[0051] Fig. 9 A structural block diagram of a visual programming implementation device for a programmable logic device in some other embodiments of the present application;

[0052] Fig.10 This is a diagram of the internal structure of a computer device in some embodiments of the present application. DETAILED DESCRIPTION

[0053] The following embodiments of the technical solution of the present application are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0055] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0056] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0057] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0058] With the development of embedded programmable logic device technology, the control link delay of the DC grid flexible control system can be achieved at the 100 microsecond level. The ability to achieve this functional performance level mainly lies in the fact that strong real-time application functions run in programmable logic devices (PLDs).

[0059] Taking FPGA as an example, the circuit design completed with hardware description languages ​​such as Verilog HDL (Hardware Description Languag) or VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) can be quickly burned to FPGA for testing after simple synthesis and layout, which is the mainstream technology for integrated circuit design verification. These editable components can be used to implement some basic logic gate circuits (such as AND, OR, XOR, NOT) or more complex combination functions such as decoders or mathematical equations. In most FPGAs, these editable components also include memory elements such as flip-flops or other more complete memory blocks. System designers can connect the logic blocks inside the FPGA through editable connections as needed, just like a circuit test board is placed in a chip. The logic blocks and connections of a finished FPGA after leaving the factory can be changed according to the designer, so the FPGA can complete the required logic functions.

[0060] In the field of power DC, usually, the application function is implemented in FPGA. The current mainstream manufacturers all use function-oriented design for FPGA. There are currently two main implementation methods: one is the traditional development method based on hardware description language (HDL), and the other is the implementation method based on graphical design tools, namely the visual implementation method. The traditional development method adopts a hierarchical and modular design approach, and describes the processing process by writing HDL code and calling IP cores. This design method requires writing a lot of code, and the workload is large, the debugging time is long, and the development cycle is greatly extended. The visual programming method is implemented from the perspective of visual development, using familiar icons to express the design content, and using lines to represent the interactive relationship between subsystems. Developers can complete the construction of processing algorithms through intuitive visual operations. Compared with the traditional development method, visual programming is simple and direct, and does not require high programming skills from users, which can greatly improve development efficiency. Therefore, visual programming is increasingly widely used.

[0061] However, in the application of FPGA visual programming, the requirements of the project site change frequently, and there are many situations for on-site parameter adjustment and functional logic combination. It is often necessary to adjust and modify the FPGA software application functions on site, which is time-consuming and labor-intensive. At the same time, each project site has different function versions and function interface definitions, and the FPGA program version is relatively specialized and cannot meet the programming requirements of multiple on-site projects.

[0062] Based on the above problems, the present application proposes a method for implementing visual programming of a programmable logic device, which specifically instantiates the logic block of the programmable logic device according to the functional requirements in advance, and then obtains identifiable data path configuration data and logic association configuration data. The identifiable data path configuration data is obtained by converting the initial data path configuration data generated by the visual development platform by the connected embedded platform. Then, according to the data path configuration data and the logic association configuration data, a mapping between the physical layer and the logical layer of the programmable logic device is established, and the underlying hardware device is separated from the upper-level application program, so as to realize the decoupling and configurability of the physical layer and the logical layer. When the functional requirements change, the application function can be changed by modifying the configuration items of the logic block, thereby improving the data update efficiency, and being applicable to engineering sites with complex and changeable functional requirements, with greater flexibility and versatility.

[0063] The visual programming implementation method of the programmable logic device provided in the embodiment of the present application can be applied to Figure 1In the application environment shown. Among them, the programmable logic device takes an FPGA chip as an example, and the programmable logic device design platform takes an FPGA design platform as an example. The visualization development platform 100 communicates with the embedded platform 102 through a network, and the embedded platform 102 communicates with the FPGA design platform 104 through a serial port. Specifically, the developer can perform FPGA visualization design on the visualization development platform 100 according to the functional requirements of the visualization engineering project. The visualization development platform 100 generates initial data path configuration data corresponding to the visualization engineering project, and sends the initial data path configuration data to the embedded platform 102. The embedded platform 102 receives the initial data path configuration data and converts the initial data path configuration data into data path configuration data that can be recognized by the FPGA design platform 104. The embedded platform sends the recognizable data path configuration data to the FPGA design platform 104, and the FPGA design platform 104 receives and stores the recognizable data path configuration data. When the FPGA design platform 104 receives the visual design instruction, it obtains the logic-related configuration data and the identifiable data path configuration data of the programmable logic device, and establishes the mapping between the physical layer and the logical layer of the programmable logic device according to the data path configuration data and the logic-related configuration data, so as to realize the decoupling of the physical layer and the logical layer. Among them, the visual development platform 100 can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, Internet of Things devices and portable wearable devices. The Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart car-mounted devices, etc. Portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc.

[0064] In some embodiments, Figure 2 As shown, a visual programming implementation method for a programmable logic device is provided, and the method is applied to Figure 1 The FPGA design platform 102 in the embodiment of the present invention, wherein the programmable logic device is described by taking FPGA as an example, includes the following steps:

[0065] S200, obtaining logic association configuration data and identifiable data path configuration data of a programmable logic device.

[0066] A programmable logic device is a general-purpose programmable digital logic circuit with a high degree of integration, which can meet the needs of general digital systems. Currently commonly used programmable logic devices include programmable array logic (PAL), programmable logic array (PLA), complex programmable logic device (CPLD), and FPGA. Logical association configuration data refers to the configuration data in the logical association layer of the programmable logic device, specifically including relevant configuration data for realizing the mapping of the physical layer and the logical layer, and configuration data for describing the connection relationship between the programmable logic unit and the programmable interconnection resources of the physical layer, such as the input and output parameters and parameter model data of each functional logic block, as well as communication protocol and communication channel data. In this embodiment, the logical association configuration data can be pre-stored data. Data path configuration data refers to configuration data used to characterize the connection relationship between various resources inside the programmable logic device, which can be understood as logic netlist data.

[0067] Taking FPGA as an example of a programmable logic device, the connection between different resources inside the FPGA chip is usually referred to as the "FPGA internal data path" (Internal Data Path), which can also be referred to as "data path" or "internal connection". Specifically, the data path configuration data includes configuration data such as the signal transmission path, the interconnection between logic elements, clock distribution and data storage, which is the key to realizing various computing and control functions inside the FPGA chip. The data path configuration data can instruct the programmable logic device to connect a specific input pin to the input port of a specific logic unit, and connect the output port of the logic unit to a specific output pin. In this embodiment, the identifiable data path configuration data refers to the data path configuration data that can be directly recognized by the programmable logic device. Specifically, the identifiable data path configuration data can be obtained by converting the initial data path configuration data by the embedded platform, and the initial data path configuration data is the initial data path configuration data generated by the visual development platform according to the designed engineering project, and the initial data path configuration data is data described by the software programming language (such as C language, C++ language, etc.).

[0068] In specific implementation, the visualization development host computer may generate initial data path configuration data according to the designed engineering project suitable for the DC control and protection field, and send the initial data path configuration data to the embedded platform. The embedded platform receives the initial data path configuration data sent by the visualization development platform, and converts the initial data path configuration data into recognizable data path configuration data, such as binary data path configuration data. The embedded platform then sends the converted recognizable data path configuration data to the FPGA design platform. The FPGA design platform stores the recognizable data path configuration data. When the FPGA design platform receives the visualization implementation instruction, it obtains the stored logic-related configuration data and recognizable data path configuration data of the FPGA.

[0069] S400, establishing a mapping between a physical layer and a logical layer of a programmable logic device according to data path configuration data and logic association configuration data.

[0070] The physical layer of FPGA refers to the physical environment in which FPGA is located in actual application. It is connected to the external system interface and carries functions such as input and output signals and power supply. It specifically includes hardware-related components such as silicon chips, pins, device packages, and circuit boards. The logic layer of FPGA refers to the logic circuit formed by connecting basic logic units such as LUT (Look-Up Table) and registers according to a specific netlist. It is the core of FPGA to realize specific functions. Various digital circuit functions such as counters, multiplexers, state machines, etc. can be realized by programming the logic layer. In this embodiment, the logic layer includes multiple logic blocks that are pre-implemented through FPGA code according to functional requirements, and the logic block has realized the corresponding logic circuit. Specifically, the logic block may include a communication logic block, a functional logic block, and a sampling processing logic block.

[0071] In specific implementation, after obtaining the logical association configuration data and the identifiable data path configuration data, the FPGA can be connected based on the data path configuration data and the logical association configuration data to realize the connection between resources such as programmable logic units and programmable input / output units in the FPGA, establish the mapping of the physical layer and the logical layer of the FPGA, and realize the decoupling of the physical layer and the logical layer.

[0072] The above-mentioned visual programming implementation method of the programmable logic device is different from the traditional method of converting the language of the written logic code through the synthesis tool to obtain the connection relationship configuration data of the programmable logic device. Instead, the identifiable data path configuration data is directly obtained by converting the initial data path configuration data generated by the visual development platform by the embedded platform without language conversion. In addition, by pre-building instantiated logic blocks, it is possible to establish a mapping between the physical layer and the logical layer according to the logical association configuration data and the data path configuration data, separate the underlying hardware device from the upper-level application program, and realize the decoupling and configurability of the physical layer and the logical layer. When the functional requirements change, the application function can be changed by modifying the configuration items of the logic block, thereby improving the data update efficiency, and can be applied to engineering sites with complex and changeable functional requirements, with greater flexibility and versatility.

[0073] like Figure 3 As shown, in some embodiments, the method further includes: S100, obtaining hierarchical division data of the programmable logic device, and dividing the interface layer of the programmable logic device into a physical layer, a logical association layer and a logical layer according to the hierarchical division data.

[0074] Hierarchical division data refers to data used to divide programmable logic devices into different levels. In this embodiment, in the visual implementation framework of FPGA layer extraction and stratification, the FPGA can be divided into three levels: physical layer, logical association layer and logical layer. In specific implementation, the FPGA chip can be divided into physical layer, logical association layer and logical layer according to the hierarchical division data. Among them, the physical layer refers to the physical environment in which the FPGA is located in actual application. It is connected to the external system interface and carries functions such as input and output signals and power supply. The logical layer refers to the logic circuit formed by connecting basic logic units according to a specific netlist, which is the core of the FPGA to realize specific functions. As a bridge between the physical layer and the logical layer, the logical association layer provides the function of converting the logic design into the underlying physical resources. It can be used to connect the logic elements, registers and timing information with the underlying physical resources, allowing developers to map the logic design to the FPGA chip.

[0075] In the technical solution of the embodiment of the present application, the programmable logic device is divided into a physical layer, a logical association layer and a logical layer by hierarchical division data, and the logical association layer is used as a bridge to achieve mapping and decoupling of the physical layer and the logical association layer.

[0076] like Figure 3 As shown, in some embodiments, S400 includes:

[0077] S420, establishing mapping between the physical mapping layer, the communication interface layer, the data exchange interface layer and the logical layer according to the data path configuration data and the logical association configuration data; the physical layer includes the physical mapping layer, the communication interface layer and the data exchange interface layer.

[0078] In this embodiment, the physical layer is designed according to the functional requirements of the DC control and protection field, mainly covering control functions, protection functions, and internal and external communication functions. Specifically, it includes a physical mapping layer, a communication interface layer, and a data exchange interface layer. Among them, the physical mapping layer is used to convert the logic design into a hardware circuit. The physical mapping layer will map it to the programmable logic unit and other hardware resources according to the user's logic design to generate a physical circuit corresponding to it. The communication interface layer is used to handle communication and data exchange with external devices. Specifically, the communication interface layer can convert data from different devices into a format that can be recognized and processed inside the FPGA, and can also convert data inside the FPGA into a format required by external devices. In addition, a certain cache area is usually set to achieve flow control during data transmission to ensure smooth and reliable data transmission. The data exchange interface layer is used to provide a standard data transmission interface for communication between different internal modules. Specifically, the data exchange interface layer can provide functions such as data conversion, data buffering, and data verification.

[0079] In specific implementation, the logical association configuration data includes the association configuration data of the physical mapping layer, the communication interface layer, and the data exchange interface layer with the logical layer. Through the data path configuration data and the logical association configuration data, the mapping of the physical mapping layer, the communication interface layer, and the data exchange interface layer with the logical layer can be established. In practical applications, it can be pre-defined physical mapping definition layer, build general basic function blocks such as adders, multipliers, etc., build general input and output and parameter model interfaces, and build a general model resource pool. Pre-define the logic blocks in the logic layer and instantiate the logic blocks. Then, map the circuit elements (such as gates, triggers, etc.) on the logic layer to the physical elements on the FPGA chip, and perform layout and routing to establish the mapping between the physical mapping layer and the logic layer. Considering the efficiency and bandwidth limitations of data transmission, establish an interface from the logic layer to the physical layer to realize the communication between the elements of the logic layer and the elements of the physical layer. Considering the data processing speed and the relationship between the data, establish an interface for data exchange between the logic layer and the physical layer, including input and output ports and intermediate variables, to establish the mapping between the data exchange interface layer and the logic layer. Commonly used data exchange interfaces include FIFO and DMA (Direct Memory Access, direct memory access), etc.

[0080] In the technical solution of the embodiment of the present application, by dividing the physical layer into a physical mapping layer, a communication interface layer and a data exchange interface layer, and establishing a mapping between the physical mapping layer, the communication interface layer and the data exchange interface layer and the logical layer, the coupling degree between the modules can be reduced, making the modules more reusable and achieving higher resource utilization.

[0081] In some embodiments, the instantiated logic block includes a communication logic block, and the logic-associated configuration data includes input and output parameters and parameter models of the communication logic block, and protocol parameters and protocol channel data of the communication interface layer;

[0082] like Figure 4 As shown, S420 includes: S422, according to the data path configuration data, the input and output parameters and parameter model of the communication logic block are associated with the protocol parameters and protocol channel parameters of the communication interface layer, and a mapping between the communication interface layer and the communication logic block is established, wherein the parameter model is associated with the logic association configuration data.

[0083] The logic blocks of the logic layer include communication logic blocks, which are logic blocks used to implement data communication, and the number of communication logic blocks can be multiple. Specifically, the communication logic block can be a communication protocol CBB (Common Building Blocks) group composed of multiple communication protocol function blocks. The logical association configuration data includes the input and output parameters and parameter model of the communication logic block, as well as the protocol parameters and protocol channel data of the communication interface layer. Among them, the parameter model is a parameter model determined according to factors such as the type of data transmitted, the transmission rate, and the transmission mode. In this embodiment, the parameter model is associated with the communication-related logical association configuration data of the logical association layer. The protocol parameters include information such as data format, transmission rate, and verification, and the protocol channel refers to the physical connection between the communication function module and other modules.

[0084] In specific implementation, the mapping between the communication interface layer and the logic layer can be established by associating the input and output parameters and parameter model of the communication logic block with the protocol parameters and protocol channel parameters of the communication interface layer according to the data path configuration data. The association process can be regarded as a matching and coordination process to achieve access to the communication function, wherein the parameter model of the communication logic block is associated with the logic association configuration data to ensure smooth data interaction communication. For example, Figure 5 As shown, based on the data path configuration data, through the logical association layer, the mapping between the input and output parameters and parameter model of the communication protocol CBB and the sending channel, receiving channel and communication parameters of the communication interface layer can be established.

[0085] In the technical solution of the embodiment of the present application, by associating the input and output parameters and parameter model of the communication logic block with the protocol parameters and protocol channel parameters of the communication interface layer, a mapping between the communication interface layer and the communication logic block is established, which facilitates the modification, expansion and reconstruction of the communication logic block and the communication interface layer, and ensures good compatibility between different platforms or systems.

[0086] In some embodiments, the instantiated logic block includes a functional logic block, and the logic-associated configuration data includes input and output parameters and parameter models of the functional logic block, and signal data and data lines of a data exchange interface layer;

[0087] like Figure 4 As shown, S420 includes: S424, associating the input and output parameters of the functional logic block with the data transceiver channel of the communication logic block, and associating the input and output parameters and parameter model of the functional logic block with the signal data and data lines of the data exchange interface layer, and establishing a mapping between the data exchange interface layer and the logic layer.

[0088] The functional logic block refers to a functional block used to implement logic control. In this embodiment, the functional logic block includes a functional logic CBB group and an algorithm strategy CBB group. The logic association configuration data includes the input and output parameters and parameter models of the functional logic block, as well as the signal data and data lines of the data exchange interface layer. Among them, the input and output parameters of the functional logic block include the number of input ports and the bit width of each input port, that is, the data width of the input signal, the number of output ports and the bit width of each output port, that is, the data width of the output signal. The parameter model of the functional logic block includes other characteristics such as internal states such as the initial value of a register or a counter, timing information such as clock frequency, and power consumption delay. The signal data of the data exchange interface layer includes synchronization signals, timing signals, and check signals. In the data exchange interface layer, signals are transmitted through the physical layer, and the data link layer uses these signals to identify the start and end positions of the data frame and error detection. Data lines include unidirectional lines, bidirectional lines, and multidirectional lines, etc., which are designed according to different transmission rates, distances, and cost requirements.

[0089] In specific implementation, establishing a mapping between the functional logic block and the data exchange interface layer can be by associating the input and output parameters of the functional logic block with the data transceiver channel of the communication logic block. Specifically, it can be by connecting the input port of the functional logic block with the data sending channel of the communication logic block, connecting the output port of the functional logic block with the data receiving channel of the communication logic block, and associating the input and output parameters and parameter model of the functional logic block with the signal data and data lines of the data exchange interface layer, that is, corresponding the input parameters of the functional logic block to the corresponding data lines, and corresponding the reading of the output parameters to the corresponding data lines, so as to establish a mapping between the data exchange interface layer and the communication logic block, and realize the visualized data transmission and processing function of FPGA.

[0090] In the technical solution of the embodiment of the present application, by establishing a mapping between the data exchange interface layer and the communication function logic block, data transmission and processing functions are realized, so that each component has a high cohesion, the coupling degree of the system is reduced, and the maintainability of the system is improved.

[0091] In some embodiments, the physical mapping layer includes a configuration data block, a monitoring data block, a sampling data block, a control command data block, and an application function data block;

[0092] like Figure 4 As shown, S420 includes: S426, establishing mapping relationships between configuration data blocks, monitoring data blocks, sampling data blocks, control command data blocks and application function data blocks and logical layers respectively according to the logic function resource configuration data and data path configuration data of each data block in the logic association configuration data.

[0093] Logical function resource configuration data refers to the configuration data of logical function resources such as computer programs, algorithms, code libraries, and logic gates. The interface block of the physical mapping layer includes a configuration data block, a monitoring data block, a sampling data block, a control command data block, and an application function data block. Among them, the configuration data block can also be called a configuration interface block, and the configuration data block is a group of registers or memory units for storing the configuration information of the FPGA chip. In this embodiment, the configuration interface block includes a general configuration interface block and a dedicated configuration interface block, wherein the general configuration interface block refers to the configuration data used to store configuration data unrelated to business needs, and the dedicated configuration interface block refers to the configuration data used to store configuration data related to business needs. The monitoring data block is used to monitor the working status and performance parameters of the FPGA chip, which can provide data such as temperature, voltage, clock frequency, power consumption, etc. of the FPGA chip, as well as various error information and warning information. The sampling data block is used to capture the output signal or internal state of the FPGA chip, specifically, the input and output waveforms, counter values, state machine states, register contents, etc. of the FPGA chip can be captured, and stored in the internal buffer for subsequent processing. The control command data block is used to send control commands to the FPGA chip, such as start / stop operation, set clock frequency, reset state machine, etc. It can be implemented through special registers or memory units. The application function data block is the main logic part of the FPGA chip, which is used to implement various application functions. It can contain multiple modules, such as processor core, DMA controller, graphics processor, etc. In the physical mapping layer, the application function data block is usually split into multiple logical areas and corresponds to different physical resources of the FPGA chip.

[0094] In actual applications, the corresponding general configuration interface block can be generated according to the number of external communication links and the number of internal communication links of the FPGA, the corresponding special configuration interface block can be generated according to the configuration parameters such as the algorithm of the application function such as FPGA control protection, the general monitoring information data block can be generated according to the monitoring information requirements sent to the embedded software by the general function of the FPGA, the general sampling information data block can be generated according to the sampling information requirements sent to the embedded software by the application function such as FPGA control protection, the corresponding control command data block can be generated according to the control command parameters received from the embedded software by the application function such as FPGA control protection, and the corresponding application function data block can be generated according to the application data information sent to the embedded software by the application function such as FPGA control protection. Then, according to the logical function resource configuration data and data path configuration data of each data block in the logical association configuration data, the mapping relationship between the configuration data block, the monitoring data block, the sampling data block, the control command data block and the application function data block and the logical layer is established respectively. It is understandable that in order to ensure data interaction between the embedded platform and the FPGA design platform, the embedded platform also needs to be defined according to the FPGA's monitoring data block, acquisition data block, control command data block and application function data block, and generate the input, output, parameter and other model definition files of the above data blocks, and then send the generated input, output, parameter and other model definition files to the host computer visualization development platform to instantiate the FPGA's function blocks.

[0095] Specifically, it can be that according to the number of general configuration interface blocks and special configuration interface blocks, the logic function configuration resources are predefined, and the association relationship between the logic data output to the general configuration interface block and the special configuration interface block is established by wiring layout; according to the configuration capacity of the general monitoring data block, the sampling data block, and the application function data block, the corresponding logic data resources are predefined, and the association relationship between the logic data output to the general monitoring data block, the sampling data block, and the application function data block is established; according to the configuration capacity of the control command data, the corresponding logic data resources are predefined, and the association relationship between the control command data input and the logic data is established; according to the configuration capacity of the communication interface layer, the logical data resource channel for sending and receiving is predefined, and the association between the receiving channel and the logic data and the association between the logic data and the sending channel is established; and according to the interface requirements of the internal data exchange, the logical data resource channel for sending and receiving is predefined, and the association between the receiving channel and the logic data and the association between the logic data and the sending channel is established. The above-mentioned predefined logic function configuration resources refer to the allocation of logic resources to different applications or tasks in order to provide the required functions for specific applications.

[0096] In the technical solution of the embodiment of the present application, by establishing a mapping relationship between the configuration data block, the monitoring data block, the sampling data block, the control command data block and the application function data block and the logical layer, the design and implementation complexity of the system can be simplified, the development efficiency can be improved, and flexible configuration and adjustment can be performed for different application scenarios.

[0097] In some embodiments, the configuration data block performs data read and write operations through the RAM.

[0098] RAM memory generally refers to random access memory, which can be used for data reading and writing. In the present embodiment, the configuration data block performs data reading and writing operations through RAM, which means that the data of the general configuration data block and the special configuration data block are written into the RAM, and when the data needs to be used, the data is read from the RAM. In this way, data can be easily transferred between different devices without the need for chip-level hardware support. Furthermore, the storage capacity size and data transmission rate can be dynamically adjusted according to the needs of the application, thereby enhancing flexibility. It is understandable that in other implementations, the configuration data block can also read and write data through a memory including but not limited to RAM.

[0099] In the technical solution of the embodiment of the present application, by caching the data of the configuration data block into the RAM, the number of data exchanges with external devices can be reduced, and high-speed, low-latency data transmission and processing can be achieved. In addition, the size of the RAM, read and write speed and other parameters can be configured as needed to meet the needs of different application scenarios.

[0100] In some embodiments, the monitoring data block, the sampling data block, the control command data block, and the application function data block perform data read and write operations through the FIFO.

[0101] The FIFO memory is a first-in, first-out dual-port buffer, that is, the first data to enter it is the first to be removed, one of which is the input port of the memory, and the other port is the output port of the memory. In this embodiment, the monitoring data block, the sampling data block, the control command data block and the application function data block can be set to perform data read and write operations through the FIFO, that is, when the data in the monitoring data block, the sampling data block, the control command data block and the application function data block are generated, they are first written into the FIFO, and when these data need to be used, the data can be read from the FIFO, and after processing, the corresponding position in the FIFO is marked as an idle state, so that the next data is written. Specifically, the appropriate FIFO depth and width can be selected according to the actual application scenario and system requirements. FIFO can also be used for data flow control and synchronization, and can buffer input data to ensure the continuity and stability of the output data flow.

[0102] In the technical solution of the embodiment of the present application, data reading and writing operations are performed in a FIFO manner, which can better control and synchronize data flow, and can also dynamically adjust the storage capacity and data transmission rate according to the needs of the application, thereby enhancing flexibility.

[0103] In order to make a clearer description of the visual programming implementation method of the programmable logic device provided by the present application, the following is a Figure 6 , Attachment Figure 7 The specific embodiment includes the following steps:

[0104] S100, obtaining hierarchical division data of a programmable logic device, and dividing the interface layer of the programmable logic device into a physical layer, a logic association layer, and a logic layer according to the hierarchical division data.

[0105] like Figure 7 As shown, the visual framework diagram of FPGA includes a physical layer, a logic association layer and a logic layer. Among them, the physical layer includes a physical mapping layer, a communication interface layer and a data exchange interface layer. The physical mapping layer includes a plurality of general configuration data blocks (also called general configuration interface blocks), special configuration data blocks (also called special configuration interface blocks), monitoring data blocks, sampling data blocks, control command data blocks and application function data blocks. The logic layer includes a plurality of instantiated logic blocks and IP (Intellectual Property) function cores, such as a communication protocol CBB group, a functional logic CBB group, an algorithm strategy CBB group, and a sampling processing CBB group, among which the communication protocol CBB group belongs to the communication logic block, and the functional logic CBB group and the algorithm strategy CBB group belong to the functional logic block.

[0106] S200, obtaining logic association configuration data and identifiable data path configuration data of a programmable logic device.

[0107] The logical association configuration data includes the input and output parameters and parameter models of the communication function logic block, the input and output parameters and parameter models of the functional logic block, the communication protocol and communication channel data of the communication interface layer, and the signal data and data line data of the data exchange interface layer.

[0108] S422, according to the data path configuration data, the input and output parameters and parameter model of the communication logic block are associated with the protocol parameters and protocol channel parameters of the communication interface layer, and a mapping between the communication interface layer and the communication logic block is established, wherein the parameter model is associated with the logic association configuration data.

[0109] S424, associate the input and output parameters of the functional logic block with the data transceiver channel of the communication logic block, and associate the input and output parameters and parameter model of the functional logic block with the signal data and data line of the data exchange interface layer, and establish a mapping between the data exchange interface layer and the logic layer.

[0110] S426, establishing mapping relationships between configuration data blocks, monitoring data blocks, sampling data blocks, control command data blocks and application function data blocks and logical layers respectively according to the logic function resource configuration data and data path configuration data of each data block in the logic association configuration data.

[0111] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0112] Based on the same inventive concept, the embodiment of the present application also provides a visual programming implementation device for a programmable logic device for implementing the visual programming implementation method of the programmable logic device involved above. The implementation solution provided by the device to solve the problem is similar to the implementation solution recorded in the above method, so the specific limitations in the embodiments of the visual programming implementation device for one or more programmable logic devices provided below can refer to the limitations of the visual programming implementation method for programmable logic devices above, and will not be repeated here.

[0113] In some embodiments, Figure 8 As shown, a visual programming implementation device 800 for a programmable logic device is provided, comprising: a data acquisition module 810 and a data mapping module 820, wherein:

[0114] The data acquisition module 810 is used to acquire the logic-related configuration data and identifiable data path configuration data of the programmable logic device.

[0115] The data mapping module 820 is used to establish a mapping between the physical layer and the logical layer of the programmable logic device according to the data path configuration data and the logic association configuration data.

[0116] The logic layer includes a plurality of instantiated logic blocks, and the identifiable data path configuration data is obtained by converting the initial data path configuration data generated by the visualization development platform by the connected embedded platform.

[0117] In the above-mentioned visual programming implementation device of the programmable logic device, unlike the traditional method of converting the language of the written logic code through the synthesis tool to obtain the connection relationship configuration data of the programmable logic device, the identifiable data path configuration data is directly obtained by converting the initial data path configuration data generated by the visual development platform by the embedded platform, without the need for language conversion. In addition, by pre-building instantiated logic blocks, it is possible to establish a mapping between the physical layer and the logical layer according to the logical association configuration data and the data path configuration data, separate the underlying hardware device from the upper-level application program, and realize the decoupling and configurability of the physical layer and the logical layer. When the functional requirements change, the application function can be changed by modifying the configuration items of the logic block, thereby improving the data update efficiency, and being applicable to engineering sites with complex and changeable functional requirements, with greater flexibility and versatility.

[0118] In some embodiments, the data mapping module 820 is also used to establish a mapping between the physical mapping layer, the communication interface layer, the data exchange interface layer and the logical layer according to the data path configuration data and the logical association configuration data; the physical layer includes the physical mapping layer, the communication interface layer and the data exchange interface layer.

[0119] In some embodiments, the instantiated logic block includes a communication logic block, and the logic-associated configuration data includes input and output parameters and parameter models of the communication logic block, and protocol parameters and protocol channel data of the communication interface layer;

[0120] The data mapping module 820 is also used to associate the input and output parameters and parameter model of the communication logic block with the protocol parameters and protocol channel parameters of the communication interface layer according to the data path configuration data, and establish a mapping between the communication interface layer and the communication logic block, wherein the parameter model is associated with the logic association configuration data.

[0121] In some embodiments, the instantiated logic block includes a functional logic block, and the logic-associated configuration data includes input and output parameters and parameter models of the functional logic block, and signal data and data lines of a data exchange interface layer;

[0122] The data mapping module 820 is also used to associate the input and output parameters of the functional logic block with the data transceiver channel of the communication logic block, and to associate the input and output parameters and parameter model of the functional logic block with the signal data and data lines of the data exchange interface layer, so as to establish a mapping between the data exchange interface layer and the logic layer.

[0123] In some embodiments, the physical mapping layer includes a configuration data block, a monitoring data block, a sampling data block, a control command data block, and an application function data block;

[0124] The data mapping module 820 is also used to establish mapping relationships between configuration data blocks, monitoring data blocks, sampling data blocks, control command data blocks and application function data blocks and logical layers according to the logical function resource configuration data and data path configuration data of each data block in the logical association configuration data.

[0125] like Fig. 9 As shown, in some embodiments, the apparatus further includes a hierarchical division module 802 for acquiring hierarchical division data of the programmable logic device, and dividing the interface layer of the programmable logic device into a physical layer, a logical association layer and a logical layer according to the hierarchical division data.

[0126] Each module in the visual programming implementation device of the programmable logic device can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0127] In some embodiments, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Fig.10 As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a visual programming implementation method of a programmable logic device is implemented. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.

[0128] Those skilled in the art will understand that Fig.10 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0129] In some embodiments, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps of the above-mentioned method for implementing visual programming of a programmable logic device when executing the computer program.

[0130] In some embodiments, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the visual programming implementation method of the programmable logic device are implemented.

[0131] In some embodiments, a computer program product is provided, including a computer program, which implements the steps in the above-mentioned visual programming implementation method of a programmable logic device when executed by a processor.

[0132] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions.

[0133] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0134] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A method for implementing visual programming of a programmable logic device, characterized in that: The method comprises: Acquiring logic-related configuration data and identifiable data path configuration data of a programmable logic device; Establishing a mapping between a physical layer and a logical layer of the programmable logic device according to the data path configuration data and the logic association configuration data; The logic layer includes a plurality of instantiated logic blocks, and the identifiable data path configuration data is obtained by converting the initial data path configuration data generated by the visualization development platform by the connected embedded platform.

2. The method according to claim 1, characterized in that The step of establishing a mapping between a physical layer and a logical layer of the programmable logic device according to the data path configuration data and the identifiable logical association configuration data comprises: According to the data path configuration data and the logic association configuration data, a mapping between the physical mapping layer, the communication interface layer and the data exchange interface layer and the logic layer is established; the physical layer includes the physical mapping layer, the communication interface layer and the data exchange interface layer.

3. The method according to claim 2, characterized in that The instantiated logic block includes a communication logic block, and the logic association configuration data includes input and output parameters and parameter models of the communication logic block, and protocol parameters and protocol channel data of the communication interface layer; Establishing a mapping between a communication interface layer and the logic layer according to the data path configuration data and the logic association configuration data includes: According to the data path configuration data, the input and output parameters and parameter model of the communication logic block are associated with the protocol parameters and protocol channel parameters of the communication interface layer, and a mapping between the communication interface layer and the communication logic block is established, wherein the parameter model is associated with the logic association configuration data.

4. The method according to claim 3, characterized in that The instantiated logic block includes a functional logic block, and the logic association configuration data includes input and output parameters and parameter models of the functional logic block, and signal data and data lines of the data exchange interface layer; Establishing a mapping between a data exchange interface layer and the logic layer according to the data path configuration data and the logic association configuration data includes: The input and output parameters of the functional logic block are associated with the data transceiver channel of the communication logic block, and the input and output parameters and parameter model of the functional logic block are associated with the signal data and data lines of the data exchange interface layer to establish a mapping between the data exchange interface layer and the logic layer.

5. The method according to claim 2, characterized in that: The physical mapping layer includes a configuration data block, a monitoring data block, a sampling data block, a control command data block and an application function data block; Establishing the mapping between the physical mapping layer and the logical layer according to the data path configuration data and the logical association configuration data includes: According to the logical function resource configuration data of each data block in the logical association configuration data and the data path configuration data, a mapping relationship between the configuration data block, the monitoring data block, the sampling data block, the control command data block and the application function data block and the logical layer is established respectively.

6. The method according to claim 5, characterized in that The configuration data block performs data reading and writing operations through the RAM.

7. The method according to claim 5, characterized in that The monitoring data block, the sampling data block, the control command data block and the application function data block perform data reading and writing operations through FIFO.

8. The method according to any one of claims 1 to 7, further comprising: Obtaining hierarchical partitioning data of programmable logic devices; According to the hierarchical division data, the interface layer of the programmable logic device is divided into a physical layer, a logic association layer and a logic layer.

9. A visual programming implementation device for a programmable logic device, characterized in that: The device comprises: A data acquisition module, used to acquire logic-related configuration data and identifiable data path configuration data of a programmable logic device; A data mapping module, used to establish a mapping between the physical layer and the logical layer of the programmable logic device according to the data path configuration data and the logic association configuration data; The logic layer includes a plurality of instantiated logic blocks, and the identifiable data path configuration data is obtained by converting the initial data path configuration data generated by the visualization development platform by the connected embedded platform.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 8 are implemented.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

12. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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