34 results about "Fpga architecture" patented technology

This invention discloses a comprehensive identification test device and method based on software-defined radio technology, belonging to the field of avionics equipment testing. The device includes: a core processing and control unit, employing a multi-channel high-speed AD / DA and MPSoC FPGA architecture, supporting concurrent operation of various conventional aircraft identification functions through multiple internally integrated models; a radio frequency transceiver module, connected to the core processing and control unit, used for digital frequency conversion and analog-to-digital conversion of signals; a high-power radio frequency front-end component, internally equipped with multi-stage attenuation circuits and isolation devices, used for physical isolation and filtering attenuation of transmitted and received signals, ensuring its power covers the dynamic range of airborne received signals; and a remote control interface for receiving remote control commands to achieve automated test linkage. This invention allows direct connection to test the receiving performance of airborne equipment without the need for external high-power accessories, achieving a high degree of integration and automation of the test equipment, significantly improving detection and troubleshooting efficiency.

The invention discloses an FPGA (Field Programmable Gate Array) configuration architecture and an application method thereof. The architecture comprises FILO modules, a local shared configuration memory area and a distributed parameter storage area established between adjacent FILO module clusters, wherein the distributed parameter storage area is specially used for caching key configuration data of a current task execution period; a configuration memory area is shared globally, a high-bandwidth configuration memory is integrated on the top layer of the FPGA architecture, and all reconfigurable parameter sets of the full task process are stored persistently. And adding a temporary stack pointer and setting a corresponding pointing area. The application method comprises the steps of global configuration preloading, local dynamic loading and FILO module execution. According to the method, the performance, the energy efficiency and the resource utilization rate of the FPGA in a lightweight and dynamic application scene are greatly improved. The method can be widely applied to the field of programmable logic device system structures.

The invention relates to the technical field of standby power supply automatic switching, and provides an intelligent standby power supply automatic switching device suitable for multiple incoming lines of a distribution network and a control method thereof.The intelligent standby power supply automatic switching device comprises a digital processing module, an optical communication interface, a multi-incoming-line adaptive logic module, an intelligent standby power supply switching function module and a constant value and wave recording module; the optical communication interface transmits acquired switch position signals and maintenance pressing plate state signals to the digital processing module through optical fibers. The digital processing module adopts a multi-core CPU + FPGA architecture and is integrated with a time-frequency synchronization module, automatically generates spare power switching logic and transmits the spare power switching logic to the intelligent spare power switching function module; the intelligent spare power switching function module comprises a plurality of spare power switching modes. The method has the advantages that multiple incoming lines and complex topology are supported, N supply-N standby and other scenes of the distribution network are met, each power supply can be set on different buses according to a fixed value and can be set as an incoming line or outgoing line attribute, expansibility is high, and different requirements of current and long-term power supply attributes are met.

The invention relates to a chip verification method and system based on a double-FPGA architecture, and the method comprises the steps: deploying a verification platform on a first programmable logic device in a hardware circuit form, deploying a tested design on a second programmable logic device, and enabling the verification platform and the second programmable logic device to be interconnected through a hardware interface; the first programmable logic device comprises a control module, an excitation generation module, an expectation calculation module, an evaluation module, an excitation output module and a response input module; in response to external triggering, the control module jumps from idle to start, controls the excitation generation module to generate excitation, and transmits the excitation to the tested design through the excitation output module; the tested design generates a response signal based on excitation and transmits the response signal to the evaluation module through the response input module; the expectation calculation module receives an excitation calculation expectation result and transmits the result to the evaluation module; and the evaluation module compares the response with the expected result to generate a verification result. The method gets rid of software simulation dependence, shortens verification starting time, is close to a real chip use environment, and improves function verification reliability.

The invention discloses a novel VPSA method biogas decarbonization purification equipment intelligent control joint control system, belongs to the industrial automation and artificial intelligence fusion field, and comprises a global perception and data acquisition layer, an edge intelligent decision and control layer, an accurate execution and linkage control layer, and a cloud edge collaborative management and digital twinborn layer four-layer architecture. The global sensing layer is provided with a 48-node sensor network and a 10kHz acquisition card to complete data acquisition preprocessing; the edge decision-making layer carries a reinforcement learning algorithm and an LSTM-CNN model through an ARM + FPGA architecture; the precise execution layer realizes millisecond-level response through a high-speed execution mechanism and a Petri net linkage matrix; and the cloud side management layer realizes remote management and virtual debugging by relying on a cloud platform and a digital twin system, solves the problems of rigid control, weak fault early warning and the like of traditional equipment, and is suitable for the fields of biomass energy utilization and environmental protection engineering.

The disclosure provides an evaluation device of a FPGA interconnection architecture based on a graph neural network, which comprises: an input unit configured to obtain description information of a target FPGA architecture and corresponding timing report information; an intra-block graph construction unit configured to obtain corresponding wiring resource graphs and global features according to the description information conversion; a node frequency label extraction unit configured to obtain frequency information of critical path node occurrence according to the timing report information; and a prediction unit configured to obtain the routability and area delay product value of the target FPGA according to the obtained wiring resource graphs and global features and the frequency information of critical path node occurrence. The evaluation device provided in some embodiments of the disclosure can predict the routability and area delay product of the interconnection architecture through the GEF model, and significantly reduce the number of calls of the traditional evaluation tool.

The invention discloses a high-precision synchronization method and system for a distributed power system, the method comprises a host and a plurality of sub-machines which are interconnected with the host in a point-to-point manner and are to be synchronized, the host and the sub-machines both adopt a CPU + FPGA architecture, and a high-precision synchronization mechanism is realized in the FPGA. According to the synchronization mechanism, synchronization compensation time and synchronization errors are calculated through a plurality of message sending periods, the step length of an interval is adjusted in a self-adaptive mode by comparing the synchronization errors with a reasonable range, and high-precision synchronization of the master machine and the slave machine is carried out. Under the condition that the processor is non-inductive, extremely high synchronization precision is achieved through extremely low network overhead occupation, the complexity and cost of distributed system synchronization design construction are reduced, and the method has high engineering application value.

The application discloses a kind of based on bit-level sparsity software and hardware collaborative acceleration method and FPGA architecture, the method includes: based on bit-level serial arithmetic unit composition target array, based on coarse-grained coding method, operand is converted into the encoding representation for bit-level sparse calculation;Bit-level serial arithmetic unit is designed in cooperation with coarse-grained coding method;Based on lookup table resource characteristics, bit-level serial arithmetic unit is optimized;Based on target array, the product accumulation operation for encoding representation is executed;Based on distributed controller, through micro load balancing communication strategy, data flow and calculation scheduling in target array are managed.Based on coarse-grained coding method and the use of bit-level serial arithmetic unit, while maintaining the accuracy of calculation, information processing density and hardware resource utilization are improved;Based on micro load balancing communication strategy, the uncertainty of calculation time and load imbalance are improved, and then the product accumulation operation efficiency and resource utilization of FPGA platform are improved.

The invention discloses audio equipment operation monitoring equipment and a use method thereof, and the equipment comprises a housing, a monitoring assembly used for monitoring audio equipment, and a supporting assembly used for supporting the housing. The monitoring assembly comprises a signal processing module, a multi-channel signal acquisition module, an analog-to-digital conversion module, a synchronization module, a storage module, a power supply module, an alarm module, a communication module and a touch control chip. The multi-channel signal acquisition module is composed of an acquisition chip, an amplifier and a filter. Through cooperation of the multichannel signal acquisition module, the high-precision ADC chip and the self-adaptive impedance matching circuit, synchronous high-precision acquisition of multichannel audio signals is realized, the accuracy and stability of signal acquisition are improved, the signal processing module adopts a dual-core DSP + FPGA architecture, a real-time Fourier transform engine is built in, and the real-time Fourier transform engine is built in the signal processing module. Complex audio signals can be rapidly processed, the analysis requirement of high real-time performance is met, and the problems that a traditional audio analyzer is complex in operation and single in function are effectively solved.

The invention belongs to the technical field of PGK systems, and particularly relates to a precise guidance assembly control system and method based on ARM + FPGA. A real-time interface unit is constructed through an ARM + FPGA architecture, deep integration of guidance and control functions is achieved from the hardware level, the problem of data transmission delay of a traditional separated design is thoroughly solved, and through dual-core collaborative division of labor (the ARM is responsible for logic decision and task scheduling, and the FPGA is responsible for high-speed data processing and track correction instruction execution), the real-time interface unit is constructed, and the real-time interface unit is constructed. The track correction response time is shortened to a millisecond level, and the real-time performance and the high-speed performance of a control system are effectively guaranteed; meanwhile, communication links and redundant hardware between subsystems are reduced through the integrated architecture, the overall utilization rate and the anti-jamming capability of the system are remarkably improved, the precise guidance requirement of the high-rotation shell in the complex flight environment is met, and the incidental injury risk of civilians caused by insufficient precision of a traditional shell is further reduced.

The invention provides an FPGA interconnection architecture evaluation device based on a graph neural network, and the device comprises an input unit which is used for obtaining the description information of a target FPGA architecture and the corresponding time sequence report information; the in-block graph construction unit is used for obtaining a corresponding wiring resource graph and global features according to description information conversion; the node frequency label extraction unit is used for counting frequency information of key path nodes according to the time sequence report information; and the prediction unit is used for acquiring the accessibility and the area delay product value of the target FPGA according to the acquired wiring resource map, the global features and the frequency information of the key path nodes. The evaluation device provided in some embodiments of the disclosure can predict the accessibility and the area delay product of the interconnection architecture through the GEF model, and the calling times of a traditional evaluation tool are significantly reduced.

The invention discloses a broadband beam pointing switching method based on an FPGA, and belongs to the technical field of digital phased arrays. The method comprises the steps that the FPGA receives and caches array configuration parameters; time delay filter coefficients and phase shifter coefficients of the array elements are calculated in parallel based on a singing function and a cordic algorithm; quantizing the coefficients, and pre-storing the quantized coefficients in an RAM (Random Access Memory) according to beam pointing; judging beam switching according to an automatic timing or external instruction mode, reading a coefficient corresponding to a target direction, and issuing the coefficient to each processing unit; an FIR filter and a phase shifter are reconfigured, and broadband signal time domain beam forming is achieved through a multi-phase filtering structure; and carrying out gain normalization and truncation correction on the composite signal and then outputting the composite signal. According to the invention, a traditional DSP + FPGA architecture is abandoned, the FPGA independently completes coefficient calculation and beam forming, through pre-storage, assembly line issuing and multi-phase processing, the beam pointing switching speed and the synthesis efficiency are significantly improved, and the method is suitable for broadband beam forming systems with high real-time requirements, such as radar and communication.

The invention discloses an avionic bus multi-protocol module based on software definition, and belongs to the technical field of avionics. The hardware and the drive of the module adopt a common platform design; the hardware is based on an FPGA architecture and comprises an FPGA module, an interface circuit, an auxiliary circuit and a storage space, and an integrated hardware platform is formed. The FPGA module is configured to automatically load the mcs solidification file from the storage space after being powered on, and different avionics bus functions are achieved through software definition; and the driver is a PCIe driver, is used as an interface of logic and application software, supports message communication and access to the storage space, and adopts a uniform data format. Through a software definition mode, a single hardware platform can support multiple avionics bus protocols, the problems that in the prior art, due to deep binding of hardware and protocols, the platform cannot be reused, and testing equipment is complex are solved, and the research and development cost can be effectively saved.

The application discloses a kind of multi-modal pipeline detection data acquisition systems based on FPGA architecture, ultrasonic detection module is used to generate 8 40kHz pulse excitation signal produces ultrasonic wave, and AD9226 analog-digital converter is controlled to collect echo data, and after being internally cached, original sampling data is output through high-speed interface;Image detection module is used to collect the image data output by high-definition image sensor, executes gray scale conversion, filtering, sobel edge detection and morphological operation preprocessing, and outputs the processed image data through fiber interface, and displays on HDMI display after being cached;Two kinds of modal data are accurately time-aligned and uniformly transmitted in the system interior.This application integrates ultrasonic detection and image detection processing, transmission functions in one system, realizes the synchronous acquisition and processing of multi-dimensional information of pipeline inner wall, significantly improves the integration and data consistency of detection system, and is suitable for high-precision, low-delay acquisition and transmission of multi-modal sensing data in industrial pipeline detection equipment.

The invention discloses an FPGA routing congestion prediction method based on a heterogeneous graph neural network, and the method comprises the steps: obtaining a netlist file in an FPGA design process, extracting the topological information of the file, and constructing a netlist subgraph; fPGA architecture information is obtained, and an architecture subgraph is constructed according to the architecture information; obtaining a layout file in the FPGA design process, extracting position information of each block in the file to construct a spatial mapping edge, and projecting nodes in the netlist sub-graph to the architecture sub-graph through the spatial mapping edge to obtain an integrated heterogeneous graph; constructing a heterogeneous graph neural network matched with the heterogeneous graph, wherein the heterogeneous graph neural network comprises a feature initialization module, a message passing module and a reading module; a data set is constructed according to the heterogeneous graph to train a heterogeneous graph neural network, and a neural network structure search strategy is used to optimize a message passing module; and inputting the heterogeneous graph into the heterogeneous graph neural network to obtain routing congestion information. According to the method, the accuracy of the FPGA routing congestion prediction result can be improved, the generalization ability is higher, and the time for reasoning, training and data preprocessing is shortened.

This invention provides an automated optimization method for efficient deployment of neural networks on FPGAs, relating to the fields of deep learning and hardware acceleration technology. The method includes: receiving the original neural network model and hardware constraint information; parsing to obtain quantization operators; generating a candidate precision configuration combination set through two-level filtering; constructing a graph-structured perceptron based on the target FPGA architecture to predict hardware resource consumption under each configuration; constructing a differential objective function that integrates task loss and weighted quantization error; solving for the initial mixed precision configuration using an adaptive penalized augmented Lagrangian method under hardware constraints; progressively expanding the neighborhood and replacing configurations through hierarchical neighborhood search to obtain the final configuration; generating hardware description code for both fixed-point and floating-point formats and calling the backend toolchain to output bitstream files. This invention achieves automated precision configuration while satisfying FPGA resource and timing constraints, significantly improving inference energy efficiency and deployment efficiency.

The invention discloses a dual-redundancy communication chip and an interaction method thereof. Wherein the dual-redundancy communication chip comprises an ARM (Advanced RISC Machines) processor, a field programmable gate array (FPGA) processor, a dual-redundancy Ethernet bare core, a dual-redundancy controller area network bus (CAN) transceiver bare core and an information transmission bus transceiver bare core; and the FPGA processor is configured to communicate with the ARM processor through an AXI bus, obtain a first upper computer instruction issued by an upper computer through the ARM processor, and configure the first interface and the second interface through the first upper computer instruction so as to realize parallel data interaction between the first interface and the second interface. In the embodiment of the invention, an ARM + FPGA architecture is adopted to replace a traditional mode of taking a computer mainboard as a center, the redundant interfaces directly finish data forwarding in the SoC without being transferred through an external bus or the mainboard, and a'center transfer 'link of the traditional architecture is skipped, so that parallel data interaction between the redundant interfaces is realized.

The application discloses a memory-compute FPGA architecture. Memory-compute cores, memory blocks and logic function blocks used for replacing part of the logic function blocks are arranged in a row-column array and arranged in an island type architecture. In the memory-compute cores, there are SRAMs arranged in a row-column array, the SRAMs store one-bit data, the output ends of an address decoding circuit are connected with each row of the SRAM array, the output ends of a write control circuit are connected with each column of the SRAM array, each eight columns of the SRAM array and an input register are connected with an 8-bit input port of an addition tree through a multiplexer and eight NOR gates, and the output port of the addition tree is connected with an output register through a shift and addition module and a quantization module in sequence. The application realizes in-memory computation on the FPGA, utilizes the parallelism and reconfigurability of the FPGA to support mapping of various networks, and utilizes in-memory computation technology to reduce data movement and further reduce computation power consumption.

The invention discloses a PCIE (Peripheral Component Interface Express)-to-EMMC (Embedded Multi Media Card) bridging method based on a Feiteng D2000 + FPGA (Field Programmable Gate Array) architecture. The method comprises a bridging connection step: connecting a Feiteng processor D2000 and an FPGA, and connecting the FPGA and an EMMC storage chip; the bridging operation step comprises the following steps of: 1, electrifying a Feiteng processor D2000, an FPGA (Field Programmable Gate Array) and an EMMC (Embedded Multi Media Card) storage chip; step 2, after the FPGA is loaded, keeping resetting the Feiteng processor D2000; step 3, resetting the EMMC storage chip by using an FPGA (Field Programmable Gate Array), and initializing the EMMC storage chip; 4, judging whether initialization of the EMMC storage chip is successful or not; if not, the FPGA is used for resetting and initializing the EMMC storage chip again; if the mapping is successful, the FPGA maps the address space of the EMMC storage chip to the function register space of the PCIE IP core through the AXI bus; step 5, the FPGA releases the reset of the Feiteng processor D2000; 6, after the Feiteng processor D2000 loads the program, PCIE enumeration operation is carried out, and address space is distributed to the FPGA end equipment.

The application discloses a photovoltaic power generation system real-time simulation method based on FPGA, which comprises the following steps: 1) FPGA modeling of the photovoltaic electrical system: establishing a photovoltaic component output characteristic equation suitable for the FPGA architecture; using a numerical integration method to perform difference on passive elements in the photovoltaic electrical system to obtain an equivalent circuit model in the form of an equivalent calculation admittance and a historical item current source in parallel; 2) FPGA modeling of the photovoltaic control system based on different photovoltaic control strategies. The simulation method has high hardware parallelism and time parallelism, high simulation precision, fast simulation speed, flexible semi-custom integrated circuit design, complete programmable and reconfigurable capability, and reduced simulation cost.

The invention discloses a calibration device and a calibration method based on a 24-bit capacitance-to-digital converter, and belongs to the field of high-precision analog-to-digital conversion. The device is used for circuit calibration and test of the 24-bit capacitance-to-digital converter and comprises a hardware part and a software part, the hardware part adopts an acquisition control panel with an SOC + FPGA architecture, and the software adopts a Labview architecture. Synchronous sampling is carried out through the two customized sockets, so that the capacitance value and voltage calibration of the capacitor is realized; the to-be-calibrated chip and the TS temperature sensor are placed in the same cavity through the customized socket, so that the temperature calibration error is reduced; sHLD signals acquired by the FPGA can be converted into excitation sources, but data acquisition is abnormal, two sets of FPGA programs are adopted, one set is used for excitation calibration, and the other set is used for capacitance, voltage and temperature calibration and testing; and automatic control is facilitated. The device mainly comprises an ADC general test platform, a 24-bit capacitance digital converter calibration daughter board, a high-precision DA, a TS temperature sensor, a customized socket and the like.

The application provides a high-speed ADC test efficiency optimization method based on an ATE external SoC, and has the characteristics that it comprises the following steps: step 1, starting a test system, and issuing basic parameters by an ATE; step 2, a signal source applies a preset excitation signal to a to-be-tested ADC, and the ADC outputs a high-speed digital sampling data stream; step 3, the ADC transmits the sampling data stream to a PL end of a ZYNQ SoC; step 4, the PL end completes system clock domain conversion; step 5, a PS end completes ADC static and dynamic parameter calculation based on cached data; and step 9, after the test is completed, an ATE issues a test termination instruction to complete the ADC parameter test. The application solves the core contradiction between high-speed collection and low-speed calculation of the ATE external FPGA architecture from the architecture level, greatly improves the adaptive flexibility and reusability of the test scheme, and creates a reliability guarantee system integrating self-diagnosis and full-process automatic control.

The application relates to a parsing and drawing method based on a commercial Xilinx Virtex-7 FPGA chip resource model, which comprises the following steps: Virtex-7 FPGA architecture system files in.xml format are parsed, Virtex-7 FPGA chip attribute information is obtained, and the attribute information is stored in a first structure; a netlist circuit file in.net format is parsed, resource information of the netlist circuit file is obtained, and the resource information is stored in a cluster netlist class; a circuit layout file in.place format is parsed, resource information of the circuit layout file is obtained, and the resource information is stored in a second structure; a Virtex-7 FPGA chip architecture, a layout block distribution and network connection of a circuit are drawn according to the first structure, the cluster netlist class and the second structure; a circuit routing file in.route format is parsed, resource information of the circuit routing file is obtained, and a track vector is stored; and according to the cluster netlist class, the resource information of the circuit routing file and a preset routing resource graph, wiring connection and key wiring path delay of the circuit are drawn. The application has high overall operation efficiency and low resource consumption.

The application discloses a kind of satellite integrated electronic systems.The system uses heterogeneous FPGA architecture, and satellite management module is deployed in the first FPGA chip, and telemetry and control module and encryption and decryption module are integrated in the second FPGA chip.System realizes fault isolation through the independent power domain and reset domain design of telemetry and control and encryption and decryption module, ensures that telemetry and control link will not be interrupted through the hardware bypass channel in the second FPGA chip, and improves system reliability.Encryption and decryption module uses encryption mode mapping diagram and management system, supports dynamic key management mechanism triggered by three events of periodic switching, mapping diagram update and periodic parameter update, can flexibly configure encryption strategy according to on-orbit task demand, and improves the security and adaptability of system.The application effectively solves the problems in the prior art, such as difficulty in balancing chip performance and cost, low integration, and single-point failure leading to whole machine failure, and is particularly suitable for small satellite platforms with strict requirements on cost, size and reliability.

The application provides a carrier wave synchronization control method of a motor controller with a distributed FPGA architecture. The motor controller comprises a master control unit and three sub-control units. The FPGA of each sub-control unit cyclically performs the following operations: receiving communication data sent by the master control unit and extracting to-be-verified control information and to-be-verified synchronization information therefrom; judging whether the to-be-verified synchronization information is valid, and determining the update mode of the carrier generation time, the current synchronization information and the current control information according to the judgment result; and generating the carrier and the PWM control signal of the phase corresponding to the sub-control unit based on the current control information and the carrier clock period of the FPGA of the sub-control unit from the updated carrier generation time. The control method provided by the application can effectively solve the phase carrier synchronization problem of the distributed motor controller under high-frequency switching control.

The invention relates to the field of semiconductors, in particular to a multilayer stacked FPGA (Field Programmable Gate Array) architecture based on TSV (Through Silicon Via) vertical interconnection. According to the multi-layer stacked FPGA architecture based on TSV vertical interconnection, interconnection of multiple layers of tube cores in the vertical direction can be achieved, a 3D packaging FPGA chip with more logic resources is stacked, and due to the fact that vertical interconnection signals are directly transmitted to other tube cores through the TSV holes, the vertical interconnection signals can be directly transmitted to other tube cores through the TSV holes; compared with a 2.5 D packaging FPGA chip based on silicon interposer long overline interconnection, the area, the power consumption and the time delay are reduced in the aspect of signal data transmission.

The present disclosure provides a field programmable gate array structure, an out-of-band bridging system, a method and a server for realizing out-of-band bridging, relates to the technical field of computers, and particularly relates to a server. The specific implementation scheme is as follows: the field programmable gate array structure comprises at least two first data interface modules, at least two second data interface modules and a cache module, each first data interface module is matched with each in-band data interface module, each second data interface module is matched with each management data interface module, the cache module is used for caching data of each first data interface module and data of each second data interface module, and each second data interface module performs data transmission with at least two first data interface modules through the cache module.

The invention discloses a signal self-correlation detection FPGA architecture, and relates to the technical field of signal processing. According to the invention, a storage module is formed by two dual-port RAMs with the maximum sliding window size, update items are sequentially stored according to an address sequence through a first dual-port RAM, and the update items are products of signal data and conjugates of signal data before a preset time delay of the update items; sequentially storing the accumulated sum of the current update item and the previous update item according to the address sequence through a second dual-port RAM, wherein the total accumulated item number is equal to the address; and on the basis of this, according to the size of the sliding window, obtaining an update item discarded after the sliding window from the first dual-port RAM in real time, and obtaining a historical accumulation item corresponding to the current sliding window from the second dual-port RAM, thereby calculating an autocorrelation function value of the signal under the preset time delay in the current sliding window. The self-correlation detection FPGA architecture supports dynamic window adjustment and can adapt to different signal scenes.

The application relates to a FPGA chip model analysis drawing method and device, the method comprises the following steps: obtaining chip and circuit design information; according to the chip and circuit design information, chip structure data of the FPGA is obtained by analysis, and a structure diagram of the FPGA is obtained by drawing according to the chip structure data; according to the chip and circuit design information, network data and circuit layout data of the FPGA are obtained by reverse analysis, and a layout diagram and an interconnection relationship diagram of the circuit layout of the FPGA are obtained by drawing on the structure diagram according to the network data and the circuit layout data; according to the chip and circuit design information, circuit wiring data of the FPGA is obtained by reverse analysis, and a wiring diagram of the FPGA is obtained by drawing on the layout diagram according to the circuit wiring data. The analysis drawing method uses resource analysis in different stages to complete data analysis work, and uses a drawing algorithm to complete the visualization work of the chip structure, the circuit layout and the circuit wiring stage, so that the commercial FPGA architecture design and the EDA algorithm research in the academic field are met.

The invention provides a novel single-contact nLED display gray scale modulation method and system. According to the invention, the control module based on the FPGA architecture is adopted to realize single-contact operation of the nLED; establishing a relation curve between the display brightness and the driving voltage of the single-contact nLED when the single-contact nLED works; a power law distribution nonlinear relational expression between human eye perception brightness and physical display brightness and a relational curve between gray levels and PWM modulation signal duty ratios are obtained, and then driving voltages corresponding to 16 gray levels and the PWM modulation signal duty ratios used for gray level nonlinear correction are obtained. And finally, establishing a 16-level PWM modulation signal lookup table according to the driving voltages corresponding to the 16 gray levels and the PWM modulation signal duty ratio for gray level nonlinear correction, wherein the 16-level PWM modulation signal lookup table is used for realizing gray level modulation of single-contact nLED display.