122 results about "Fpga architecture" patented technology

An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I / O blocks on the periphery. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The B16×16 tile is a nesting of a B2×2 tile that includes a two by two array of four B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. The expressway routing channels M1, M2, and M3 are segmented, and between each of the segments in the expressway routing channels M1, M2, and M3 are disposed extensions that can extend the expressway routing channel M1, M2, or M3 an identical distance along the same direction. The expressway routing channels M1, M2, and M3 run both vertically through every column and horizontally through every row of B2×2 tiles. At the intersections of each of the expressway routing channels M1, M2, and M3 in the horizontal direction with the expressway routing channels M1, M2 and M3 in the vertical direction is an expressway turn (E-turn) disposed at the center of each B2×2 tile. An E-turn is a passive device that includes a matrix of reprogrammable switches. The reprogrammable switches are preferably a pass device controlled by an SRAM bit. The interconnect conductors in the expressway routing channels M1, M2 and M3 that are fed into an E-turn may be coupled to many of the other interconnect conductors in the expressway routing channels M1, M2 and M3 that come into the E-turn by the programmable switches. Further, the interconnect conductors in the expressway routing channels M1, M2 and M3 that are fed into an E-turn continue in the same direction through the E-turn, even though the interconnect conductors are coupled to other interconnect conductors by the reprogrammable switches.

The invention relates to a picture processing method, a task data processing method and a device. The method comprises the following steps of: using the processing units corresponding to each sub-structure in a machine learning model to execute the corresponding sub-tasks, wherien the at least part of the processing units comprise FPGA units;obtaining the pictures to be processed; extracting the text features in the picture to be processed; determining a candidate text box of any angle in the picture to be processed according to the text features; performing pooling processing on each candidate text box to rotate a region of interest, and projecting each candidate text box onto a feature map of a fixed size to obtain a text box feature map corresponding to each candidate text box; recognizing a text in the text box feature map to obtain a text recognition result. The present application can process data in parallel to realize the picture processing method through the FPGA architecture,and can improve the accuracy and efficiency of text recognition in the picture to be processed while reducing cost and power consumption.

An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16x16 tiles arranged in a rectangular array and enclosed by I / O blocks on the periphery. On each of the four sides of a B16x16 tile, and also associated with each of the I / O blocks is a freeway routing channel. A B16x16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the four clusters includes first and second LUT3s, a LUT2, and a DFF. Each of the LUT3s have first, second, and third inputs and a single output. Each of the LUT2s have first and second inputs and a single output. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUT3s are muliplexed to the input of DFF, and symmetrized with the output of the DFF to form first and second outputs of each of the clusters.

A field programmable gate array (FPGA) and method of reconfiguring a FPGA are disclosed. The FPGA includes a plurality of logic elements interconnected with reconfigurable switches and at least horizontal and vertical direct links. A memory is coupled to the reconfigurable switches, the memory being configured to store at least two run time configurations. The reconfigurable switches are reconfigurable based on a selected run time configuration stored in the memory. The memory may be a nanoelectronic random access memory (RAM). The memory may be configured to store the at least two run time configurations for at least four logic elements. Each logic element may include a look-up-table (LUT), a flip-flop, inputs and outputs. Each logic element may include dedicated carry logic. At least four logic elements may be interconnected with diagonal direct links.

A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.