55 results about "Fpga architecture" patented technology

The invention belongs to the technical field of parallel robot controllers, and discloses a high-performance parallel robot controller based on an arm + fpga architecture, through deep heterogeneous fusion of an ARM and an FPGA, the control period is shortened to be within 10 microseconds, the trajectory tracking error is controlled to be 0.1 mm or below, and the performance bottleneck of a traditional architecture in a high-speed scene is solved; the multi-core ARM undertakes complex tasks such as global trajectory planning and dynamics solution, and realizes parallel processing by means of an NEON instruction set; the FPGA fully releases the hardware parallel characteristic of the FPGA, real-time tasks such as multi-axis motion control and sensor data fusion are synchronously completed through a distributed logic unit, and a complex decision-real-time execution assembly line cooperation mode is formed. Inertial parameters and load changes of the mechanical arm are estimated in real time through an LSTM neural network, and feedforward compensation is carried out on interference such as mechanical vibration and load abrupt change in combination with an extended state observer achieved through FPGA hardware; the innovatively designed double closed-loop control architecture supports seamless switching between a force control mode and a position control mode.

The invention provides a full-link detection and trusted industrial control method and system based on a domestic chip, and relates to the technical field of industrial automation and information security. The system comprises a security calculation module which is constructed by integrating a TPM (Trusted Platform Module) in a domestic chip; the special hardware encryption acceleration module is designed based on an ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array) architecture and is integrated in a domestic chip; the trusted execution environment module is constructed based on a security isolation technology; the anomaly detection module is constructed based on a pulse neural network; the block chain auditing module is constructed based on a block chain framework; the dynamic security policy engine is used to automatically trigger a security response policy. The invention constructs an integrated industrial safety control system based on a domestic chip, and the system is especially suitable for intelligent manufacturing and high-safety-level industrial scenes. The problems that in the prior art, full-link safe starting cannot be achieved in a localized chip environment, an efficient encryption and trusted execution environment is lacked, and the real-time anomaly detection and log auditing capacity is insufficient are solved.

The invention discloses a space-time image texture angle detection and discrimination method and system, and belongs to the field of visual flow measurement instruments. According to the design, a Zynq series processor with an ARM + FPGA architecture is used as a core, and a system module comprises a PS host control end, a PL end texture enhancement module, a two-dimensional Fourier transform module, a frequency spectrum logarithm transform module, a Gaussian filter module and an image segmentation and texture angle detection and judgment module. Wherein the texture enhancement module inhibits noise interference and enhances the continuity of effective textures; the two-dimensional Fourier transform module converts the information of the spatial domain image to a frequency domain; the frequency spectrum logarithmic transformation module is used for carrying out logarithmic magnitude spectrum calculation on the transformed spectrogram so as to improve the visibility of a low-amplitude component; and the image segmentation and texture angle detection and discrimination module carries out angle detection and discrimination after effective and invalid signals are separated, and finally outputs an angle detection result. The method can be applied to a river surface flow velocity measurement system based on a space-time image velocity measurement method, and the adaptability and efficiency of flow measurement in complex scenes can be improved.

The invention discloses a satellite integrated electronic system. According to the system, a heterogeneous FPGA architecture is adopted, a satellite service management module is deployed on a first FPGA chip, and a measurement and control module and an encryption and decryption module are integrated on a second FPGA chip. The system realizes fault isolation through the design of an independent power domain and a reset domain of the measurement and control and encryption and decryption module, ensures that a measurement and control link is not interrupted through a hardware bypass channel in the second FPGA chip, and improves the reliability of the system. The encryption and decryption module adopts an encryption mode mapping graph and management system, supports a dynamic key management mechanism triggered based on three events of periodic switching, mapping graph updating and periodic parameter updating, can flexibly configure an encryption strategy according to an on-orbit task demand, and improves the security and adaptability of the system. The problems that in the prior art, chip performance and cost are difficult to balance, the integration level is low, and a whole machine fails due to a single-point fault are effectively solved, and the method is particularly suitable for a microsatellite platform with strict requirements for cost, size and reliability.

This invention discloses a comprehensive identification test device and method based on software-defined radio technology, belonging to the field of avionics equipment testing. The device includes: a core processing and control unit, employing a multi-channel high-speed AD / DA and MPSoC FPGA architecture, supporting concurrent operation of various conventional aircraft identification functions through multiple internally integrated models; a radio frequency transceiver module, connected to the core processing and control unit, used for digital frequency conversion and analog-to-digital conversion of signals; a high-power radio frequency front-end component, internally equipped with multi-stage attenuation circuits and isolation devices, used for physical isolation and filtering attenuation of transmitted and received signals, ensuring its power covers the dynamic range of airborne received signals; and a remote control interface for receiving remote control commands to achieve automated test linkage. This invention allows direct connection to test the receiving performance of airborne equipment without the need for external high-power accessories, achieving a high degree of integration and automation of the test equipment, significantly improving detection and troubleshooting efficiency.

The invention discloses an FPGA (Field Programmable Gate Array) configuration architecture and an application method thereof. The architecture comprises FILO modules, a local shared configuration memory area and a distributed parameter storage area established between adjacent FILO module clusters, wherein the distributed parameter storage area is specially used for caching key configuration data of a current task execution period; a configuration memory area is shared globally, a high-bandwidth configuration memory is integrated on the top layer of the FPGA architecture, and all reconfigurable parameter sets of the full task process are stored persistently. And adding a temporary stack pointer and setting a corresponding pointing area. The application method comprises the steps of global configuration preloading, local dynamic loading and FILO module execution. According to the method, the performance, the energy efficiency and the resource utilization rate of the FPGA in a lightweight and dynamic application scene are greatly improved. The method can be widely applied to the field of programmable logic device system structures.

The invention provides an autonomous and controllable real-time simulation platform based on CPU and FPGA architecture development, and relates to the technical field of real-time simulation, the platform executes operation of an operating system and a complex model through a CPU, the FPGA completes nanosecond I / O refresh and high-speed calculation in parallel, the two are cooperated through a PCIe bus, and the real-time simulation platform is developed through the FPGA. Hard real-time calculation of the fuel cell model of electric-thermal-fluid multi-physics field coupling is realized; and the digital quantity output by the model is instantly converted into real voltage, temperature, pressure and flow through the FPGA and is reinjected into the tested FCCU, so that the controller completes closed-loop control, fault diagnosis and limit working condition verification under the condition of no physical pile.

The invention relates to the technical field of standby power supply automatic switching, and provides an intelligent standby power supply automatic switching device suitable for multiple incoming lines of a distribution network and a control method thereof.The intelligent standby power supply automatic switching device comprises a digital processing module, an optical communication interface, a multi-incoming-line adaptive logic module, an intelligent standby power supply switching function module and a constant value and wave recording module; the optical communication interface transmits acquired switch position signals and maintenance pressing plate state signals to the digital processing module through optical fibers. The digital processing module adopts a multi-core CPU + FPGA architecture and is integrated with a time-frequency synchronization module, automatically generates spare power switching logic and transmits the spare power switching logic to the intelligent spare power switching function module; the intelligent spare power switching function module comprises a plurality of spare power switching modes. The method has the advantages that multiple incoming lines and complex topology are supported, N supply-N standby and other scenes of the distribution network are met, each power supply can be set on different buses according to a fixed value and can be set as an incoming line or outgoing line attribute, expansibility is high, and different requirements of current and long-term power supply attributes are met.

The invention relates to a chip verification method and system based on a double-FPGA architecture, and the method comprises the steps: deploying a verification platform on a first programmable logic device in a hardware circuit form, deploying a tested design on a second programmable logic device, and enabling the verification platform and the second programmable logic device to be interconnected through a hardware interface; the first programmable logic device comprises a control module, an excitation generation module, an expectation calculation module, an evaluation module, an excitation output module and a response input module; in response to external triggering, the control module jumps from idle to start, controls the excitation generation module to generate excitation, and transmits the excitation to the tested design through the excitation output module; the tested design generates a response signal based on excitation and transmits the response signal to the evaluation module through the response input module; the expectation calculation module receives an excitation calculation expectation result and transmits the result to the evaluation module; and the evaluation module compares the response with the expected result to generate a verification result. The method gets rid of software simulation dependence, shortens verification starting time, is close to a real chip use environment, and improves function verification reliability.

The invention discloses a novel VPSA method biogas decarbonization purification equipment intelligent control joint control system, belongs to the industrial automation and artificial intelligence fusion field, and comprises a global perception and data acquisition layer, an edge intelligent decision and control layer, an accurate execution and linkage control layer, and a cloud edge collaborative management and digital twinborn layer four-layer architecture. The global sensing layer is provided with a 48-node sensor network and a 10kHz acquisition card to complete data acquisition preprocessing; the edge decision-making layer carries a reinforcement learning algorithm and an LSTM-CNN model through an ARM + FPGA architecture; the precise execution layer realizes millisecond-level response through a high-speed execution mechanism and a Petri net linkage matrix; and the cloud side management layer realizes remote management and virtual debugging by relying on a cloud platform and a digital twin system, solves the problems of rigid control, weak fault early warning and the like of traditional equipment, and is suitable for the fields of biomass energy utilization and environmental protection engineering.

The disclosure provides an evaluation device of a FPGA interconnection architecture based on a graph neural network, which comprises: an input unit configured to obtain description information of a target FPGA architecture and corresponding timing report information; an intra-block graph construction unit configured to obtain corresponding wiring resource graphs and global features according to the description information conversion; a node frequency label extraction unit configured to obtain frequency information of critical path node occurrence according to the timing report information; and a prediction unit configured to obtain the routability and area delay product value of the target FPGA according to the obtained wiring resource graphs and global features and the frequency information of critical path node occurrence. The evaluation device provided in some embodiments of the disclosure can predict the routability and area delay product of the interconnection architecture through the GEF model, and significantly reduce the number of calls of the traditional evaluation tool.

The invention discloses a high-precision synchronization method and system for a distributed power system, the method comprises a host and a plurality of sub-machines which are interconnected with the host in a point-to-point manner and are to be synchronized, the host and the sub-machines both adopt a CPU + FPGA architecture, and a high-precision synchronization mechanism is realized in the FPGA. According to the synchronization mechanism, synchronization compensation time and synchronization errors are calculated through a plurality of message sending periods, the step length of an interval is adjusted in a self-adaptive mode by comparing the synchronization errors with a reasonable range, and high-precision synchronization of the master machine and the slave machine is carried out. Under the condition that the processor is non-inductive, extremely high synchronization precision is achieved through extremely low network overhead occupation, the complexity and cost of distributed system synchronization design construction are reduced, and the method has high engineering application value.

The application discloses a kind of based on bit-level sparsity software and hardware collaborative acceleration method and FPGA architecture, the method includes: based on bit-level serial arithmetic unit composition target array, based on coarse-grained coding method, operand is converted into the encoding representation for bit-level sparse calculation;Bit-level serial arithmetic unit is designed in cooperation with coarse-grained coding method;Based on lookup table resource characteristics, bit-level serial arithmetic unit is optimized;Based on target array, the product accumulation operation for encoding representation is executed;Based on distributed controller, through micro load balancing communication strategy, data flow and calculation scheduling in target array are managed.Based on coarse-grained coding method and the use of bit-level serial arithmetic unit, while maintaining the accuracy of calculation, information processing density and hardware resource utilization are improved;Based on micro load balancing communication strategy, the uncertainty of calculation time and load imbalance are improved, and then the product accumulation operation efficiency and resource utilization of FPGA platform are improved.

The invention discloses audio equipment operation monitoring equipment and a use method thereof, and the equipment comprises a housing, a monitoring assembly used for monitoring audio equipment, and a supporting assembly used for supporting the housing. The monitoring assembly comprises a signal processing module, a multi-channel signal acquisition module, an analog-to-digital conversion module, a synchronization module, a storage module, a power supply module, an alarm module, a communication module and a touch control chip. The multi-channel signal acquisition module is composed of an acquisition chip, an amplifier and a filter. Through cooperation of the multichannel signal acquisition module, the high-precision ADC chip and the self-adaptive impedance matching circuit, synchronous high-precision acquisition of multichannel audio signals is realized, the accuracy and stability of signal acquisition are improved, the signal processing module adopts a dual-core DSP + FPGA architecture, a real-time Fourier transform engine is built in, and the real-time Fourier transform engine is built in the signal processing module. Complex audio signals can be rapidly processed, the analysis requirement of high real-time performance is met, and the problems that a traditional audio analyzer is complex in operation and single in function are effectively solved.

The invention belongs to the technical field of PGK systems, and particularly relates to a precise guidance assembly control system and method based on ARM + FPGA. A real-time interface unit is constructed through an ARM + FPGA architecture, deep integration of guidance and control functions is achieved from the hardware level, the problem of data transmission delay of a traditional separated design is thoroughly solved, and through dual-core collaborative division of labor (the ARM is responsible for logic decision and task scheduling, and the FPGA is responsible for high-speed data processing and track correction instruction execution), the real-time interface unit is constructed, and the real-time interface unit is constructed. The track correction response time is shortened to a millisecond level, and the real-time performance and the high-speed performance of a control system are effectively guaranteed; meanwhile, communication links and redundant hardware between subsystems are reduced through the integrated architecture, the overall utilization rate and the anti-jamming capability of the system are remarkably improved, the precise guidance requirement of the high-rotation shell in the complex flight environment is met, and the incidental injury risk of civilians caused by insufficient precision of a traditional shell is further reduced.

The invention discloses a high-stability KVM (Keyboard Video Mouse) switcher based on an FPGA (Field Programmable Gate Array) architecture, which relates to the technical field of switchers and comprises a main control module, a display interface module, a signal switching module, an EDID (Extended Display Identifier) processing module, a power management module and a communication control module, according to the main control module, a Xilinx Zynq-7020 FPGA chip is adopted as a control core, functional module programming is achieved through a hardware description language, and IP cores with different functions are supported to be dynamically loaded. The display interface module is connected with the main control module, adopts a TI TPS65987DP controller to realize a full-link native DP1.4a interface, and comprises a dual-channel HBR3 high-speed transmission link and a self-adaptive equalizer; the signal switching module is connected with the display interface module, and adopts an Analog Devices ADG7336 switching chip to realize the switching of a plurality of paths of signals; the EDID processing module is connected with the main control module and adopts a self-developed EDID analysis engine to realize an intelligent EDID self-learning function; and the power management module is connected with the main control module, and 9-36V DC wide voltage input is realized by adopting a TI TPS5430 power chip.

This invention discloses a layout optimization method for FPGA routing based on the maximum independent set, comprising the following steps: S1, defining the detailed layout optimization object in FPGA architecture definition; S2, efficiently parsing the occupancy of valid layout logic units; S3, solving for the maximum independent set in the FPGA netlist; S4, selecting the optimization object to be moved and candidate positions; S5, determining the line length evaluation algorithm; S6, designing the movement cost for routing optimization; S7, globally optimizing the layout using the maximum independent set; S8, directional optimization of the layout; S9, outputting the detailed layout results. The advantages of this invention compared to existing technologies are: the algorithm finds the global maximum independent set to construct the optimization object, finds a suitable target position for the optimization object to move, and avoids getting trapped in local optima for line length optimization. The algorithm proposed in this invention can significantly optimize the overall line length required in the routing stage without disturbing the global validity and timing of the FPGA circuit netlist, and also reduces the congestion density of the global circuit netlist.

One technical solution of the present invention is to provide a layout method for a scalable multi-die network-on-chip (NOC) FPGA architecture. Another technical solution of the present invention is to provide an application of the aforementioned layout method for a scalable multi-die NOC FPGA architecture. The present invention discloses a scalable multi-die NOC-based FPGA architecture and a corresponding hierarchical recursive layout algorithm designed to directly map register transfer-level dataflow designs generated by existing high-level synthesis onto the proposed interconnect architecture. The disclosed method can unlock the potential of hierarchical topologies and more effectively utilize dedicated interconnect resources, such as cross-die wire meshes, NOCs, and high-speed transceivers.

The utility model provides a software rapid development and verification platform under a DSP + FPGA architecture, and belongs to the technical field of embedded computers, the software rapid development and verification platform specifically comprises a DSP daughter card, a substrate, a PC and a cable, the substrate is provided with a power supply module, a DSP daughter card slot, a communication module, a first FPGA and a second FPGA, the DSP daughter card is connected with the DSP daughter card slot, the DSP daughter card slot, the second FPGA, the first FPGA and the PC are sequentially connected through the cable, and the DSP daughter card slot is connected with the communication module. The DSP daughter card slot is further connected with one end of the communication module through a cable, the other end of the communication module is connected with the PC through a cable, and the power module is used for supplying power to the DSP daughter card slot, the first FPGA, the second FPGA and the communication module. Through the processing scheme of the invention, the embedded computer has the capabilities of rapid development, advanced debugging and timely verification of DSP (Digital Signal Processor) software.

The invention provides an FPGA interconnection architecture evaluation device based on a graph neural network, and the device comprises an input unit which is used for obtaining the description information of a target FPGA architecture and the corresponding time sequence report information; the in-block graph construction unit is used for obtaining a corresponding wiring resource graph and global features according to description information conversion; the node frequency label extraction unit is used for counting frequency information of key path nodes according to the time sequence report information; and the prediction unit is used for acquiring the accessibility and the area delay product value of the target FPGA according to the acquired wiring resource map, the global features and the frequency information of the key path nodes. The evaluation device provided in some embodiments of the disclosure can predict the accessibility and the area delay product of the interconnection architecture through the GEF model, and the calling times of a traditional evaluation tool are significantly reduced.

The invention discloses a broadband beam pointing switching method based on an FPGA, and belongs to the technical field of digital phased arrays. The method comprises the steps that the FPGA receives and caches array configuration parameters; time delay filter coefficients and phase shifter coefficients of the array elements are calculated in parallel based on a singing function and a cordic algorithm; quantizing the coefficients, and pre-storing the quantized coefficients in an RAM (Random Access Memory) according to beam pointing; judging beam switching according to an automatic timing or external instruction mode, reading a coefficient corresponding to a target direction, and issuing the coefficient to each processing unit; an FIR filter and a phase shifter are reconfigured, and broadband signal time domain beam forming is achieved through a multi-phase filtering structure; and carrying out gain normalization and truncation correction on the composite signal and then outputting the composite signal. According to the invention, a traditional DSP + FPGA architecture is abandoned, the FPGA independently completes coefficient calculation and beam forming, through pre-storage, assembly line issuing and multi-phase processing, the beam pointing switching speed and the synthesis efficiency are significantly improved, and the method is suitable for broadband beam forming systems with high real-time requirements, such as radar and communication.

The invention discloses an avionic bus multi-protocol module based on software definition, and belongs to the technical field of avionics. The hardware and the drive of the module adopt a common platform design; the hardware is based on an FPGA architecture and comprises an FPGA module, an interface circuit, an auxiliary circuit and a storage space, and an integrated hardware platform is formed. The FPGA module is configured to automatically load the mcs solidification file from the storage space after being powered on, and different avionics bus functions are achieved through software definition; and the driver is a PCIe driver, is used as an interface of logic and application software, supports message communication and access to the storage space, and adopts a uniform data format. Through a software definition mode, a single hardware platform can support multiple avionics bus protocols, the problems that in the prior art, due to deep binding of hardware and protocols, the platform cannot be reused, and testing equipment is complex are solved, and the research and development cost can be effectively saved.

The application discloses a kind of multi-modal pipeline detection data acquisition systems based on FPGA architecture, ultrasonic detection module is used to generate 8 40kHz pulse excitation signal produces ultrasonic wave, and AD9226 analog-digital converter is controlled to collect echo data, and after being internally cached, original sampling data is output through high-speed interface;Image detection module is used to collect the image data output by high-definition image sensor, executes gray scale conversion, filtering, sobel edge detection and morphological operation preprocessing, and outputs the processed image data through fiber interface, and displays on HDMI display after being cached;Two kinds of modal data are accurately time-aligned and uniformly transmitted in the system interior.This application integrates ultrasonic detection and image detection processing, transmission functions in one system, realizes the synchronous acquisition and processing of multi-dimensional information of pipeline inner wall, significantly improves the integration and data consistency of detection system, and is suitable for high-precision, low-delay acquisition and transmission of multi-modal sensing data in industrial pipeline detection equipment.

The invention discloses a multi-channel solid-state power controller based on a DSP + FPGA architecture. The multi-channel solid-state power controller comprises a DSP main control unit, an FPGA control unit, an SSPC channel unit, a power supply unit and a communication interface, the multi-channel power distribution control problem can be well solved; and meanwhile, a capacitive load power distribution function is realized by utilizing a PWM (Pulse Width Modulation) technology, a short-circuit state and a false short-circuit state caused by the capacitive load can be accurately judged, and the reliability of the product is further improved.

The invention discloses an FPGA routing congestion prediction method based on a heterogeneous graph neural network, and the method comprises the steps: obtaining a netlist file in an FPGA design process, extracting the topological information of the file, and constructing a netlist subgraph; fPGA architecture information is obtained, and an architecture subgraph is constructed according to the architecture information; obtaining a layout file in the FPGA design process, extracting position information of each block in the file to construct a spatial mapping edge, and projecting nodes in the netlist sub-graph to the architecture sub-graph through the spatial mapping edge to obtain an integrated heterogeneous graph; constructing a heterogeneous graph neural network matched with the heterogeneous graph, wherein the heterogeneous graph neural network comprises a feature initialization module, a message passing module and a reading module; a data set is constructed according to the heterogeneous graph to train a heterogeneous graph neural network, and a neural network structure search strategy is used to optimize a message passing module; and inputting the heterogeneous graph into the heterogeneous graph neural network to obtain routing congestion information. According to the method, the accuracy of the FPGA routing congestion prediction result can be improved, the generalization ability is higher, and the time for reasoning, training and data preprocessing is shortened.

The invention discloses a spaceborne interference SAR echo simulator and an echo simulation method, and relates to the technical field of spaceborne interference SAR. The simulator comprises a radio frequency transceiver module, an intermediate frequency modulation module, an echo calculation module and a main control device. The radio frequency transceiver module realizes bidirectional frequency conversion and clock distribution of radio frequency and intermediate frequency signals; the intermediate frequency modulation module completes conversion and synchronous control of intermediate frequency and baseband signals; the echo calculation module adopts a CPU + GPU + FPGA architecture to efficiently generate scene echo data; the main control equipment realizes test case configuration, module control and state monitoring; the simulation method comprises the steps of constructing a space geometric model to calculate a phase difference, establishing a point target echo model, generating scene echo data, and performing intermediate frequency modulation and radio frequency conversion to form a signal closed loop. According to the invention, full-link closed-loop simulation is realized, the echo simulation precision and real-time performance are improved, multi-scene dynamic configuration is supported, and efficient test support is provided for satellite-borne InSAR load research and development.

This invention provides an automated optimization method for efficient deployment of neural networks on FPGAs, relating to the fields of deep learning and hardware acceleration technology. The method includes: receiving the original neural network model and hardware constraint information; parsing to obtain quantization operators; generating a candidate precision configuration combination set through two-level filtering; constructing a graph-structured perceptron based on the target FPGA architecture to predict hardware resource consumption under each configuration; constructing a differential objective function that integrates task loss and weighted quantization error; solving for the initial mixed precision configuration using an adaptive penalized augmented Lagrangian method under hardware constraints; progressively expanding the neighborhood and replacing configurations through hierarchical neighborhood search to obtain the final configuration; generating hardware description code for both fixed-point and floating-point formats and calling the backend toolchain to output bitstream files. This invention achieves automated precision configuration while satisfying FPGA resource and timing constraints, significantly improving inference energy efficiency and deployment efficiency.

The invention discloses a dual-redundancy communication chip and an interaction method thereof. Wherein the dual-redundancy communication chip comprises an ARM (Advanced RISC Machines) processor, a field programmable gate array (FPGA) processor, a dual-redundancy Ethernet bare core, a dual-redundancy controller area network bus (CAN) transceiver bare core and an information transmission bus transceiver bare core; and the FPGA processor is configured to communicate with the ARM processor through an AXI bus, obtain a first upper computer instruction issued by an upper computer through the ARM processor, and configure the first interface and the second interface through the first upper computer instruction so as to realize parallel data interaction between the first interface and the second interface. In the embodiment of the invention, an ARM + FPGA architecture is adopted to replace a traditional mode of taking a computer mainboard as a center, the redundant interfaces directly finish data forwarding in the SoC without being transferred through an external bus or the mainboard, and a'center transfer 'link of the traditional architecture is skipped, so that parallel data interaction between the redundant interfaces is realized.

The application discloses a memory-compute FPGA architecture. Memory-compute cores, memory blocks and logic function blocks used for replacing part of the logic function blocks are arranged in a row-column array and arranged in an island type architecture. In the memory-compute cores, there are SRAMs arranged in a row-column array, the SRAMs store one-bit data, the output ends of an address decoding circuit are connected with each row of the SRAM array, the output ends of a write control circuit are connected with each column of the SRAM array, each eight columns of the SRAM array and an input register are connected with an 8-bit input port of an addition tree through a multiplexer and eight NOR gates, and the output port of the addition tree is connected with an output register through a shift and addition module and a quantization module in sequence. The application realizes in-memory computation on the FPGA, utilizes the parallelism and reconfigurability of the FPGA to support mapping of various networks, and utilizes in-memory computation technology to reduce data movement and further reduce computation power consumption.

The invention discloses a PCIE (Peripheral Component Interface Express)-to-EMMC (Embedded Multi Media Card) bridging method based on a Feiteng D2000 + FPGA (Field Programmable Gate Array) architecture. The method comprises a bridging connection step: connecting a Feiteng processor D2000 and an FPGA, and connecting the FPGA and an EMMC storage chip; the bridging operation step comprises the following steps of: 1, electrifying a Feiteng processor D2000, an FPGA (Field Programmable Gate Array) and an EMMC (Embedded Multi Media Card) storage chip; step 2, after the FPGA is loaded, keeping resetting the Feiteng processor D2000; step 3, resetting the EMMC storage chip by using an FPGA (Field Programmable Gate Array), and initializing the EMMC storage chip; 4, judging whether initialization of the EMMC storage chip is successful or not; if not, the FPGA is used for resetting and initializing the EMMC storage chip again; if the mapping is successful, the FPGA maps the address space of the EMMC storage chip to the function register space of the PCIE IP core through the AXI bus; step 5, the FPGA releases the reset of the Feiteng processor D2000; 6, after the Feiteng processor D2000 loads the program, PCIE enumeration operation is carried out, and address space is distributed to the FPGA end equipment.