76 results about "Fpga architecture" patented technology

The invention belongs to the technical field of parallel robot controllers, and discloses a high-performance parallel robot controller based on an arm + fpga architecture, through deep heterogeneous fusion of an ARM and an FPGA, the control period is shortened to be within 10 microseconds, the trajectory tracking error is controlled to be 0.1 mm or below, and the performance bottleneck of a traditional architecture in a high-speed scene is solved; the multi-core ARM undertakes complex tasks such as global trajectory planning and dynamics solution, and realizes parallel processing by means of an NEON instruction set; the FPGA fully releases the hardware parallel characteristic of the FPGA, real-time tasks such as multi-axis motion control and sensor data fusion are synchronously completed through a distributed logic unit, and a complex decision-real-time execution assembly line cooperation mode is formed. Inertial parameters and load changes of the mechanical arm are estimated in real time through an LSTM neural network, and feedforward compensation is carried out on interference such as mechanical vibration and load abrupt change in combination with an extended state observer achieved through FPGA hardware; the innovatively designed double closed-loop control architecture supports seamless switching between a force control mode and a position control mode.

The invention relates to the technical field of FPGA architecture, in particular to an SM4 hardware acceleration and anti-side-channel protection method and system of a domestic FPGA, which comprises the following steps of: performing data type identification operation on bright-ciphertext batch data by utilizing an acceleration block to obtain a data type, and according to a pre-constructed parallelization strategy and the data type, performing data type identification operation on the SM4 hardware acceleration and anti-side-channel protection on the SM4 hardware acceleration and anti-side-channel protection on the SM4 hardware acceleration and anti-side-channel protection system; performing dynamic resource configuration on the plaintext-ciphertext batch data to obtain resource configuration information, and performing configuration according to the resource configuration information, the key-mode parameter and the dynamic control instruction to obtain a configured SM4 algorithm; according to the configured SM4 algorithm, performing encryption processing on the plaintext-ciphertext batch data to obtain to-be-protected encrypted data; and performing protection operation based on physical layer leakage suppression, logic layer confusion association and system layer dynamic response on key-mode parameters, dynamic control instructions, plaintext-ciphertext batch data and encryption processing by using the protection block, and converting to-be-protected encrypted data into protected encrypted data. According to the invention, the encryption processing performance and security can be improved.

The invention provides a complex operation lightweight architecture and method based on an FPGA, the architecture comprises a main scheduling module, a calculation module and a floating point operator module, the calculation module comprises a storage unit and a calculation unit, the storage unit obtains and caches input data of a target algorithm, and the main scheduling module carries out the calculation of the target algorithm according to the operation sequence of the target algorithm. The target algorithm is divided into a plurality of calculation steps, and corresponding operation enable signals are generated and transmitted to the calculation unit; the calculation unit obtains target parameters required by calculation steps from the storage unit according to the operation enable signal, obtains floating point operator units required by the calculation steps from the floating point operator module, and executes the calculation steps to determine an operation intermediate result; and storing the operation intermediate result in a storage unit, generating an operation completion signal and transmitting the operation completion signal to a main scheduling module to control the next calculation step until a final operation result is obtained. Therefore, the FPGA architecture with low power consumption and miniaturization is realized.

The invention provides a full-link detection and trusted industrial control method and system based on a domestic chip, and relates to the technical field of industrial automation and information security. The system comprises a security calculation module which is constructed by integrating a TPM (Trusted Platform Module) in a domestic chip; the special hardware encryption acceleration module is designed based on an ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array) architecture and is integrated in a domestic chip; the trusted execution environment module is constructed based on a security isolation technology; the anomaly detection module is constructed based on a pulse neural network; the block chain auditing module is constructed based on a block chain framework; the dynamic security policy engine is used to automatically trigger a security response policy. The invention constructs an integrated industrial safety control system based on a domestic chip, and the system is especially suitable for intelligent manufacturing and high-safety-level industrial scenes. The problems that in the prior art, full-link safe starting cannot be achieved in a localized chip environment, an efficient encryption and trusted execution environment is lacked, and the real-time anomaly detection and log auditing capacity is insufficient are solved.

The invention provides a photovoltaic power station battery monitoring method and system. The photovoltaic power station battery monitoring system comprises a data acquisition layer which comprises an electrical parameter sensor, an environment sensor, an infrared camera and an unmanned aerial vehicle inspection module; the edge calculation layer adopts an ARM + FPGA architecture to realize data preprocessing and fault preliminary screening; the cloud platform layer is used for deploying a CNN + LSTM model and providing a health assessment, early warning and visual interface, and relates to the technical field of photovoltaic power generation, electrical parameters, environmental parameters and image data are synchronously acquired, wavelet transform and an environmental normalization algorithm are used for preprocessing, and high-precision identification of faults such as hot spots and hidden cracks is realized in combination with a CNN + LSTM fusion model; and the battery state is quantitatively evaluated through a health index (HI) model. The system adopts an edge computing and cloud platform architecture, supports real-time early warning and life prediction, solves the hysteresis and unicity defects of a traditional monitoring scheme, and is suitable for intelligent operation and maintenance of a large-scale photovoltaic power station.

The invention discloses a space-time image texture angle detection and discrimination method and system, and belongs to the field of visual flow measurement instruments. According to the design, a Zynq series processor with an ARM + FPGA architecture is used as a core, and a system module comprises a PS host control end, a PL end texture enhancement module, a two-dimensional Fourier transform module, a frequency spectrum logarithm transform module, a Gaussian filter module and an image segmentation and texture angle detection and judgment module. Wherein the texture enhancement module inhibits noise interference and enhances the continuity of effective textures; the two-dimensional Fourier transform module converts the information of the spatial domain image to a frequency domain; the frequency spectrum logarithmic transformation module is used for carrying out logarithmic magnitude spectrum calculation on the transformed spectrogram so as to improve the visibility of a low-amplitude component; and the image segmentation and texture angle detection and discrimination module carries out angle detection and discrimination after effective and invalid signals are separated, and finally outputs an angle detection result. The method can be applied to a river surface flow velocity measurement system based on a space-time image velocity measurement method, and the adaptability and efficiency of flow measurement in complex scenes can be improved.

The invention discloses a satellite integrated electronic system. According to the system, a heterogeneous FPGA architecture is adopted, a satellite service management module is deployed on a first FPGA chip, and a measurement and control module and an encryption and decryption module are integrated on a second FPGA chip. The system realizes fault isolation through the design of an independent power domain and a reset domain of the measurement and control and encryption and decryption module, ensures that a measurement and control link is not interrupted through a hardware bypass channel in the second FPGA chip, and improves the reliability of the system. The encryption and decryption module adopts an encryption mode mapping graph and management system, supports a dynamic key management mechanism triggered based on three events of periodic switching, mapping graph updating and periodic parameter updating, can flexibly configure an encryption strategy according to an on-orbit task demand, and improves the security and adaptability of the system. The problems that in the prior art, chip performance and cost are difficult to balance, the integration level is low, and a whole machine fails due to a single-point fault are effectively solved, and the method is particularly suitable for a microsatellite platform with strict requirements for cost, size and reliability.

This invention discloses a comprehensive identification test device and method based on software-defined radio technology, belonging to the field of avionics equipment testing. The device includes: a core processing and control unit, employing a multi-channel high-speed AD / DA and MPSoC FPGA architecture, supporting concurrent operation of various conventional aircraft identification functions through multiple internally integrated models; a radio frequency transceiver module, connected to the core processing and control unit, used for digital frequency conversion and analog-to-digital conversion of signals; a high-power radio frequency front-end component, internally equipped with multi-stage attenuation circuits and isolation devices, used for physical isolation and filtering attenuation of transmitted and received signals, ensuring its power covers the dynamic range of airborne received signals; and a remote control interface for receiving remote control commands to achieve automated test linkage. This invention allows direct connection to test the receiving performance of airborne equipment without the need for external high-power accessories, achieving a high degree of integration and automation of the test equipment, significantly improving detection and troubleshooting efficiency.

The invention discloses an FPGA (Field Programmable Gate Array) configuration architecture and an application method thereof. The architecture comprises FILO modules, a local shared configuration memory area and a distributed parameter storage area established between adjacent FILO module clusters, wherein the distributed parameter storage area is specially used for caching key configuration data of a current task execution period; a configuration memory area is shared globally, a high-bandwidth configuration memory is integrated on the top layer of the FPGA architecture, and all reconfigurable parameter sets of the full task process are stored persistently. And adding a temporary stack pointer and setting a corresponding pointing area. The application method comprises the steps of global configuration preloading, local dynamic loading and FILO module execution. According to the method, the performance, the energy efficiency and the resource utilization rate of the FPGA in a lightweight and dynamic application scene are greatly improved. The method can be widely applied to the field of programmable logic device system structures.

A high-speed file system based on ZYNQ comprises a storage board and a DSP data processing board, the storage board comprises a ZYNQ chip of an ARM + FPGA architecture and an SRIO switch, the DSP data processing board comprises a plurality of 8-core DSP chips, the DSP chips communicate with the ZYNQ chip through the SRIO switch, and the ZYNQ chip communicates with the DSP data processing board through the SRIO switch. A DDR space of an ARM side of a ZYNQ chip is divided into a message receiving address, a data receiving address, a message sending address and a data sending address, each type of address is divided into a plurality of areas, and each area is provided for a DSP chip to use. Based on protocols of two data types of messages and data, multiple cores of multiple DSPs in the system can operate files, folders and disks at the same time, the DSP scale supported by the storage system can be greatly improved on the premise that the number of storage board cards is not increased, a basically complete file system at the DSP end is achieved, and the storage efficiency is improved. And the stored data can be exported through the network port of the DSP end, so that the network port specially used for exporting the data is saved.

The invention provides an autonomous and controllable real-time simulation platform based on CPU and FPGA architecture development, and relates to the technical field of real-time simulation, the platform executes operation of an operating system and a complex model through a CPU, the FPGA completes nanosecond I / O refresh and high-speed calculation in parallel, the two are cooperated through a PCIe bus, and the real-time simulation platform is developed through the FPGA. Hard real-time calculation of the fuel cell model of electric-thermal-fluid multi-physics field coupling is realized; and the digital quantity output by the model is instantly converted into real voltage, temperature, pressure and flow through the FPGA and is reinjected into the tested FCCU, so that the controller completes closed-loop control, fault diagnosis and limit working condition verification under the condition of no physical pile.

The invention relates to the technical field of standby power supply automatic switching, and provides an intelligent standby power supply automatic switching device suitable for multiple incoming lines of a distribution network and a control method thereof.The intelligent standby power supply automatic switching device comprises a digital processing module, an optical communication interface, a multi-incoming-line adaptive logic module, an intelligent standby power supply switching function module and a constant value and wave recording module; the optical communication interface transmits acquired switch position signals and maintenance pressing plate state signals to the digital processing module through optical fibers. The digital processing module adopts a multi-core CPU + FPGA architecture and is integrated with a time-frequency synchronization module, automatically generates spare power switching logic and transmits the spare power switching logic to the intelligent spare power switching function module; the intelligent spare power switching function module comprises a plurality of spare power switching modes. The method has the advantages that multiple incoming lines and complex topology are supported, N supply-N standby and other scenes of the distribution network are met, each power supply can be set on different buses according to a fixed value and can be set as an incoming line or outgoing line attribute, expansibility is high, and different requirements of current and long-term power supply attributes are met.

The invention relates to a chip verification method and system based on a double-FPGA architecture, and the method comprises the steps: deploying a verification platform on a first programmable logic device in a hardware circuit form, deploying a tested design on a second programmable logic device, and enabling the verification platform and the second programmable logic device to be interconnected through a hardware interface; the first programmable logic device comprises a control module, an excitation generation module, an expectation calculation module, an evaluation module, an excitation output module and a response input module; in response to external triggering, the control module jumps from idle to start, controls the excitation generation module to generate excitation, and transmits the excitation to the tested design through the excitation output module; the tested design generates a response signal based on excitation and transmits the response signal to the evaluation module through the response input module; the expectation calculation module receives an excitation calculation expectation result and transmits the result to the evaluation module; and the evaluation module compares the response with the expected result to generate a verification result. The method gets rid of software simulation dependence, shortens verification starting time, is close to a real chip use environment, and improves function verification reliability.

The invention discloses a novel VPSA method biogas decarbonization purification equipment intelligent control joint control system, belongs to the industrial automation and artificial intelligence fusion field, and comprises a global perception and data acquisition layer, an edge intelligent decision and control layer, an accurate execution and linkage control layer, and a cloud edge collaborative management and digital twinborn layer four-layer architecture. The global sensing layer is provided with a 48-node sensor network and a 10kHz acquisition card to complete data acquisition preprocessing; the edge decision-making layer carries a reinforcement learning algorithm and an LSTM-CNN model through an ARM + FPGA architecture; the precise execution layer realizes millisecond-level response through a high-speed execution mechanism and a Petri net linkage matrix; and the cloud side management layer realizes remote management and virtual debugging by relying on a cloud platform and a digital twin system, solves the problems of rigid control, weak fault early warning and the like of traditional equipment, and is suitable for the fields of biomass energy utilization and environmental protection engineering.

The invention discloses a design method of a subminiature high-sampling-rate one-driving-eight fast reflecting mirror controller, and relates to the technical field of photoelectric device measurement. The controller controls eight groups of fast reflecting mirrors; sCI serial communication is realized between the main control computer and the controller; the controller adopts a DSP + FPGA architecture mode, and an FPGA chip transmits internal data to a DSP chip through SRIO; the DSP chip is used for external communication and implementation of a fast reflector closed-loop algorithm; the FPGA chip is used for realizing AD acquisition, DA driving and a digital current loop algorithm; input signals of the fast reflectors are transmitted to the digital current loop module after being processed by a closed-loop algorithm, the FPGA chip calls the DAC module to process the output of the digital current loop, and the output power is adjusted by the power amplifier module so as to control the eight groups of fast reflectors in real time; and the FPGA chip calls the ADC module to collect feedback voltage of the fast reflectors in real time and feed the feedback voltage back to the FPGA chip, and the feedback voltage is processed by a closed-loop algorithm and a digital current loop algorithm to realize synchronous and real-time closed-loop control of the eight groups of fast reflectors.

The disclosure provides an evaluation device of a FPGA interconnection architecture based on a graph neural network, which comprises: an input unit configured to obtain description information of a target FPGA architecture and corresponding timing report information; an intra-block graph construction unit configured to obtain corresponding wiring resource graphs and global features according to the description information conversion; a node frequency label extraction unit configured to obtain frequency information of critical path node occurrence according to the timing report information; and a prediction unit configured to obtain the routability and area delay product value of the target FPGA according to the obtained wiring resource graphs and global features and the frequency information of critical path node occurrence. The evaluation device provided in some embodiments of the disclosure can predict the routability and area delay product of the interconnection architecture through the GEF model, and significantly reduce the number of calls of the traditional evaluation tool.

The invention discloses an FPGA (Field Programmable Gate Array) wiring optimized layout method based on a maximum independent set. The method comprises the following steps: S1, defining a detailed layout optimization object by an FPGA architecture; s2, efficiently analyzing an occupation condition of a legalized layout logic unit; s3, solving the maximum independent set of the FPGA netlist; s4, selecting a moving optimization object and a candidate position; s5, determining a line length evaluation algorithm; s6, designing a moving cost oriented to wiring optimization; s7, using the maximum independent set to globally optimize the layout; s8, directionally optimizing the layout; and S9, outputting a detailed layout result. Compared with the prior art, the algorithm has the advantages that the algorithm searches a global maximum independent set to construct an optimization object, a proper moving target position is searched for the optimization object, falling into a local optimal solution of line length optimization is avoided, and on the premise that the global legality and the time sequence of an FPGA circuit netlist are not disturbed, the algorithm can improve the optimization efficiency of the FPGA circuit netlist. The overall wire length required in the wiring stage is obviously optimized, and the congestion density of a global circuit netlist is reduced.

The invention discloses a high-precision synchronization method and system for a distributed power system, the method comprises a host and a plurality of sub-machines which are interconnected with the host in a point-to-point manner and are to be synchronized, the host and the sub-machines both adopt a CPU + FPGA architecture, and a high-precision synchronization mechanism is realized in the FPGA. According to the synchronization mechanism, synchronization compensation time and synchronization errors are calculated through a plurality of message sending periods, the step length of an interval is adjusted in a self-adaptive mode by comparing the synchronization errors with a reasonable range, and high-precision synchronization of the master machine and the slave machine is carried out. Under the condition that the processor is non-inductive, extremely high synchronization precision is achieved through extremely low network overhead occupation, the complexity and cost of distributed system synchronization design construction are reduced, and the method has high engineering application value.

The application discloses a kind of based on bit-level sparsity software and hardware collaborative acceleration method and FPGA architecture, the method includes: based on bit-level serial arithmetic unit composition target array, based on coarse-grained coding method, operand is converted into the encoding representation for bit-level sparse calculation;Bit-level serial arithmetic unit is designed in cooperation with coarse-grained coding method;Based on lookup table resource characteristics, bit-level serial arithmetic unit is optimized;Based on target array, the product accumulation operation for encoding representation is executed;Based on distributed controller, through micro load balancing communication strategy, data flow and calculation scheduling in target array are managed.Based on coarse-grained coding method and the use of bit-level serial arithmetic unit, while maintaining the accuracy of calculation, information processing density and hardware resource utilization are improved;Based on micro load balancing communication strategy, the uncertainty of calculation time and load imbalance are improved, and then the product accumulation operation efficiency and resource utilization of FPGA platform are improved.

The invention discloses audio equipment operation monitoring equipment and a use method thereof, and the equipment comprises a housing, a monitoring assembly used for monitoring audio equipment, and a supporting assembly used for supporting the housing. The monitoring assembly comprises a signal processing module, a multi-channel signal acquisition module, an analog-to-digital conversion module, a synchronization module, a storage module, a power supply module, an alarm module, a communication module and a touch control chip. The multi-channel signal acquisition module is composed of an acquisition chip, an amplifier and a filter. Through cooperation of the multichannel signal acquisition module, the high-precision ADC chip and the self-adaptive impedance matching circuit, synchronous high-precision acquisition of multichannel audio signals is realized, the accuracy and stability of signal acquisition are improved, the signal processing module adopts a dual-core DSP + FPGA architecture, a real-time Fourier transform engine is built in, and the real-time Fourier transform engine is built in the signal processing module. Complex audio signals can be rapidly processed, the analysis requirement of high real-time performance is met, and the problems that a traditional audio analyzer is complex in operation and single in function are effectively solved.

The invention belongs to the technical field of PGK systems, and particularly relates to a precise guidance assembly control system and method based on ARM + FPGA. A real-time interface unit is constructed through an ARM + FPGA architecture, deep integration of guidance and control functions is achieved from the hardware level, the problem of data transmission delay of a traditional separated design is thoroughly solved, and through dual-core collaborative division of labor (the ARM is responsible for logic decision and task scheduling, and the FPGA is responsible for high-speed data processing and track correction instruction execution), the real-time interface unit is constructed, and the real-time interface unit is constructed. The track correction response time is shortened to a millisecond level, and the real-time performance and the high-speed performance of a control system are effectively guaranteed; meanwhile, communication links and redundant hardware between subsystems are reduced through the integrated architecture, the overall utilization rate and the anti-jamming capability of the system are remarkably improved, the precise guidance requirement of the high-rotation shell in the complex flight environment is met, and the incidental injury risk of civilians caused by insufficient precision of a traditional shell is further reduced.

This disclosure relates generally to a method and a system for computing using a field programmable gate array (FPGA) neuromorphic architecture. Implementing energy efficient Artificial Intelligence (AI) applications at power constrained environment / devices is challenging due to huge energy consumption during both training and inferencing. The disclosure is a FPGA architecture based neuromorphic computing platform, the basic components include a plurality of neurons and memory. The FPGA neuromorphic architecture is parameterized, parallel and modular, thus enabling improved energy / inference and Latency-Throughput. Based on values of the plurality of features of the data set, the FPGA neuromorphic architecture is generated in a modular and parallel fashion. The output of the disclosed FPGA neuromorphic architecture is the plurality of output spikes from the neuron, which becomes the basis of inference for computing.

The invention discloses a high-stability KVM (Keyboard Video Mouse) switcher based on an FPGA (Field Programmable Gate Array) architecture, which relates to the technical field of switchers and comprises a main control module, a display interface module, a signal switching module, an EDID (Extended Display Identifier) processing module, a power management module and a communication control module, according to the main control module, a Xilinx Zynq-7020 FPGA chip is adopted as a control core, functional module programming is achieved through a hardware description language, and IP cores with different functions are supported to be dynamically loaded. The display interface module is connected with the main control module, adopts a TI TPS65987DP controller to realize a full-link native DP1.4a interface, and comprises a dual-channel HBR3 high-speed transmission link and a self-adaptive equalizer; the signal switching module is connected with the display interface module, and adopts an Analog Devices ADG7336 switching chip to realize the switching of a plurality of paths of signals; the EDID processing module is connected with the main control module and adopts a self-developed EDID analysis engine to realize an intelligent EDID self-learning function; and the power management module is connected with the main control module, and 9-36V DC wide voltage input is realized by adopting a TI TPS5430 power chip.

This invention discloses a layout optimization method for FPGA routing based on the maximum independent set, comprising the following steps: S1, defining the detailed layout optimization object in FPGA architecture definition; S2, efficiently parsing the occupancy of valid layout logic units; S3, solving for the maximum independent set in the FPGA netlist; S4, selecting the optimization object to be moved and candidate positions; S5, determining the line length evaluation algorithm; S6, designing the movement cost for routing optimization; S7, globally optimizing the layout using the maximum independent set; S8, directional optimization of the layout; S9, outputting the detailed layout results. The advantages of this invention compared to existing technologies are: the algorithm finds the global maximum independent set to construct the optimization object, finds a suitable target position for the optimization object to move, and avoids getting trapped in local optima for line length optimization. The algorithm proposed in this invention can significantly optimize the overall line length required in the routing stage without disturbing the global validity and timing of the FPGA circuit netlist, and also reduces the congestion density of the global circuit netlist.

One technical solution of the present invention is to provide a layout method for a scalable multi-die network-on-chip (NOC) FPGA architecture. Another technical solution of the present invention is to provide an application of the aforementioned layout method for a scalable multi-die NOC FPGA architecture. The present invention discloses a scalable multi-die NOC-based FPGA architecture and a corresponding hierarchical recursive layout algorithm designed to directly map register transfer-level dataflow designs generated by existing high-level synthesis onto the proposed interconnect architecture. The disclosed method can unlock the potential of hierarchical topologies and more effectively utilize dedicated interconnect resources, such as cross-die wire meshes, NOCs, and high-speed transceivers.

The present invention discloses a window-based dynamic erase scheduling method. The present invention proposes a novel window-based dynamic erase scheduling algorithm. By dynamically scheduling user tasks and erase tasks, the algorithm disclosed by the present invention can reduce the erase conflicts of the FPGA erase module and erase each user task as much as possible in a timely manner. Compared with the current method, the method proposed by the present invention greatly reduces the area and energy consumption of the hardware circuit and improves the reliability of the system. The present invention proposes an erase scheduling algorithm based on negotiation drive and ILP-based optimization drive. By utilizing global conflict information, the algorithm of the present invention can erase more user tasks and improve system reliability. The present invention ensures the reliability of a mixed critical task set system. The present invention proposes a multi-ICAP port allocation algorithm based on DVFS, which can explore the impact of FPGA architecture support on system reliability to further optimize system reliability.

The invention provides a carrier synchronization control method of a motor controller of a distributed FPGA architecture, the motor controller comprises a main control unit and three sub-control units, and the FPGA of each sub-control unit cyclically executes the following operations: receiving communication data sent by the main control unit and extracting control information to be verified and synchronization information to be verified from the communication data; judging whether the synchronization information to be verified is valid or not, and determining an updating mode of the carrier generation moment, the current synchronization information and the current control information according to a judgment result; and from the updated carrier generation moment, generating a carrier and a PWM control signal of a corresponding phase of the sub-control unit based on the current control information and the carrier clock period of the FPGA of the sub-control unit. According to the control method provided by the invention, the carrier synchronization problem of each phase of the distributed motor controller under the control of the high-frequency switch can be effectively solved.

The utility model provides a software rapid development and verification platform under a DSP + FPGA architecture, and belongs to the technical field of embedded computers, the software rapid development and verification platform specifically comprises a DSP daughter card, a substrate, a PC and a cable, the substrate is provided with a power supply module, a DSP daughter card slot, a communication module, a first FPGA and a second FPGA, the DSP daughter card is connected with the DSP daughter card slot, the DSP daughter card slot, the second FPGA, the first FPGA and the PC are sequentially connected through the cable, and the DSP daughter card slot is connected with the communication module. The DSP daughter card slot is further connected with one end of the communication module through a cable, the other end of the communication module is connected with the PC through a cable, and the power module is used for supplying power to the DSP daughter card slot, the first FPGA, the second FPGA and the communication module. Through the processing scheme of the invention, the embedded computer has the capabilities of rapid development, advanced debugging and timely verification of DSP (Digital Signal Processor) software.

The present invention relates to a modular data encryption and decryption system and method, belonging to the field of computer cryptography. The modular encryption and decryption architecture of the present invention runs on a system-on-chip processor and an FPGA respectively. Through the decoupled design and collaborative work of the management software and the microprocessor module software on the system-on-chip, the decoupling of cryptographic processing from the underlying hardware is achieved, and the problems of repeated design and repeated replacement of cryptographic application modules are solved; the FPGA architecture adopts the method of embedding multiple algorithm modules, and the microprocessor module corresponds to the FPGA algorithm module one by one, solving the problem that one cryptographic application module can run on multiple hardware platforms and one hardware platform can run multiple cryptographic application modules. The management software communicates with the microprocessor module by adopting the internal standard socket method of the system and communicates with the FPGA by adopting the bus method, realizing the standardization and platformization of different microprocessor modules and different cryptographic modules, and completing functions such as the scheduling of cryptographic microprocessor modules and the unified management of cryptographic resources.

The invention provides an FPGA interconnection architecture evaluation device based on a graph neural network, and the device comprises an input unit which is used for obtaining the description information of a target FPGA architecture and the corresponding time sequence report information; the in-block graph construction unit is used for obtaining a corresponding wiring resource graph and global features according to description information conversion; the node frequency label extraction unit is used for counting frequency information of key path nodes according to the time sequence report information; and the prediction unit is used for acquiring the accessibility and the area delay product value of the target FPGA according to the acquired wiring resource map, the global features and the frequency information of the key path nodes. The evaluation device provided in some embodiments of the disclosure can predict the accessibility and the area delay product of the interconnection architecture through the GEF model, and the calling times of a traditional evaluation tool are significantly reduced.