Fine-grain dynamically reconfigurable FPGA architecture

一种门阵列、存储器的技术，应用在逻辑电路、脉冲技术、降低功耗等方向，能够解决未取得ASIC、类似面积等问题

Inactive Publication Date: 2016-02-17
PRINCETON UNIV TRUSTEESHIPS
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Problems solved by technology

However, the price for design flexibility is that current FPGAs do not achieve ASIC-like area, power, or performance

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  • Fine-grain dynamically reconfigurable FPGA architecture
  • Fine-grain dynamically reconfigurable FPGA architecture
  • Fine-grain dynamically reconfigurable FPGA architecture

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Embodiment Construction

[0028] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0029] This paper discloses a hybrid CMOS nanotechnology reconfigurable architecture, called NATURE, which can solve some existing FPGA problems: logic density and run-time reconfiguration efficiency. The architecture utilizes the concept of sequential logic folding, which divides the circuit into multiple cascaded stages, and utilizes the same logic element (LE, logicmement) to implement each stage through very fast dynamic reconfiguration. Since logic folding greatly limits on-chip communication, the number of global interconnects can be greatly reduced by deep logic folding, i.e., when reconfiguration occurs after only one or two look-uptable (LUT) levels in the circuit , because most local or short-distance interconnects are required. Due to its reliance on traditional siled architectures, NATURE was unable to take full advantage of this phenomenon. In order to...

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Abstract

A field programmable gate array (FPGA) and method of reconfiguring a FPGA are disclosed. The FPGA includes a plurality of logic elements interconnected with reconfigurable switches and at least horizontal and vertical direct links. A memory is coupled to the reconfigurable switches, the memory being configured to store at least two run time configurations. The reconfigurable switches are reconfigurable based on a selected run time configuration stored in the memory. The memory may be a nanoelectronic random access memory (RAM). The memory may be configured to store the at least two run time configurations for at least four logic elements. Each logic element may include a look-up-table (LUT), a flip-flop, inputs and outputs. Each logic element may include dedicated carry logic. At least four logic elements may be interconnected with diagonal direct links.

Description

technical field [0001] The present invention mainly relates to a field-programmable gate array (FPGA, field-programmable gate array), and more particularly relates to a fine-grained dynamic reconfigurable FPGA. Background technique [0002] As complementary metal-oxide-semiconductor (CMOS, complementary metal-oxide-semiconductor) technology is pushed to its physical limit, the design and manufacturing costs of application-specific integrated circuits (ASIC, application-specific integrated circuits) become high. Compared with ASICs, FPGAs offer a shorter time-to-market and lower design costs, making FPGAs more and more attractive. However, the price for design flexibility is that current FPGAs do not achieve ASIC-like area, power, or performance. This is mainly due to the large overhead introduced to achieve reconfigurability. It is estimated that FPGAs can yield 21 times the silicon area, more than 3 times the latency, and more than 10 times the dynamic power consumption c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/173
CPCH03K19/1776H03K19/0008H03K19/17728H03K19/17736H03K19/17752
Inventor 林廷钧张玮尼拉·K·杰哈
Owner PRINCETON UNIV TRUSTEESHIPS
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