12results about "Radiation hardening" patented technology

It is provided an improved integrated circuit (10) is provided for driving fast links in radiation-hard applications comprising a PISO device (1) including a transmitting block (2) defining a first basic logic and configured to transmit first data in parallel (1p) correlated to a first low frequency clock signal (1l), a PLL (3) configured to receive a first reference clock signal (1r) and to generate at least a first high frequency clock signal (1a) and in including at least a first FD (30) configured to generate at least a first control clock signal (1c), a Serializer (4) operatively connected to the PLL (3) and the transmitting block (2) and configured to receive at least the first data in parallel (1p) and the first high frequency clock signal (1a) and reorganize the first data in parallel (1p) on the basis of a first load signal (4c) in first serial data (1s) related in frequency to the first high clock signal frequency (1a), in which the first PD (30) is operatively connected to the transmitting block (2), the first low frequency clock signal (1l) coincides with the first control clock signal (1c) and the transmitting block (2) transmits the first low frequency clock signal (1l) to the Serializer (4) so as to determine the first load signal (4c) in proportion to the first low frequency clock signal (1l); and a SIPO device (5) including a receiving block (6) defining a second basic logic and configured to receive second data (5p) correlated to a second low frequency clock signal (5l), CDR apparatus (7) configured to receive second serial data (5s), to generate at least a second high frequency clock signal (5a) and in including at least a second FD (70) configured to generate at least a second control clock signal (5c), a Deserializer (8) operatively connected to the CDR apparatus (7) and to the receiving block (6) and configured to receive at least the second serial data (5s) and the second high frequency clock signal (5a) and reorganize the second data (5s) on the basis of a second load signal (8c) in the second parallel data (5p) correlated in frequency to the second high frequency clock signal (5a), wherein the second PD (70) is operationally connected to the receiving block (6), the second low frequency clock signal frequency (5l) coincides with the second control clock signal (5c) and the receiving block (6) transmits the second low frequency clock signal (5l) to the Deserializer (8) in order to determine the second load signal (8c) proportionally to the second low frequency clock signal (5l); and wherein the Serializer (4) is operatively connected to the Deserializer (8) and to the CDR apparatus (7), the first serial data (1s) coincide with the second serial data (5s), the first parallel data (1p) they are equivalent to the second parallel data (5p), the first high frequency signals (1a) are equivalent to the second high frequency signals (5a) and the first low frequency signals (1l) are equivalent to the second low frequency signals (5l).

The disclosure provides a circuit (700) and method for correcting single event upsets, SEUs, or glitches in electronic circuits. The circuit includes rising and falling edge detection sub-circuits (710, 712) connected to a sequential circuit element output (706) which generate signals if the sequential circuit element output changes logic levels, and comparison sub-circuits (716, 724) which compare the signal from the edge detection sub-circuits with a signal generated on an active edge of a clock signal of the sequential circuit element. The comparison sub-circuits detect an SEU or glitch if their two signals do not coincide. First and second gating sub-circuits (720, 728) permit the outputs of the comparison sub-circuits to asynchronously set or reset the sequential circuit element (702).

A semiconductor component includes a substrate including a plurality of source / drain implants in the form of rows and a charge storage structure disposed over the substrate. The charge storage structure includes at least three continuous layers including a first silicon oxide layer, a silicon nitride layer disposed on the first silicon oxide layer, and a second silicon oxide layer disposed on the silicon nitride layer. The semiconductor component further includes a plurality of gate structures in the form of columns disposed over the charge structure and extending perpendicular to the rows and further includes a radiation protection layer disposed over the charge storage structure and the plurality of gate structures. The radiation protection layer includes a radiation resistant material including boron having an isotope composition of at least 90% boron-11.

The invention relates to the technical field of chip design, in particular to a chip radiation suppression circuit which comprises a primary side ground, a secondary side ground and an isolation chip. Wherein the primary side ground comprises a first capacitor bank, and the secondary side ground comprises a second capacitor bank and a first magnetic bead group; the first capacitor bank comprises a first decoupling support capacitor bank and a first differential mode filter capacitor which are connected in parallel, and the second capacitor bank comprises a second decoupling support capacitor bank and a second differential mode filter capacitor which are connected in parallel; one end of the first decoupling support capacitor bank and one end of the first differential mode filter capacitor are connected with a primary side power supply input pin of the isolation chip, and the other end of the first decoupling support capacitor bank and the other end of the first differential mode filter capacitor are connected with a primary side grounding pin; one end of the second decoupling support capacitor bank and one end of the first differential mode filter capacitor are connected with a secondary power supply input pin of the isolation chip, and the other end of the second decoupling support capacitor bank and the other end of the first differential mode filter capacitor are connected with a secondary grounding pin; and one end of each magnetic bead in the first magnetic bead group is connected with each secondary side pin corresponding to the isolation chip, and the other end of each magnetic bead in the first magnetic bead group is connected with an external cable.

A circuit for mitigating single-event transients (SETs) comprising: a first sub-circuit comprising a first p-type transistor arrangement configured to produce a first output and a first n-type transistor arrangement configured to produce a second output; and a second sub-circuit comprising a connected p-type transistor arrangement and a connected n-type transistor arrangement connected in series, wherein the first output and the second output are electrically coupled to each other by the second sub-circuit.

The present disclosure is directed to a programmable logic device, such as a field programmable gate array (FPGA), that can withstand and operate in high radiation environments. The programmable logic device includes a bit line, a first logic gate coupled to the bit line, and a second logic gate coupled to the first logic gate and the bit line. The programmable logic device further includes a magnetoresistive memory circuitry coupled to the first logic gate and the second logic gate, the magnetoresistive memory circuitry including a non-volatile memory element and a latch. A third logic gate is coupled to the latch, a multiplexer (MUX) is coupled to the third logic gate and the bit line, and a tri-gate is coupled to the third logic gate, the MUX, and the bit line.

The invention discloses an anti-single particle risk system for a spacecraft, and the system is characterized in that a filtering module is connected to a power module, and is used for filtering noises and peaks with different frequencies in the power module; and the latch-up effect caused by the influence of transient voltage fluctuation on the CMOS in the chip is prevented. The signal limiting module is connected to the signal line and used for limiting the trigger current of the signal. And latch-up caused by CMOS well current abrupt change in the chip due to large current generated by the single event effect is prevented. And the level conversion module is connected to the high-sensitivity device and is used for ensuring the stability and the reliability of the power supply. And the surge protection module is connected to the power loop and is used for absorbing transient voltage, so that overvoltage protection is realized, and false triggering or latching of a subsequent circuit is prevented. And all power supply lines adopt a double-point double-line design, so that single-point failure caused by breakdown of a certain power distribution switch by a single particle is prevented. The control unit adopts a hot and cold dual redundancy measure of a host and a standby, and the management power supply module carries out hot backup, so that the normal work of the management power supply module is ensured.

Disclosed in the present application is a decoupling circuit. The decoupling circuit comprises: at least two decoupling units, which are connected in parallel. Each decoupling unit comprises a first capacitor assembly and a second capacitor assembly, which are connected in parallel, wherein the first capacitor assembly comprises at least two first capacitors, with the withstand voltage of each first capacitor being less than a power source voltage, and the second capacitor assembly comprises a second capacitor. The at least two first capacitors are connected in series, and are then connected in parallel to the second capacitor. In the first capacitor assembly, two adjacent first capacitors are connected to form a common terminal of the decoupling unit, and common terminals of a plurality of decoupling units are connected together.

The present disclosure describes various aspects of complementary 2(N)-bit redundancy for single event upset (SEU) prevention. In some aspects, an integrated circuit (104) includes a data storage element (206) to store a data value, another data storage element (202) to store a complementary data value, a multi-bit data storage element (e.g., a 2-bit storage element, (204)) to store both the data value and the complementary data value, and voting logic (124) that may enable a complementary data storage scheme with inter-circuit redundancy to prevent SEU. Additionally, the voting logic of the integrated circuit may enable detection and correction of data value errors and / or enable programming of voting logic criteria, which may be implemented dynamically based on a type of SEU failures that are detected or corrected.

A radiation-resistant encoder fault-tolerant system based on FPGA includes: a rotary transformer, a photoelectric encoder code disk, a photoelectric encoder working hardware circuit, a photoelectric encoder backup hardware circuit, a switching circuit, and an FPGA. The rotary transformer provides a reference for fault diagnosis and circuit switching. The photoelectric encoder code disk is used to measure angle information when the system is working normally. The switching circuit is used to switch to the backup hardware circuit when the working hardware circuit fails. The FPGA determines whether the working hardware circuit is working normally and controls the switching process. The FPGA includes an amplitude adjustment module, a phase compensation module, and an adaptive filtering module. Based on the output of the modules, the FPGA integrates the data and outputs the photoelectric encoder angle information processed by the FPGA. This invention can provide angle signals for motor control systems in radiation environments, improve the long-term reliability of encoder systems in nuclear radiation environments, and has the advantages of small size, low power consumption, and high resolution.

This disclosure describes various aspects of complementary 2(N) bit redundancy for single event upset (SEU) prevention. In some aspects, an integrated circuit (104) includes a data storage element (206) to store a data value, another data storage element (202) to store a complementary data value, a multi-bit data storage element (e.g., 2-bit storage element (204)) to store both the data value and the complementary data value, and voting logic (124) that can enable a complementary data storage scheme with inter-circuit redundancy for preventing SEUs. Additionally, the voting logic of the integrated circuit can implement detection and correction of data value errors and / or implement programming of voting logic criteria, which can be dynamically implemented based on the type of SEU fault detected or corrected.

A circuit 700 for detecting, and optionally correcting, single event upsets (SEU) or glitches in an electronic circuit includes at least one edge detection sub-circuit 710, 712 connected to a sequenti