Methods and circuitry for reconfigurable seu/set tolerance

Abstract

A device is disclosed in one embodiment that has multiple identical sets of programmable functional elements, programmable routing resources, and majority voters that correct errors. The voters accept a mode input for a redundancy mode and a split mode. In the redundancy mode, the programmable functional elements are identical and are programmed identically so the voters produce an output corresponding to the majority of inputs that agree. In a split mode, each voter selects a particular programmable functional element output as the output of the voter. Therefore, in the split mode, the programmable functional elements can perform different functions, operate independently, and / or be connected together to process different parts of the same problem.

Description

ORIGIN OF THE INVENTION[0001]The invention described herein was made by employee(s) of the United States Government and may be manufactured and used by or for the Government of the United States of America for governmental purposes without the payment of any royalties thereon or therefore.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates generally to circuitry which may be operated in environments whereby the circuitry is subject to single event upsets (SEU) and / or single event transients (SET) and, more specifically, to circuitry which is reconfigurable for adjusting the SEU / SET tolerance thereof.[0004]2. Description of Related Art[0005]The Field Programmable Gate Array (FPGA) is a type of programmable logic device (PLD). The FPGA may comprise an array of programmable tiles or programmable functional elements such as, for example, input / output blocks (IOBs), configurable logic blocks (CLBs), took up tables (LUTs), dedicated random access ...

AI Technical Summary

Benefits of technology

The present invention provides improved circuitry that is resistant to errors caused by single event upsets (SEU / SET) and offers increased data flow capacity in a non-redundant operating mode. The circuitry includes programmable functional elements and interconnections that can be reconfigured to adjust their SEU / SET tolerance. The circuitry can be organized into blocks that are physically separated from each other to prevent errors caused by a single SEU / SET. The invention also provides a method for making the reconfigurable circuitry. The technical effects of the invention include improved reliability, higher data flow capacity, and flexibility in design options.

Problems solved by technology

End-user designed techniques can be used to provide tailor made solutions which are more efficient with higher data capacity but may be less reliable due to greater difficulty in providing reliable SEU / SET mitigation.

However, there are many papers on the pitfalls of taking an FPGA and programming SEU / SET by adding redundancy through the firmware programming.

For example, there may be some underlying common source of error that is unknown due to the underlying structure of the chip.

Moreover, the circuitry is expensive to test due to the requirement for testing within an environment with sufficient radiation to cause errors.

However, software programming techniques may be less efficient, may take more time, and may intrude upon the application design.

Without TMR, scrubbing reduces the time period (potentially indefinite) during which the device is functioning erroneously.

Occasionally data is directly obtained by placing test specimens in Low Earth Orbit, but rarely in other instances due to impracticality.

Combating these faults requires more complex algorithmic or heuristic approaches that check whether outputs meet user-defined reasonableness criteria.

The above approaches do not solve the aforementioned problems.

The complexity and difficulty of end-user-designed mitigation is encountered over and over through the life cycle of the application.

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