59 results about "Hardware redundancy" patented technology

The invention discloses an EtherCAT master station synchronous control method and system based on a microkernel operating system, and belongs to the technical field of industrial automation field bus control. According to the system, a microkernel architecture is adopted, an EtherCAT protocol stack and a universal network protocol stack are deployed as two independent user mode processes, and data interaction is carried out through an inter-process communication and shared memory mechanism provided by a microkernel. According to the method, through a bidirectional dynamic clock compensation mechanism, static compensation in an initialization stage and dynamic compensation in an operation stage of a system are combined; a dynamic task scheduling strategy based on load awareness is adopted, and the task execution sequence is dynamically adjusted according to the CPU utilization rate and the task priority monitored in real time; a hardware redundancy design of double clock sources and double communication links is introduced, and a progressive synchronous recovery strategy is adopted during switching. According to the invention, nanosecond-level synchronization precision and microsecond-level fault switching can be realized, and the method is suitable for industrial control scenes with extremely high requirements on real-time performance and reliability.

The invention provides a brain electrical stimulation control method and device, a medium and computer equipment, and the method comprises the steps: setting an electrical stimulation period time signal through a local control module, and dividing the electrical stimulation period time signal into a stimulation stage, a window stage and a recovery stage with continuous time periods; in the stimulation stage, an electrical stimulation signal with preset parameters is output through the time-multiplexed electrode slice; in the empty window stage, disconnection or hardware protection is carried out on the electrode slices to shield crosstalk of stimulation signals to an electroencephalogram acquisition channel; in the recovery stage, electroencephalogram signals are collected and subjected to suppression algorithm processing to eliminate residual artifacts, and in the recovery stage, the collected electroencephalogram signals are subjected to suppression algorithm processing to eliminate residual low-frequency artifacts of electrode capacitance. The problems of hardware redundancy and artifact interference of an existing electrical stimulation system are effectively solved, and accuracy and safety are improved.

The invention relates to the technical field of digital ring main unit power distribution operation regulation and control, and discloses an intelligent power distribution operation regulation and control system of a digital ring main unit, which comprises a state sensing module, a logic judgment unit and an execution regulation and control module, the logic discrimination unit identifies a feeder power distribution state according to the power flow distribution data and generates a topology reconstruction scheme; the execution regulation and control module drives a switch to act, migrates the feeder loop to a target bus section, forms transition impedance by using closing pre-breakdown current during migration, inhibits transient inrush current, drives an impedance compensation branch to access according to a zero-sequence current vector of the feeder loop, and counteracts neutral point potential drift by using potential bias generated by reactive power injection; according to the method, the power distribution topology is converted from static hard connection to logic remapping, circuit transient state physical process reconstruction and stock hardware redundancy mining are utilized, node power vector balanced distribution is achieved under the condition that the feeder line continuous power receiving state is maintained, and power flow randomness conflicts are eliminated.

The invention provides a pulse detection method, communication equipment, a storage medium and a program product. The method comprises the following steps: acquiring a communication signal according to a clock reference signal of a receiver; after the first pulse detection result of the communication signal is passed, acquiring a control state of pulse frequency drift check of the communication signal; and according to the control state and the clock reference signal, pulse frequency drift detection is controlled to be enabled until pulse detection of the communication signal is completed. According to the invention, after the first pulse detection result of the communication signal is passing and the control state of obtaining the pulse frequency drift detection of the communication signal is forbidden, the pulse frequency drift detection is controlled to be enabled based on the clock reference signal and the correctness verification result, so that the control accuracy of pulse detection is improved, and the accuracy of pulse detection is improved. And the problem that a large amount of invalid software / hardware redundancy and resource waste exist under the working conditions that the configuration clock reference of the receiver is inconsistent, the number of configured half bytes of the receiver is inconsistent with the number of configured half bytes of the transmitter or the communication is unstable at the beginning is avoided.

The invention provides a fault-tolerant control method and device for a hand feeling simulator of a steer-by-wire system, and solves the problems that in the prior art, redundancy depends on hardware, the cost is high, faults of the hand feeling simulator cannot be effectively handled, and driving safety is harmed. The method specifically comprises the following steps: S1, monitoring the operation state of a hand feeling simulator system in real time; wherein the hand feeling simulator system comprises an MCU, a motor drive axle and a three-phase motor, and the MCU is connected with the three-phase motor through the motor drive axle; s2, when the hand feeling simulator system has an unrecoverable fault, disconnecting the connection between the motor and the motor drive axle; and S3, at least two phase lines connected to the three phase lines of the motor are controlled to form a short-circuit loop, resistance is provided for the vehicle steering wheel when the vehicle steering wheel is rotated, safety is high, cost is low, and control is easy and reliable.

The application discloses an EtherCAT master station synchronization control method and system based on a microkernel operating system, and belongs to the technical field of industrial automation fieldbus control. The system adopts a microkernel architecture, deploys an EtherCAT protocol stack and a general network protocol stack as two independent user state processes, and carries out data interaction through an inter-process communication and shared memory mechanism provided by the microkernel. The method combines static compensation in the system initialization stage and dynamic compensation in the running stage through a bidirectional dynamic clock compensation mechanism, adopts a dynamic task scheduling strategy based on load sensing, dynamically adjusts the task execution order according to the real-time monitored CPU usage and task priority, introduces a hardware redundancy design of double clock sources and double communication links, and adopts a gradual synchronization recovery strategy during switching. The application can realize nanosecond-level synchronization accuracy and microsecond-level fault switching, and is suitable for industrial control scenes with extremely high real-time and reliability requirements.

The invention relates to an improved systolic array computing device capable of improving pipeline efficiency, the device comprises an input characteristic value cache array, a multiply-accumulate array and an output characteristic value cache array, and the multiply-accumulate array is composed of N * N multiply-accumulate units. In order to improve the utilization rate of the array, data paths connected end to end are added in the horizontal direction and the vertical direction respectively, so that the array forms a Torus annular interconnection structure; input characteristic values are injected through diagonal positions, partial sum results are annularly accumulated in the vertical direction, so that continuous flow of input and partial sum is achieved, the structure remarkably reduces assembly line filling and emptying delay, hardware redundancy caused by input and output FIFO arrays in a traditional systolic array is avoided, calculation of a 512 * 512 matrix through a 256 * 256 array is taken as an example, and the structure has the advantages of being simple in structure, convenient to operate and low in cost. The calculation delay is reduced from 2560 clock cycles to 2176 clock cycles, and the array utilization rate is improved to 94%. The method has the advantages of being high in efficiency, low in cost, good in expansibility and suitable for neural network and matrix calculation acceleration.

The invention discloses a busbar differential protection capacity expansion method and system and a storage medium, and belongs to the technical field of power system relay protection. The method is applied to a double-bus wiring system configured with two sets of redundant bus differential protection devices, and the core is a differential transformation scheme: firstly analyzing hardware configuration and branch distribution conditions of the two sets of devices, directly adding a branch to a device with spare resources, and accessing a newly-added main transformer interval; and for the device with the full branches, the access position is vacated by adjusting the branch distribution of the existing incoming line interval and the main transformer interval. In the construction process, short circuit is carried out first and then reconnection is carried out to guarantee the safety of a current loop, and hardware wiring optimization, protection program upgrading and function verification are matched to complete transformation. The corresponding system comprises the bus differential protection device transformed by the method, and a computer readable storage medium for storing a program upgrading step. The whole set of equipment does not need to be replaced, the existing hardware redundancy expansion function is utilized, the modification cost is low, the safety risk is small, and the flexibility is high.

The invention relates to the technical field of power electronic conversion, and discloses a power conversion circuit and a UPS (Uninterrupted Power Supply) system, which realize an AC / DC (Alternating Current / Direct Current) rectification function in a mains supply mode and a DC / DC boosting function in a battery mode on a single set of hardware through innovative circuit design and device multiplexing on the premise of not obviously increasing hardware cost, and further realize a power conversion function in a battery mode. The system structure is simplified, the cost is reduced, and the power density is improved. According to the design, the multifunctionality of the existing device is fully utilized, and the problems of hardware redundancy and cost increase are avoided. Meanwhile, as the number of devices and the circuit complexity are reduced, the reliability of the system is improved, and the maintenance difficulty is reduced. Besides, due to the improvement of the power density, the whole power conversion circuit can support higher power output under the same size, or more compact design can be realized under the same power requirement, and powerful support is provided for integration and miniaturization of medium-power UPS power supply equipment.

The utility model relates to a kind of low-pressure four-axis robot hardware circuit, comprising: core board, mainboard, drive board, safety relay, switching power supply and AC contactor;The core board is connected with the mainboard, the mainboard is connected with the drive board, and the mainboard is connected with safety relay by relay control line, and the safety relay is connected with the AC contactor by contact control line, and the AC contactor is connected with the drive board by switching power supply;The core board, mainboard and drive board constitute electronic circuit part, optimize the controller multi-core heterogeneous computing architecture, realize software and hardware collaborative processing, provide powerful computing power for controller;With modularization thought design relevant PCB, guarantee the multiplicity of PCB;Using safety relay and AC contactor designs double-loop structure, through hardware redundancy, real-time monitoring and high-level safety certification, complete fault tolerance to single point is realized, while giving consideration to quick response and maintainability.

The invention discloses a hydraulic station full-link dual-software-hardware redundancy control system which is characterized by comprising dual-software-hardware redundancy and a redundancy control switching mechanism, the dual-software-hardware redundancy comprises two sets of hardware, and the two sets of software can be switched mutually during use; the dual software and hardware redundancy comprises sensor redundancy, data acquisition module redundancy, control module redundancy, control mechanism redundancy, human-computer interface redundancy, data storage redundancy and communication redundancy; the redundancy control switching mechanism comprises a switching execution mechanism and switching arbitration logic, whether switching is carried out or not is judged according to the switching arbitration logic, and dual software and hardware are switched through the switching execution mechanism. The invention provides a first dual-channel software and hardware deep redundancy architecture covering full links of perception-decision-execution-man-machine interaction-storage, and solves the core problem of undisturbed switching of hydraulic control.

The invention designs a redundant fault-tolerant control system and control method for a distributed drive-by-wire chassis, and the system achieves the high-reliability operation of a whole drive-by-wire chassis system through the multi-level redundant design including power subsystem redundancy, dual-controller hot backup redundancy and four-corner module independent control mutual redundancy in combination with a degradation fault-tolerant mechanism. The system comprises components such as DCDC, a low-voltage storage battery, double controllers, four distributed corner modules and various sensors, corresponding fault diagnosis and safety control strategies are configured, and the core of the system is that through collaborative design of hardware redundancy and software fault tolerance, it is ensured that the system can still maintain basic safety functions under the condition that one or more components have faults, and the system is safe and reliable. And the safety and the reliability of the drive-by-wire chassis are obviously improved.

The invention discloses a forklift electronic control hardware redundancy system, and relates to the field of forklift control. Comprising a main control module which processes a driving instruction and sensor data in real time, generates an execution mechanism control signal and synchronizes parameters to a standby module through a high-speed bus; the standby control module realizes non-inductive control right takeover through a dynamic thermal synchronization method when the main system fails; the multi-channel fault detection module is used for carrying out fault detection on system operation through the sensor module, and the arbitration switching module is used for carrying out control switching after the multi-channel fault detection module detects a system fault. The failure state of the main control channel is accurately judged on the basis of parameters calculated in real time, the control right is switched to the standby module in an undisturbed mode through the arbitration switching module, the fatal defect that a traditional system is shut down when a fault occurs is broken through, a forklift is kept in a continuous controllable state under sudden faults such as controller short circuit and signal distortion, and the system reliability is improved. And the systematic collapse risk of a single channel architecture is fundamentally eliminated.

The invention relates to a multi-thread parallel redundancy fault-tolerant method based on a compilation layer. The invention relates to the technical field of embedded processor design. The method comprises the following steps: determining thread division and an SoR region core; packaging an SoR region related fault-tolerant function library, packaging a core fault-tolerant function into a header file, and ensuring that a library file contains a tool function strongly associated with the SoR region; matching the compiler with the tool chain; marking and automatically identifying the source program; automatically identifying and supplementing the ROSE compiler; compiling the SoR region and generating a dual-thread code; performing double-thread parallel execution and check point interaction; and redundant fault-tolerant processing and flow continuation are carried out. The method does not depend on a specific hardware platform, and the problem of poor portability of a traditional hardware redundancy technology or a fault-tolerant technology depending on a specific hardware architecture is effectively avoided.

The invention relates to a power supply current detection method based on a BMS system, and relates to the technical field of battery management systems, current sensors are configured at the positive electrode input end and the negative electrode output end of a battery respectively to construct hardware redundancy, and the method comprises the following steps that the reading Ipos of the positive electrode current sensor and the reading Ineg of the negative electrode current sensor are collected in real time and preprocessed; respectively carrying out validity judgment on the preprocessed Ipos and Ineg and a preset normal working current range [Imin, Imax]; according to the validity judgment result, multi-mode arbitration is carried out based on a fault-safety principle, and one of a single-sensor failure mode, a double-sensor consistent mode, a double-sensor conflict mode and a double-sensor failure mode is automatically selected; and outputting the final system current value Ifinal for SOC estimation, thermal management and / or power control of the BMS. According to the method, the problem that the system is out of control possibly caused by failure of a single-point sensor or data conflict of double sensors in the existing BMS current detection technology is solved.

The application relates to the field of computer storage, and discloses an FPGA-based SSD controller verification method and system, which aims to solve the problems of hardware redundancy, non-systematic verification and poor flexibility of a verification scheme in a high-integration board card environment. Technical solution points: the verification method is divided into three stages, that is, first, a hardware environment is constructed through FPGA integration verification, then, basic functions and performance are tested through data disk verification, and finally, system-level testing and version solidification are completed through system disk verification; the verification system comprises a host computer and an integrated board card, and an FPGA module integrates an SSD controller and network interface function logic. The application does not require additional hardware, realizes low-cost and systematic comprehensive verification, and is suitable for function and performance verification of an SSD controller in a high-integration board card environment.

The invention discloses a redundancy control circuit and method for a passive relay protection device, and belongs to the technical field of relay protection, and the control circuit comprises a current sampling loop, a main control chip, and a hardware redundancy overcurrent protection system. Wherein the current sampling loop is used for converting a three-phase current of a power grid into a sampling voltage signal and respectively inputting the sampling voltage signal into the main control chip and the hardware redundancy overcurrent protection system; the main control chip is used for realizing software protection of a power grid according to an input sampling voltage signal; and the hardware redundancy overcurrent protection system is used for realizing hardware redundancy protection of the power grid according to the input sampling voltage signal. According to the invention, based on the existing software protection process of the relay protection device, a redundant hardware protection loop is additionally designed, so that when a line fails, a software system can be effectively prevented from downtime.

The invention discloses an automatic test system for safety PLC module production, and relates to the technical field of safety PLC production test. The system comprises an industrial all-in-one machine, a signal source control device and extensible peripheral test equipment, supports interaction with an MES server system, and can realize full-process automatic test of a to-be-tested safety PLC card. Parameter configuration and data management are completed through the industrial all-in-one machine, it is guaranteed that test data are locally stored and uploaded to the MES server, the traceability of the test data is guaranteed, and the signal source control device designs special tests of time-sharing automatic burning, redundant channel isolation testing and fault simulation according to the characteristics of hardware redundancy, self-diagnosis and the like of the safety PLC. Test automation, coverage comprehensiveness, data traceability and process flexibility are realized in the production of the safety PLC module, the test efficiency and the product quality are remarkably improved, and the method is suitable for a large-scale production test scene of an industrial-grade safety PLC.

The invention discloses a Flash starting system and method based on a trusted measurement mechanism. The Flash starting system and method are suitable for starting scenes of main and standby Flash memories of domestic CPUs (central processing units). The system comprises a domestic CPU (central processing unit), a CPLD (complex programmable logic device), a TPCM (trusted platform control module), a main Flash memory, at least one standby Flash memory and a GPIO (general purpose input / output) signal line. And the CPLD expands a single-path SPI interface of the CPU into multiple paths through logic programming, and is connected with the main Flash and the standby Flash to realize intelligent switching. The TPCM performs trusted measurement on the boot firmware of the main and standby Flash memories after the system is powered on, so that the integrity of the boot firmware is ensured. And during starting, loading is preferentially carried out from the main Flash memory, and if the loading fails, the standby Flash memory is automatically switched to, so that the starting reliability and stability of the system are improved. Through combination of hardware redundancy and trusted measurement, malicious starting of firmware loading is effectively prevented, and safe and stable operation of the system is guaranteed.

This invention discloses a server PCIe resource adaptive configuration method, relating to the fields of server architecture and PCIe high-speed bus configuration technology. Addressing the problems of existing solutions such as reliance on custom BIOS development, timing incompatibility, lack of resource arbitration, inability to dynamically optimize, and operational redundancy, this invention adopts a fully hardware-coordinated architecture of the motherboard and component-side CPLD. It completes time-division reporting of topology data and four-level hardware trusted verification through the native sideband channel of the UBC cable. Through hardware-based resource conflict arbitration and cross-CPU platform register conversion, the configuration table is generated and locked before BIOS PCIe initialization. Simultaneously, it supports OS runtime load monitoring, incremental bandwidth adjustment, and hot-swappable adaptive configuration, combined with parallel cable status alarms and automatic fault rollback mechanisms. This invention eliminates reliance on custom BIOS, is compatible with standard power-on timings, improves configuration stability and resource utilization in complex scenarios, reduces hardware redundancy and operational costs, and is applicable to general server PCIe resource adaptive management.

The invention discloses a heating system, a server and a heating method, and relates to the technical field of computers, and the heating system comprises a temperature monitoring assembly which is used for monitoring the first case temperature of a target server; the control assembly is used for sending a heating starting signal to the heating assembly when the first case temperature is lower than a first preset temperature and sending a first heating stopping signal when the first case temperature is higher than a second preset temperature; the heating assembly is used for entering a heating state after receiving the heating starting signal and stopping heating after receiving the first heating stopping signal; the redundancy control part is used for monitoring the second case temperature of the target server, and when the second case temperature is larger than the third preset temperature and the heating assembly is in the heating state, a power-off safety instruction is sent to the power management assembly, and power supply to the heating assembly is cut off. Therefore, by introducing a hardware redundancy control mechanism independent of the main control system, the problems that a heating circuit continuously works and equipment is overheated and damaged due to failure of software and hardware of a control assembly are solved.

The invention discloses a sub-megahertz-level high-precision low-cost embedded multi-channel synchronous current acquisition platform. The sub-megahertz-level high-precision low-cost embedded multi-channel synchronous current acquisition platform comprises a sensing and analog circuit module, a data acquisition module and a data transmission module which work cooperatively, the sensing and analog circuit module comprises a plurality of AC-AC sensors and analog circuits; the data acquisition module comprises a multi-channel synchronous sampling ADC and a low-cost dual-core MCU; and the data transmission module is electrically connected with one core of the dual-core MCU. According to the invention, the ADC is synchronously sampled through multiple channels, and the multiple ADCs share the same SPI interface design, so that the hardware redundancy cost is reduced; a time stamp is generated through combination of a voltage period ID and a phase value format, and a global voltage sequence is constructed through voltage values collected by sensor nodes, so that a global current sequence which is synchronously collected is constructed, high-precision synchronous current sampling is realized, extra synchronous hardware is not needed, the upper bound of a synchronous error is remarkably reduced, and the synchronous error is not increased along with the distance.

This invention relates to the field of digital ring main unit (RN) power distribution operation and control technology, and discloses an intelligent power distribution operation and control system for digital RN, including a state perception module, a logic discrimination unit, and an execution control module. The logic discrimination unit identifies the power distribution status of the feeder based on power flow distribution data and generates a topology reconfiguration scheme. The execution control module drives the switch action to migrate the feeder circuit to the target bus section. During the migration, the pre-breakdown current of the closing circuit is used to form a transition impedance to suppress transient inrush current. The zero-sequence current vector of the feeder circuit drives the impedance compensation branch connection, and the potential bias generated by reactive power injection is used to offset the neutral point potential drift. This invention realizes the transformation of the power distribution topology from static hard connection to logical remapping. By utilizing the reconstruction of circuit transient physical processes and the mining of existing hardware redundancy, the power vector distribution of nodes is balanced while maintaining continuous power supply to the feeder, thus resolving random power flow conflicts.

The invention relates to the technical field of mine fire safety monitoring, in particular to a hardware redundancy design smoke sensor based on a heterogeneous isolation structure and a use method.The smoke sensor comprises a control cavity, a circuit board, a main control board, a photoelectric smoke sensing unit and an ionic smoke sensing unit; the operation mode comprises a fusion operation mode in which the photoelectric smoke detector and the ion smoke detector synchronously transmit signals to calculate the smoke concentration value, and a single detector operation mode in which the smoke concentration value is calculated through the other detector in a failure state of one detector. The system is suitable for coverage of various types of smoke, the environment anti-interference capability is high, the fault switching response is fast, accurate monitoring and automatic fault switching of coal dust smoldering smoke and electromechanical combustion smoke are achieved, and continuity and reliability of mine fire early warning are guaranteed.

The invention discloses a permanent magnet positioning 6DOF resolving LM algorithm implementation method and device, relates to the technical field of permanent magnet positioning and FPGA hardware acceleration, and can significantly improve the real-time performance, the single iteration time is less than or equal to 5 ms, the sliding window update delay is less than or equal to 2 ms, and a 20 ms magnetic moment period is adapted. Hardware redundancy can be reduced, only 10 points are replaced during window updating, and the recalculation amount and power consumption are reduced. And by removing old data and introducing new data, the positioning precision is kept to be less than or equal to 0.5 mm, and the attitude angle precision is kept to be less than or equal to 0.1 degree. In addition, the method also has good robustness, and the system stability is improved by counter binding, exception elimination and a backup data mechanism.

The utility model provides a testing device after abnormal parking of a maglev train, relates to the technical field of maglev train detection, and realizes efficient and safe detection of the maglev train in an abnormal parking state through non-contact electromagnetic coupling detection, multi-source sensor fusion and hardware redundancy design. The electromagnetic induction module utilizes the magnetic field coupling principle to replace physical contact, electromagnet dynamic parameter acquisition can be completed in an electrified state, and the short circuit risk in the detection process is reduced. The attitude acquisition module can break through the inclination angle detection range limitation of a traditional sensor and enlarge the detection range of a train; the two groups of microprocessors and the independent power supply architecture ensure parallel processing of multi-channel data and continuous power-off working capability, and the detection reliability under complex working conditions is improved. The whole set of device has strong environmental adaptability while ensuring the detection precision, and provides a rapid and accurate solution for rapid diagnosis and emergency disposal after abnormal parking of the maglev train.

The application discloses a kind of Flash starting system and method based on credibility measurement mechanism, and is suitable for domestic CPU main and standby Flash memory starting scene.System includes domestic CPU, CPLD device, trusted platform control module TPCM, main Flash memory, at least one standby Flash memory and GPIO signal line.CPLD is connected with main and standby Flash by logic programming expansion CPU single SPI interface to multiple, and realizes intelligent switching.TPCM carries out trusted measurement to the starting firmware of main and standby Flash memory after system power on, and ensures starting firmware integrity.When starting, it is loaded from main Flash memory preferentially, and automatically switches to standby Flash memory if it fails, to improve system starting reliability and stability.The application effectively prevents malicious starting firmware loading by combining hardware redundancy with trusted measurement, and guarantees safe and stable operation of system.

The invention discloses a multi-SOC-based camera controller on-orbit autonomous reconstruction system and method, and relates to the technical field of space camera master control. The invention aims to solve the problem that the single event effect (such as function error or disorder) of the SOC device is easily caused in the space intense radiation environment in the prior art. Comprising a main control unit, an SPI communication data line, a switch channel unit, a FLASH storage unit, a CAN bus communication unit, an RS-422 bus communication unit, a focusing control unit and a temperature control and detection unit. According to the invention, three SOCs are adopted to form hardware redundancy, on-orbit autonomous error detection and correction functions are realized, and the operation stability and reliability of the camera controller in a harsh space radiation environment are effectively improved. The switch channel unit is adopted to dynamically allocate the peripheral control right, when a certain SOC fails, the SOC can be seamlessly switched to a normal SOC to take over a peripheral channel of the SOC, and the function continuity is guaranteed; and after the fault SOC is recovered, the default configuration can be automatically switched back.

The application provides a kind of on-board routing telemetry remote control method based on multi-thread architecture, comprising: on-board routing telemetry remote control system adopts multi-thread architecture to realize parallel processing: telemetry acquisition thread is used to collect system telemetry data with every second as cycle, and according to E_PDU encoding format, telemetry data is stored to memory;Remote control execution thread is used to cyclically monitor task queue, when there is remote control instruction task in the queue, the instruction is parsed and executed, and the execution state is fed back to telemetry data storage to memory;Time synchronization thread is used to continuously monitor PPS, and combine the received time broadcast frame to carry out microsecond level calibration to system time;Main thread is used to monitor GPIO interrupt event in real time.The application supports E_PDU data encoding format and CAN protocol split data transmission, and improves reliability through hardware redundancy, software redundancy and data checking mechanism, solves the technical problem of on-orbit real-time control and high fault tolerance demand of on-board routing equipment.