7 results about "Hardware redundancy" patented technology

The application discloses a spacecraft active thermal control cross backup temperature control system and a control method thereof, and relates to the technical field of spacecraft thermal control.The system comprises a temperature control partition assembly, a main part and a backup heating circuit, a main part and a backup temperature sensor, an intelligent management bus and an intelligent temperature control unit.The main part heating circuit and the backup heating circuit are integrated in the same heating sheet, and the temperature sensor is installed closely at the same temperature measuring point.The intelligent temperature control unit only controls the main part heating circuit to work in the default mode;when it is determined that the power of the main part heating circuit is insufficient and the power of the whole satellite has a margin, the backup heating circuit is controlled to work simultaneously with the main part, so that the power is superposed;after the temperature meets the standard, the main part and the backup are stopped simultaneously and the default mode is restored.The application breaks through the backup thinking of switching only when a traditional fault occurs, reconstructs the backup heater from hardware redundancy to power redundancy, dynamically compensates the power gap in orbit without increasing the hardware cost, and improves the robustness and reliability of the spacecraft thermal control system.

The utility model relates to a kind of low-pressure four-axis robot hardware circuit, comprising: core board, mainboard, drive board, safety relay, switching power supply and AC contactor;The core board is connected with the mainboard, the mainboard is connected with the drive board, and the mainboard is connected with safety relay by relay control line, and the safety relay is connected with the AC contactor by contact control line, and the AC contactor is connected with the drive board by switching power supply;The core board, mainboard and drive board constitute electronic circuit part, optimize the controller multi-core heterogeneous computing architecture, realize software and hardware collaborative processing, provide powerful computing power for controller;With modularization thought design relevant PCB, guarantee the multiplicity of PCB;Using safety relay and AC contactor designs double-loop structure, through hardware redundancy, real-time monitoring and high-level safety certification, complete fault tolerance to single point is realized, while giving consideration to quick response and maintainability.

The application relates to the field of computer storage, and discloses an FPGA-based SSD controller verification method and system, which aims to solve the problems of hardware redundancy, non-systematic verification and poor flexibility of a verification scheme in a high-integration board card environment. Technical solution points: the verification method is divided into three stages, that is, first, a hardware environment is constructed through FPGA integration verification, then, basic functions and performance are tested through data disk verification, and finally, system-level testing and version solidification are completed through system disk verification; the verification system comprises a host computer and an integrated board card, and an FPGA module integrates an SSD controller and network interface function logic. The application does not require additional hardware, realizes low-cost and systematic comprehensive verification, and is suitable for function and performance verification of an SSD controller in a high-integration board card environment.

This invention discloses a server PCIe resource adaptive configuration method, relating to the fields of server architecture and PCIe high-speed bus configuration technology. Addressing the problems of existing solutions such as reliance on custom BIOS development, timing incompatibility, lack of resource arbitration, inability to dynamically optimize, and operational redundancy, this invention adopts a fully hardware-coordinated architecture of the motherboard and component-side CPLD. It completes time-division reporting of topology data and four-level hardware trusted verification through the native sideband channel of the UBC cable. Through hardware-based resource conflict arbitration and cross-CPU platform register conversion, the configuration table is generated and locked before BIOS PCIe initialization. Simultaneously, it supports OS runtime load monitoring, incremental bandwidth adjustment, and hot-swappable adaptive configuration, combined with parallel cable status alarms and automatic fault rollback mechanisms. This invention eliminates reliance on custom BIOS, is compatible with standard power-on timings, improves configuration stability and resource utilization in complex scenarios, reduces hardware redundancy and operational costs, and is applicable to general server PCIe resource adaptive management.

The embodiment of the present disclosure discloses a processor global multi-mode unlocking method, a processor, a medium and a program product. The method comprises the following steps: setting a timer, which is used to record the duration of the microinstruction execution stagnation in the processor when the reorder unit is not empty; setting multiple unlocking modes and the exclusive threshold of each unlocking mode; triggering the corresponding unlocking mode to perform the unlocking operation when the duration is greater than the exclusive threshold of any unlocking mode and less than the maximum upper limit; determining the unlocking success when there is a new microinstruction submission, and resetting the timer; triggering a fatal error alarm when the duration is greater than or equal to the maximum upper limit. The method can break through the scene limitation of the module-level unlocking through the unlocking mechanism of globalization, multi-mode and supporting mixed calls, efficiently solve the microinstruction submission blocking problem caused by cross-module or global resources, and reduce the hardware redundancy and improve the adaptation ability to new abnormal scenes.

This invention discloses a dual-redundant control system and method for an eVTOL tilt rotor actuator, belonging to the field of electric vertical takeoff and landing (eVTOL) control technology. This invention constructs a four-layer fully closed-loop logical architecture—data layer, algorithm layer, control layer, and application layer—deeply integrating four key technologies: precise modeling of the crank-rocker mechanism, online optimization using fifth-order polynomials, real-time compensation using three-loop PID control, and seamless switching between primary and backup drives. It innovatively achieves: ① smooth switching between primary and backup drives within 100ms (stepped lift output, shock-free); ② full-stroke angle control accuracy ≤ ±1.5°, displacement accuracy ≤ 0.1mm; ③ angle locking ≤ ±0.5° in fault conditions, retaining ≥50% of the stroke; ④ one-click macro definition switching between desktop debugging and embedded operation. This invention solves the defect of hardware redundancy and control system disconnect, providing a highly reliable and high-precision control solution for tilt rotor eVTOLs.

This invention discloses a dedicated protocol conversion device and embedded system management circuit for the VME bus, comprising: a PCIe interface circuit, a protocol conversion core circuit composed of a domestic FPGA chip (JFM7K325T), a VME bus driver circuit composed of an MS8T245TP-I bus transceiver, and a backplane interface circuit. The device completes the hardware conversion from PCIe to VME bus protocol using a single chip through an address decoder, data buffer, control state machine, and interrupt management logic embedded within the FPGA. This invention also integrates an embedded system hardware monitoring circuit, which is fixedly connected to a domestic RTC clock chip, temperature sensor chip, and EEPROM chip via an I2C bus, and uses hardware timers and hardware address generation logic to achieve periodic automatic hardware recording of log data. This invention solves the technical problems of high hardware redundancy, reliance on imported chips, and poor signal integrity in existing VME bus interface solutions, achieving complete independent control from the chip level to the circuit level.