75 results about "Hardware redundancy" patented technology

The invention provides a multichannel gas ultrasonic flowmeter, which relates to the technical field of flow measurement and comprises a hardware layer and a software layer, the hardware layer comprises a pipeline, a connecting mechanism, a multichannel ultrasonic transducer, a pressure sensor, a temperature sensor, a wiring terminal box and a control box with an LCD display screen; the software layer comprises a data acquisition module, a preprocessing module, a multichannel speed measurement module, a data fusion module, a dynamic parameter compensation module, a flow calculation module, a man-machine interaction module, a communication module and a storage module. Pipeline section flow velocity information is collected through a multichannel ultrasonic transducer array, and a complex flow state is fitted in combination with a weighted fusion algorithm; the flow is dynamically compensated and corrected based on pressure and temperature; reliable operation of the system is guaranteed by means of hardware redundancy and a software verification diagnosis mechanism, the problems that a traditional flowmeter is low in measurement precision and poor in working condition adaptability are solved, and high-precision and stable gas flow measurement is achieved.

The invention provides an optimization method for sharing one group of physical registers by multiple groups of logic registers, which comprises the following steps: S1, defining a shared physical register file, the step comprises a physical register structure link and a quantity constraint link, the physical register structure link comprises N vector physical registers with VLEN bit width, and the quantity constraint link comprises N vector physical registers with VLEN bit width; each vector physical register can be divided into VLEN / FLEN floating point physical registers; in order to solve the problem of hardware redundancy caused by independence of a floating point register and a vector register in an RISC-V architecture, instruction pipeline sharing of floating point and vector expansion is realized through a scheme that multiple groups of logic registers share a physical register, and the hardware redundancy is avoided. And hardware overhead is reduced.

The invention provides a satellite-borne routing telemetering and remote control method based on a multi-thread framework, which comprises the following steps: a satellite-borne routing telemetering and remote control system adopts the multi-thread framework to realize parallel processing: a telemetering acquisition thread is used for acquiring system telemetering data by taking per second as a period and storing the telemetering data into a memory according to an EPDU (Extended Protocol Data Unit) coding format; the remote control execution thread is used for circularly monitoring a task queue, analyzing and executing an instruction when a remote control instruction task exists in the queue, and feeding back an execution state to the telemetry data storage memory; the time synchronization thread is used for continuously monitoring the PPS and performing microsecond-level calibration on the system time in combination with the received time broadcast frame; the main thread is used for monitoring GPIO interrupt events in real time. According to the invention, the EPDU data coding format and CAN protocol split data transmission are supported, the reliability is improved through hardware redundancy, software redundancy and a data verification mechanism, and the technical problems of on-orbit real-time control and high fault tolerance requirements of satellite-borne routing equipment are solved.

The invention provides a wheel speed detection device and a chip system. The wheel speed detection device comprises a first comparator, a second comparator and a signal analyzer, the first comparator and the second comparator are respectively configured with different reference voltages, and the input end of the first comparator and the input end of the second comparator are used for receiving voltage signals generated by the same wheel speed sensor; and the signal analyzer is used for analyzing the wheel speed information according to the first comparison signal output by the first comparator and the second comparison signal output by the second comparator. Thus, the input signal is subjected to multi-threshold judgment by using a double-comparator structure, so that sensor signals of different current levels can be identified and analyzed uniformly, and compatible processing of sensor signals of multiple protocols is realized. Therefore, the problem that the overall system cost is increased due to hardware redundancy and system complexity increase in a traditional scheme is avoided, and the universality and the integration capacity of the interface module are effectively improved in a low-cost mode.

The invention relates to the technical field of steam turbine safety monitoring, in particular to a method and system for arranging an OC bus of a TSI system, and the method comprises the steps: dividing the OC bus into three types of independent main channels, namely a data collection bus, a communication bus and an address and working condition bus, in a physical layout layer; a grounding design of separating an analog ground from a digital ground and a resistance buffer circuit are arranged in a matched manner to form a multi-layer anti-interference system, and different buses are arranged in a layered manner; the hardware redundancy layer constructs a double-inter-phase hard wiring redundancy channel by depending on an independent channel reserved by physical layout, a fault switching mechanism is formed by combining a relay and a control node, and the redundancy channel is physically isolated from a main channel; and the intelligent algorithm layer constructs a state space according to an address bus and a power channel state in the physical layout layer, and performs iterative optimization on an algorithm decision through a dynamic allocation model in combination with a fault feedback signal of the hardware redundancy layer. According to the scheme, the OC bus is arranged by adopting a three-layer progressive structure, so that the transmission reliability is improved.

The invention discloses an EtherCAT master station synchronous control method and system based on a microkernel operating system, and belongs to the technical field of industrial automation field bus control. According to the system, a microkernel architecture is adopted, an EtherCAT protocol stack and a universal network protocol stack are deployed as two independent user mode processes, and data interaction is carried out through an inter-process communication and shared memory mechanism provided by a microkernel. According to the method, through a bidirectional dynamic clock compensation mechanism, static compensation in an initialization stage and dynamic compensation in an operation stage of a system are combined; a dynamic task scheduling strategy based on load awareness is adopted, and the task execution sequence is dynamically adjusted according to the CPU utilization rate and the task priority monitored in real time; a hardware redundancy design of double clock sources and double communication links is introduced, and a progressive synchronous recovery strategy is adopted during switching. According to the invention, nanosecond-level synchronization precision and microsecond-level fault switching can be realized, and the method is suitable for industrial control scenes with extremely high requirements on real-time performance and reliability.

The invention provides a brain electrical stimulation control method and device, a medium and computer equipment, and the method comprises the steps: setting an electrical stimulation period time signal through a local control module, and dividing the electrical stimulation period time signal into a stimulation stage, a window stage and a recovery stage with continuous time periods; in the stimulation stage, an electrical stimulation signal with preset parameters is output through the time-multiplexed electrode slice; in the empty window stage, disconnection or hardware protection is carried out on the electrode slices to shield crosstalk of stimulation signals to an electroencephalogram acquisition channel; in the recovery stage, electroencephalogram signals are collected and subjected to suppression algorithm processing to eliminate residual artifacts, and in the recovery stage, the collected electroencephalogram signals are subjected to suppression algorithm processing to eliminate residual low-frequency artifacts of electrode capacitance. The problems of hardware redundancy and artifact interference of an existing electrical stimulation system are effectively solved, and accuracy and safety are improved.

The invention relates to the technical field of digital ring main unit power distribution operation regulation and control, and discloses an intelligent power distribution operation regulation and control system of a digital ring main unit, which comprises a state sensing module, a logic judgment unit and an execution regulation and control module, the logic discrimination unit identifies a feeder power distribution state according to the power flow distribution data and generates a topology reconstruction scheme; the execution regulation and control module drives a switch to act, migrates the feeder loop to a target bus section, forms transition impedance by using closing pre-breakdown current during migration, inhibits transient inrush current, drives an impedance compensation branch to access according to a zero-sequence current vector of the feeder loop, and counteracts neutral point potential drift by using potential bias generated by reactive power injection; according to the method, the power distribution topology is converted from static hard connection to logic remapping, circuit transient state physical process reconstruction and stock hardware redundancy mining are utilized, node power vector balanced distribution is achieved under the condition that the feeder line continuous power receiving state is maintained, and power flow randomness conflicts are eliminated.

The invention provides a pulse detection method, communication equipment, a storage medium and a program product. The method comprises the following steps: acquiring a communication signal according to a clock reference signal of a receiver; after the first pulse detection result of the communication signal is passed, acquiring a control state of pulse frequency drift check of the communication signal; and according to the control state and the clock reference signal, pulse frequency drift detection is controlled to be enabled until pulse detection of the communication signal is completed. According to the invention, after the first pulse detection result of the communication signal is passing and the control state of obtaining the pulse frequency drift detection of the communication signal is forbidden, the pulse frequency drift detection is controlled to be enabled based on the clock reference signal and the correctness verification result, so that the control accuracy of pulse detection is improved, and the accuracy of pulse detection is improved. And the problem that a large amount of invalid software / hardware redundancy and resource waste exist under the working conditions that the configuration clock reference of the receiver is inconsistent, the number of configured half bytes of the receiver is inconsistent with the number of configured half bytes of the transmitter or the communication is unstable at the beginning is avoided.

The invention provides a fault-tolerant control method and device for a hand feeling simulator of a steer-by-wire system, and solves the problems that in the prior art, redundancy depends on hardware, the cost is high, faults of the hand feeling simulator cannot be effectively handled, and driving safety is harmed. The method specifically comprises the following steps: S1, monitoring the operation state of a hand feeling simulator system in real time; wherein the hand feeling simulator system comprises an MCU, a motor drive axle and a three-phase motor, and the MCU is connected with the three-phase motor through the motor drive axle; s2, when the hand feeling simulator system has an unrecoverable fault, disconnecting the connection between the motor and the motor drive axle; and S3, at least two phase lines connected to the three phase lines of the motor are controlled to form a short-circuit loop, resistance is provided for the vehicle steering wheel when the vehicle steering wheel is rotated, safety is high, cost is low, and control is easy and reliable.

The application discloses an EtherCAT master station synchronization control method and system based on a microkernel operating system, and belongs to the technical field of industrial automation fieldbus control. The system adopts a microkernel architecture, deploys an EtherCAT protocol stack and a general network protocol stack as two independent user state processes, and carries out data interaction through an inter-process communication and shared memory mechanism provided by the microkernel. The method combines static compensation in the system initialization stage and dynamic compensation in the running stage through a bidirectional dynamic clock compensation mechanism, adopts a dynamic task scheduling strategy based on load sensing, dynamically adjusts the task execution order according to the real-time monitored CPU usage and task priority, introduces a hardware redundancy design of double clock sources and double communication links, and adopts a gradual synchronization recovery strategy during switching. The application can realize nanosecond-level synchronization accuracy and microsecond-level fault switching, and is suitable for industrial control scenes with extremely high real-time and reliability requirements.

The invention discloses a data analysis method and device, equipment and a computer storage medium, and the method comprises the steps: determining a subframe proportion corresponding to a target communication task and a target perception task according to the determined task feature data corresponding to the target communication task and the target perception task; and executing the target communication task and the target sensing task based on the subframe proportion and the preset signal transceiving parameter. And according to the determined target communication data and target sensing data, performing data analysis to obtain a data analysis result. According to the technical scheme, efficient cooperative work of the communication task and the sensing task can be achieved, the resource utilization efficiency is improved to a great extent, and hardware redundancy is greatly reduced. According to the technical scheme, the coordination capability and flexibility during cooperative work of the communication task and the sensing task are enhanced, and resource configuration and system performance are optimized. According to the technical scheme, the accuracy of the sensing task execution process and the sensing task data is effectively improved, and then the accuracy and practicability of a data analysis result are remarkably improved.

The invention relates to an improved systolic array computing device capable of improving pipeline efficiency, the device comprises an input characteristic value cache array, a multiply-accumulate array and an output characteristic value cache array, and the multiply-accumulate array is composed of N * N multiply-accumulate units. In order to improve the utilization rate of the array, data paths connected end to end are added in the horizontal direction and the vertical direction respectively, so that the array forms a Torus annular interconnection structure; input characteristic values are injected through diagonal positions, partial sum results are annularly accumulated in the vertical direction, so that continuous flow of input and partial sum is achieved, the structure remarkably reduces assembly line filling and emptying delay, hardware redundancy caused by input and output FIFO arrays in a traditional systolic array is avoided, calculation of a 512 * 512 matrix through a 256 * 256 array is taken as an example, and the structure has the advantages of being simple in structure, convenient to operate and low in cost. The calculation delay is reduced from 2560 clock cycles to 2176 clock cycles, and the array utilization rate is improved to 94%. The method has the advantages of being high in efficiency, low in cost, good in expansibility and suitable for neural network and matrix calculation acceleration.

The invention discloses a busbar differential protection capacity expansion method and system and a storage medium, and belongs to the technical field of power system relay protection. The method is applied to a double-bus wiring system configured with two sets of redundant bus differential protection devices, and the core is a differential transformation scheme: firstly analyzing hardware configuration and branch distribution conditions of the two sets of devices, directly adding a branch to a device with spare resources, and accessing a newly-added main transformer interval; and for the device with the full branches, the access position is vacated by adjusting the branch distribution of the existing incoming line interval and the main transformer interval. In the construction process, short circuit is carried out first and then reconnection is carried out to guarantee the safety of a current loop, and hardware wiring optimization, protection program upgrading and function verification are matched to complete transformation. The corresponding system comprises the bus differential protection device transformed by the method, and a computer readable storage medium for storing a program upgrading step. The whole set of equipment does not need to be replaced, the existing hardware redundancy expansion function is utilized, the modification cost is low, the safety risk is small, and the flexibility is high.

The invention relates to the technical field of power electronic conversion, and discloses a power conversion circuit and a UPS (Uninterrupted Power Supply) system, which realize an AC / DC (Alternating Current / Direct Current) rectification function in a mains supply mode and a DC / DC boosting function in a battery mode on a single set of hardware through innovative circuit design and device multiplexing on the premise of not obviously increasing hardware cost, and further realize a power conversion function in a battery mode. The system structure is simplified, the cost is reduced, and the power density is improved. According to the design, the multifunctionality of the existing device is fully utilized, and the problems of hardware redundancy and cost increase are avoided. Meanwhile, as the number of devices and the circuit complexity are reduced, the reliability of the system is improved, and the maintenance difficulty is reduced. Besides, due to the improvement of the power density, the whole power conversion circuit can support higher power output under the same size, or more compact design can be realized under the same power requirement, and powerful support is provided for integration and miniaturization of medium-power UPS power supply equipment.

The utility model relates to a kind of low-pressure four-axis robot hardware circuit, comprising: core board, mainboard, drive board, safety relay, switching power supply and AC contactor;The core board is connected with the mainboard, the mainboard is connected with the drive board, and the mainboard is connected with safety relay by relay control line, and the safety relay is connected with the AC contactor by contact control line, and the AC contactor is connected with the drive board by switching power supply;The core board, mainboard and drive board constitute electronic circuit part, optimize the controller multi-core heterogeneous computing architecture, realize software and hardware collaborative processing, provide powerful computing power for controller;With modularization thought design relevant PCB, guarantee the multiplicity of PCB;Using safety relay and AC contactor designs double-loop structure, through hardware redundancy, real-time monitoring and high-level safety certification, complete fault tolerance to single point is realized, while giving consideration to quick response and maintainability.

The invention discloses a design method for improving radar reliability based on FMECA. The method comprises the steps of dividing a system FMECA agreed level, a fault criterion and a severity level; aiming at antenna transceiving, servo control, information processing, control and display function faults, a scheme is selected to improve the reliability, and an analog simulation test is carried out to verify the effect; radar hardware design key points are determined, and low-power-consumption design and hardware redundancy design measures are adopted; radar software design key points are determined, the problems of deep coupling and large-area crash of software and hardware are solved, and health management software is designed to realize task migration and reconstruction; according to the process FMECA data of the existing product, obtaining the process failure mode, reason, severity grade and detected difficulty information, carrying out a reliability enhancement test, exciting and exposing the process defect in the module processing process, and adopting a corresponding improvement scheme in the processing process; in the testing and using process, FMECA iteration is carried out, and the radar reliability is improved.

The invention discloses a hydraulic station full-link dual-software-hardware redundancy control system which is characterized by comprising dual-software-hardware redundancy and a redundancy control switching mechanism, the dual-software-hardware redundancy comprises two sets of hardware, and the two sets of software can be switched mutually during use; the dual software and hardware redundancy comprises sensor redundancy, data acquisition module redundancy, control module redundancy, control mechanism redundancy, human-computer interface redundancy, data storage redundancy and communication redundancy; the redundancy control switching mechanism comprises a switching execution mechanism and switching arbitration logic, whether switching is carried out or not is judged according to the switching arbitration logic, and dual software and hardware are switched through the switching execution mechanism. The invention provides a first dual-channel software and hardware deep redundancy architecture covering full links of perception-decision-execution-man-machine interaction-storage, and solves the core problem of undisturbed switching of hydraulic control.

The invention designs a redundant fault-tolerant control system and control method for a distributed drive-by-wire chassis, and the system achieves the high-reliability operation of a whole drive-by-wire chassis system through the multi-level redundant design including power subsystem redundancy, dual-controller hot backup redundancy and four-corner module independent control mutual redundancy in combination with a degradation fault-tolerant mechanism. The system comprises components such as DCDC, a low-voltage storage battery, double controllers, four distributed corner modules and various sensors, corresponding fault diagnosis and safety control strategies are configured, and the core of the system is that through collaborative design of hardware redundancy and software fault tolerance, it is ensured that the system can still maintain basic safety functions under the condition that one or more components have faults, and the system is safe and reliable. And the safety and the reliability of the drive-by-wire chassis are obviously improved.

The invention discloses a forklift electronic control hardware redundancy system, and relates to the field of forklift control. Comprising a main control module which processes a driving instruction and sensor data in real time, generates an execution mechanism control signal and synchronizes parameters to a standby module through a high-speed bus; the standby control module realizes non-inductive control right takeover through a dynamic thermal synchronization method when the main system fails; the multi-channel fault detection module is used for carrying out fault detection on system operation through the sensor module, and the arbitration switching module is used for carrying out control switching after the multi-channel fault detection module detects a system fault. The failure state of the main control channel is accurately judged on the basis of parameters calculated in real time, the control right is switched to the standby module in an undisturbed mode through the arbitration switching module, the fatal defect that a traditional system is shut down when a fault occurs is broken through, a forklift is kept in a continuous controllable state under sudden faults such as controller short circuit and signal distortion, and the system reliability is improved. And the systematic collapse risk of a single channel architecture is fundamentally eliminated.

The invention relates to a multi-thread parallel redundancy fault-tolerant method based on a compilation layer. The invention relates to the technical field of embedded processor design. The method comprises the following steps: determining thread division and an SoR region core; packaging an SoR region related fault-tolerant function library, packaging a core fault-tolerant function into a header file, and ensuring that a library file contains a tool function strongly associated with the SoR region; matching the compiler with the tool chain; marking and automatically identifying the source program; automatically identifying and supplementing the ROSE compiler; compiling the SoR region and generating a dual-thread code; performing double-thread parallel execution and check point interaction; and redundant fault-tolerant processing and flow continuation are carried out. The method does not depend on a specific hardware platform, and the problem of poor portability of a traditional hardware redundancy technology or a fault-tolerant technology depending on a specific hardware architecture is effectively avoided.

The invention relates to a power supply current detection method based on a BMS system, and relates to the technical field of battery management systems, current sensors are configured at the positive electrode input end and the negative electrode output end of a battery respectively to construct hardware redundancy, and the method comprises the following steps that the reading Ipos of the positive electrode current sensor and the reading Ineg of the negative electrode current sensor are collected in real time and preprocessed; respectively carrying out validity judgment on the preprocessed Ipos and Ineg and a preset normal working current range [Imin, Imax]; according to the validity judgment result, multi-mode arbitration is carried out based on a fault-safety principle, and one of a single-sensor failure mode, a double-sensor consistent mode, a double-sensor conflict mode and a double-sensor failure mode is automatically selected; and outputting the final system current value Ifinal for SOC estimation, thermal management and / or power control of the BMS. According to the method, the problem that the system is out of control possibly caused by failure of a single-point sensor or data conflict of double sensors in the existing BMS current detection technology is solved.

The invention relates to the technical field of vehicle-mounted communication, in particular to an FSI and SOC data interaction method and device, equipment and a medium, and the method comprises the steps: judging whether a current XCPLink module receives a request message sent by an upper computer or not; if the current XCPLink module receives the request message, determining the type of the request message; and performing data interaction between the FSI and the SOC according to the type of the request message based on the preset shared memory area. Therefore, the problems of hardware redundancy, function security limitation, insufficient real-time performance and high cost existing in communication between the cross-function security island and the SOC module in the existing XCP technology are solved, efficient XCP communication between the FSI and the SOC module is realized through a shared memory mechanism, external access to an FSI hardware link is avoided, the function security requirement is met, and the system performance is improved. And meanwhile, cross-hardware compatibility and expandability are improved, and high safety and reliability are achieved.

The application relates to the field of computer storage, and discloses an FPGA-based SSD controller verification method and system, which aims to solve the problems of hardware redundancy, non-systematic verification and poor flexibility of a verification scheme in a high-integration board card environment. Technical solution points: the verification method is divided into three stages, that is, first, a hardware environment is constructed through FPGA integration verification, then, basic functions and performance are tested through data disk verification, and finally, system-level testing and version solidification are completed through system disk verification; the verification system comprises a host computer and an integrated board card, and an FPGA module integrates an SSD controller and network interface function logic. The application does not require additional hardware, realizes low-cost and systematic comprehensive verification, and is suitable for function and performance verification of an SSD controller in a high-integration board card environment.

The invention discloses a redundancy control circuit and method for a passive relay protection device, and belongs to the technical field of relay protection, and the control circuit comprises a current sampling loop, a main control chip, and a hardware redundancy overcurrent protection system. Wherein the current sampling loop is used for converting a three-phase current of a power grid into a sampling voltage signal and respectively inputting the sampling voltage signal into the main control chip and the hardware redundancy overcurrent protection system; the main control chip is used for realizing software protection of a power grid according to an input sampling voltage signal; and the hardware redundancy overcurrent protection system is used for realizing hardware redundancy protection of the power grid according to the input sampling voltage signal. According to the invention, based on the existing software protection process of the relay protection device, a redundant hardware protection loop is additionally designed, so that when a line fails, a software system can be effectively prevented from downtime.

The invention discloses an automatic test system for safety PLC module production, and relates to the technical field of safety PLC production test. The system comprises an industrial all-in-one machine, a signal source control device and extensible peripheral test equipment, supports interaction with an MES server system, and can realize full-process automatic test of a to-be-tested safety PLC card. Parameter configuration and data management are completed through the industrial all-in-one machine, it is guaranteed that test data are locally stored and uploaded to the MES server, the traceability of the test data is guaranteed, and the signal source control device designs special tests of time-sharing automatic burning, redundant channel isolation testing and fault simulation according to the characteristics of hardware redundancy, self-diagnosis and the like of the safety PLC. Test automation, coverage comprehensiveness, data traceability and process flexibility are realized in the production of the safety PLC module, the test efficiency and the product quality are remarkably improved, and the method is suitable for a large-scale production test scene of an industrial-grade safety PLC.

The invention discloses a Flash starting system and method based on a trusted measurement mechanism. The Flash starting system and method are suitable for starting scenes of main and standby Flash memories of domestic CPUs (central processing units). The system comprises a domestic CPU (central processing unit), a CPLD (complex programmable logic device), a TPCM (trusted platform control module), a main Flash memory, at least one standby Flash memory and a GPIO (general purpose input / output) signal line. And the CPLD expands a single-path SPI interface of the CPU into multiple paths through logic programming, and is connected with the main Flash and the standby Flash to realize intelligent switching. The TPCM performs trusted measurement on the boot firmware of the main and standby Flash memories after the system is powered on, so that the integrity of the boot firmware is ensured. And during starting, loading is preferentially carried out from the main Flash memory, and if the loading fails, the standby Flash memory is automatically switched to, so that the starting reliability and stability of the system are improved. Through combination of hardware redundancy and trusted measurement, malicious starting of firmware loading is effectively prevented, and safe and stable operation of the system is guaranteed.

This invention discloses a server PCIe resource adaptive configuration method, relating to the fields of server architecture and PCIe high-speed bus configuration technology. Addressing the problems of existing solutions such as reliance on custom BIOS development, timing incompatibility, lack of resource arbitration, inability to dynamically optimize, and operational redundancy, this invention adopts a fully hardware-coordinated architecture of the motherboard and component-side CPLD. It completes time-division reporting of topology data and four-level hardware trusted verification through the native sideband channel of the UBC cable. Through hardware-based resource conflict arbitration and cross-CPU platform register conversion, the configuration table is generated and locked before BIOS PCIe initialization. Simultaneously, it supports OS runtime load monitoring, incremental bandwidth adjustment, and hot-swappable adaptive configuration, combined with parallel cable status alarms and automatic fault rollback mechanisms. This invention eliminates reliance on custom BIOS, is compatible with standard power-on timings, improves configuration stability and resource utilization in complex scenarios, reduces hardware redundancy and operational costs, and is applicable to general server PCIe resource adaptive management.

The invention discloses a heating system, a server and a heating method, and relates to the technical field of computers, and the heating system comprises a temperature monitoring assembly which is used for monitoring the first case temperature of a target server; the control assembly is used for sending a heating starting signal to the heating assembly when the first case temperature is lower than a first preset temperature and sending a first heating stopping signal when the first case temperature is higher than a second preset temperature; the heating assembly is used for entering a heating state after receiving the heating starting signal and stopping heating after receiving the first heating stopping signal; the redundancy control part is used for monitoring the second case temperature of the target server, and when the second case temperature is larger than the third preset temperature and the heating assembly is in the heating state, a power-off safety instruction is sent to the power management assembly, and power supply to the heating assembly is cut off. Therefore, by introducing a hardware redundancy control mechanism independent of the main control system, the problems that a heating circuit continuously works and equipment is overheated and damaged due to failure of software and hardware of a control assembly are solved.