Method for testing SOC (System On Chip) based on reference vector and bit mask

A technology of reference vector and test method, applied in the direction of measuring electricity, measuring device, measuring electrical variables, etc., can solve the problem of low compression rate, etc., and achieve the effect of high compression efficiency

Active Publication Date: 2012-02-15
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] The present invention aims to solve the problem of low compression rate in existing test metho

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  • Method for testing SOC (System On Chip) based on reference vector and bit mask
  • Method for testing SOC (System On Chip) based on reference vector and bit mask
  • Method for testing SOC (System On Chip) based on reference vector and bit mask

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specific Embodiment approach 1

[0040] Specific implementation mode one: combine figure 1Describe this embodiment, the specific steps of the SOC test method based on reference vector and bitmask in this embodiment are:

[0041] Step 1: Compress the test data corresponding to the circuit;

[0042] Step 2: transmit and store the compressed data on ATE;

[0043] Step 3: Decompress the compressed data through the decompression structure on the chip, and restore it to test data;

[0044] Step 4: Test the IP core with test data.

[0045] The compression process of Step 1 is as follows:

[0046] Step 11: arrange the test data corresponding to the circuit in the form of multiple scan chains to obtain multiple test segments;

[0047] Step 1 and 2: Carry out group division for all test segments, and then select the test segment with high frequency in the group after division according to the capacity of the allocated dictionary in the hardware as a dictionary entry;

[0048] Step 13: According to the frequency of...

specific Embodiment approach 2

[0052] Specific embodiment 2: the feature of this embodiment is that in step one of specific embodiment 1, the method of arranging the test data corresponding to the circuit into test segments according to the form of multiple scan chains is: set the test data corresponding to the circuit as a test set T D , consisting of n vectors, respectively t 1 , t 2 , t 3 ,...,t n , the number of scan chains in the IP core is m, each test vector is divided into m groups on average, and each group contains d-bit data, if the number of bits of each test vector is Ntotal, d=Ntotal / m, if a certain group of data If the length is less than d, fill it up with the uncertain bit "X", combine the jth data of all test vectors together to form a scan chain, j=1, 2,..., m, the kth bit of all scan chains grouped together to form the kth test segment.

[0053] When the test set T D When n=2, m=3, and d=6, the process of arranging test segments in the form of multiple scan chains is as follows f...

specific Embodiment approach 3

[0054] Specific embodiment three: the characteristic of this embodiment is, the method for carrying out group division to test segment in the step one two of specific embodiment one is:

[0055] Step a: establish an undirected graph G=(V, E) for the test segment, wherein V is a vertex set, and E is an edge set; the test segment without an edge in the undirected graph is encoded using a bit mask, so that the test segment connected to vertices with edges;

[0056] Step b: Search for the point with the largest degree in the undirected graph, if the largest point is unique, execute step d; if the largest point is not unique, execute step c;

[0057] Step c: Select the vertex with the least irrelevant bits X as the point with the largest current degree;

[0058] Step d: use all the vertices connected to the current maximum degree vertex to establish a subgraph H;

[0059] Step e: Search the subgraph H, obtain the vertex pair with the most common neighbors in the subgraph H, if no...

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Abstract

The invention discloses a method for testing an SOC (System On Chip) based on a reference vector and a bit mask, relating to a method for testing the SOC and solving the problem of lower compression rate when the traditional testing method s used for testing an IP core. The method comprises the steps of: 1, compressing test data corresponding to a circuit; 2, transmitting compressed data and storing in ATE (Automatic Test Equipment); 3, decompressing the compressed data through a decompression structure on a chip, reducing into test data; and 4, testing the IP core by using the test data. Themethod has high compression efficiency higher than that of the similar products by above 20 percent, has no additional hardware redundancy, and is used for testing the SOC based on a reusable IP coredesign.

Description

technical field [0001] The invention relates to a method for testing SOC. Background technique [0002] With the gradual improvement of the integrated circuit manufacturing process, more and more IP cores (Intellectual Property) are integrated on a chip. The complexity of SOC has risen sharply, and at the same time it has brought many new challenges to SOC testing. Among them, the test time is long, the amount of test data is large, and the test power consumption has become the three major problems that need to be paid attention to in the SOC test. [0003] Since the SOC is usually composed of reusable IP cores, the structure information of the IP core is not required to encode the test vectors, and the test compression technology can achieve good results in reducing the amount of test data and test time. In the traditional data stream form of data compression and decompression, the data compression part is done in advance, and the decompression circuit is realized on the ...

Claims

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Application Information

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IPC IPC(8): G01R31/3185
Inventor 俞洋乔立岩彭宇陶丽楠向刚
Owner HARBIN INST OF TECH
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