Design method of scanning unit based on partial scanning of improved test vector set

A technology of test vectors and scanning units, applied in the direction of measuring electricity, measuring devices, measuring electrical variables, etc., can solve problems such as hardware redundancy and large memory capacity, reduce storage space, reduce hardware redundancy, and facilitate test compression and the effect of vector generation

Inactive Publication Date: 2012-01-18
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] In order to solve the problems of test delay, hardware redundancy and required memory capacity in the existing online te...

Method used

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  • Design method of scanning unit based on partial scanning of improved test vector set
  • Design method of scanning unit based on partial scanning of improved test vector set
  • Design method of scanning unit based on partial scanning of improved test vector set

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Experimental program
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specific Embodiment approach 1

[0064] Specific Embodiment 1: In the design method of the scanning unit based on partial scanning of the improved test vector set described in this embodiment,

[0065] Firstly, the important equivalent output pins that are important for fault detection are obtained by using the method of fault simulation on the equivalent output pins of the sequential circuit combination;

[0066] Then, the improved test vector set is obtained by simulating the faults of the equivalent input pins of the sequential circuit combination;

[0067] Finally, according to the improved test vector set and the equivalent output pins that are not important for fault detection, the flip-flops are divided into fixed-input flip-flops and important flip-flops, and the important flip-flops are connected in series to form a partial scan chain.

[0068] The given input flip-flops are don't care flip-flops, 0 don't care flip-flops and 1 don't care flip-flops.

[0069] The method of carrying out fault simulati...

specific Embodiment approach 2

[0102] Specific Embodiment 2: This embodiment is a further description of the important triggers described in Specific Embodiment 1. image 3 with Figure 9 This embodiment will be described.

[0103] The important trigger 1 in this embodiment includes a first selector 1-1, a second selector 1-2, a third selector 1-3, a fourth selector 1-4, a test trigger 1-5 and a function triggers 1-6,

[0104] The input signal of the enable terminal of the first selector 1-1 is mode[1], the input signal of the enable terminal of the second selector 1-2 is mode[0], and the input signal of the enable terminal of the third selector 1-3 The signal is mode[0], and the input signal of the enable terminal of the fourth selector 1-4 is mode[1];

[0105] The 0 input terminal of the first selector 1-1 is used as the test unit scan data input terminal of the important flip-flop 1, and the test scan data SI is input, and the 1 input terminal of the first selector 1-1 is connected with the second sel...

specific Embodiment approach 3

[0147] Specific Embodiment 3. This embodiment is a further description of the irrelevant trigger described in Specific Embodiment 1. Refer to Figure 12 As shown, the irrelevant flip-flop described in this embodiment is composed of a selector and a D flip-flop, the 0 input end of the selector is connected to the data output end of the D flip-flop, and the data output end of the selector is connected to the D flip-flop The data input end of the D flip-flop is the data output end of the irrelevant flip-flop.

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Abstract

The invention discloses a design method of a scanning unit based on partial scanning of an improved test vector set, relating to the technical field of SOC (system-on-a-chip) test of digital integrated circuits, and solving the problems of delayed test, hardware redundancy and large required capacity of a memory in the conventional online test method. The method comprises the following steps of: firstly, obtaining an important equivalent output pin which is important to fault detection by stimulating a fault of an equivalent output pin in a combined part of a sequence circuit; secondly, obtaining the improved test vector set by stimulating a fault of an equivalent input pin in the combined part of the sequence circuit; and finally, according to the improved test vector set and an equivalent output pin which is unimportant to the fault detection, dividing triggers into fixed-input triggers and important triggers, and serially connecting the important triggers to form a partial scanningchain. By the method, the obtained scanning unit has a relatively high fault coverage rate and can reduce the hardware redundancy of a test circuit, the digit of bits of the test vector and the memory space.

Description

technical field [0001] The invention relates to the technical field of SOC testing of digital integrated circuits, in particular to the technical field of SOC testing of reusable IP (Intellectual Property) cores. Background technique [0002] With the improvement of integrated circuit technology, a complex system composed of multiple chips can be integrated on one chip, and the system-on-a-chip (SoC) emerges as the times require. With the increasing demand for chip reliability, SoC testing technology has been extensively studied. [0003] SoC testing can be divided into offline testing and online testing. In-circuit testing refers to physical fault detection while the circuit is running. The main reasons why online testing is becoming more and more important are as follows: [0004] First of all, in key areas with high safety requirements such as aerospace and military, it is necessary to complete the test while working; [0005] Second, online testing can ensure the max...

Claims

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Application Information

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IPC IPC(8): G01R31/3181G01R31/3185
Inventor 俞洋杨智明乔立岩王帅邓立宝王继业
Owner HARBIN INST OF TECH
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