1248 results about "Very large scale integrated" patented technology

A coolerless photonic integrated circuit (PIC), such as a semiconductor electro-absorption modulator/laser (EML) or a coolerless optical transmitter photonic integrated circuit (TxPIC), may be operated over a wide temperature range at temperatures higher then room temperature without the need for ambient cooling or hermetic packaging. Since there is large scale integration of N optical transmission signal WDM channels on a TxPIC chip, a new DWDM system approach with novel sensing schemes and adaptive algorithms provides intelligent control of the PIC to optimize its performance and to allow optical transmitter and receiver modules in DWDM systems to operate uncooled. Moreover, the wavelength grid of the on-chip channel laser sources may thermally float within a WDM wavelength band where the individual emission wavelengths of the laser sources are not fixed to wavelength peaks along a standardized wavelength grid but rather may move about with changes in ambient temperature. However, control is maintained such that the channel spectral spacing between channels across multiple signal channels, whether such spacing is periodic or aperiodic, between adjacent laser sources in the thermally floating wavelength grid are maintained in a fixed relationship. Means are then provided at an optical receiver to discover and lock onto floating wavelength grid of transmitted WDM signals and thereafter demultiplex the transmitted WDM signals for OE conversion.

Methods, and structures formed thereby, are disclosed for forming laterally grown structures with nanoscale dimensions from nanoscale arrays which can be patterned from nanoscale lithography. The structures and methods disclosed herein have applications with electronic, photonic, molecular electronic, spintronic, microfluidic or nano-mechanical (NEMS) technologies. The spacing between laterally grown structures can be a nanoscale measurement, for example with a spacing distance which can be approximately 1-50 nm, and more particularly can be from approximately 3-5 nm. This spacing is appropriate for integration of molecular electronic devices. The pitch between posts can be less than the average distance characteristic between dislocation defects for example in GaN (ρ=10¹⁰/cm²→d=0.1 μm) resulting an overall reduction in defect density. Large-scale integration of nanoscale devices can be achieved using lithographic equipment that is orders of magnitude less expensive that that used for advanced lithographic techniques, such as electron beam lithography.

An efficient computer implemented method computes critical area for via blocks in Very Large Scale Integrated (VLSI) circuits. The method is incremental and takes advantage of the hierarchy in the design. In order to increase the efficiency further we use the Linfin or the L1 metric instead of the Euclidean geometry.

A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.

An application adapted to run within an enterprise wide, web-based framework which provides reusable services and facilities such as security, meta-data management and traceability of data and a framework supporting the same. The framework supports decision making across the value chain, with an emphasis on the meta-data needed for decision making. The framework can support the activities of a virtual organization (internal or external) and the inevitable variations in data types, file formats etc. without requiring massive integration between the various sources of data involved.

The invention discloses a soft starting circuit for a pulse width modulation DC-DC switch power, comprising a frequency splitting count module, a current threshold module, a current sampling module, a current limiting comparator, a two input or-gate, an oscillator and an RS trigger. The current in a power inductance is sampled when an external switch rectifier is conducted, and the current changes from small to big by stage by limiting the peak value of the current so as to control the step change of the duty ratio, thus leading the output voltage to increase by stage gradually, avoiding surge current in starting procedure and realizing the soft starting function. The invention has the advantages of integrating to the inside of large scale integrated circuit without high capacitance in the outside or a microcontroller to control, limiting the load current directly with good soft starting effect and being suitable for a voltage control mode and a current control mode; the circuit is simple correspondingly by adopting a current gating network; the soft starting time can be regulated automatically according to different loads.

Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/output buffer which can be adapted to several input/output levels, a dynamid RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.

The invention relates to a fault simulation system and a fault analysis method for single event upset in a large scale integrated circuit SRAM-type FPGA (Field Programmable Gate Array). The fault simulation system comprises a host computer and a control board, wherein the control board comprises a fault injection module, a fault detecting module and a fault analyzing module. The fault simulation system and the fault analysis method provided by the invention are flexible to use, low in cost, high in simulation precision, fast in simulation speed and free from any physical damage to a chip.

A method, system, and apparatus for improved IC device packaging is described. In an aspect, an (IC) device package includes an IC die having at one or more contact pads, each contact pad located at a corresponding hotspot on a surface of the IC die. The package also includes a thermally conductive interposer which is thermally coupled to the IC die at the contact pads. In another aspect, an underfill material fills a space between the IC die and the interposer. The interposer may also be electrically coupled to the IC die. In an aspect, the interposer and the IC die are coupled through thermal interconnects or “nodules.”

The invention relates to a Cu-Al2O3 nanometer dispersion strengthening alloy and preparation thereof. The preparation includes the steps of Cu-Al alloy vacuum smelting, pulverizing, screening, internal oxidizing, hydrogen reducing, vacuum hot pressing, canned hot extruding, etc. Comparing with oxygen-free copper, sigma of the alloy of the invention is 2 to 6 times higher that of the oxygen-free copper, the anti-annealing softening temperature is up to over 900 DEG C, the conductivity is up to 96% IACA and more. The process of the invention is simple, the prepared Cu-Al2O3 nanometer dispersion strengthening alloy has high strength, high conductivity, electrical conductivity higher than 96% IACA, and is anti-annealing and antimagnetic. The alloy can not only used for large-scale integrated circuit lead frame, manufacturing of controlled thermonuclear reaction heat sink components, and is expecially suitable for manufacturing of microwave tube grid mesh, inertial instrument sensor, particle accelerator and other high-precise parts.

This invention discloses a large scale integrated hospital information system including a hospital information management system HIS, an electronic case history system EMR, an image transmission and storage system PACS, a check network information system LIS and an office automation system HOS, a combined enquiry and analysis system, a manpower resource management sub-system and a foreign information interface and exchange part, in which, all systems are connected by exchanges to transmit information. This invented device applies at least two stages of exchange structure and a server cluster mode fiber to connect to the floors, and the server includes an IBM520 optical channel disc array small computer, an IBM365 optical channel disc array double heat-standby server, an IBM 440 disc array double motor heat-standby server, a PACS cluster load balance server set and a WEB server.

A temperature controlling apparatus determines a fan rotation speed from a surrounding noise and a fan noise, measures a temperature of a large scale integration (LSI) device or the like that is a controlled object, determines, in a cooling capacity range of the determined fan rotation speed, an operating clock frequency that falls within an allowable temperature range, and controls the LSI to be connected.

The present invention provides a spread spectrum clock generator that is capable of preventing phase jumps and jitters and suppressing the occurrence of Electro Magnetic Interference components and that can easily be applied to large scale integrated circuits. The spread spectrum clock generator can be configured with a filter, quantizer, fractional divider, and other elements. Also, this clock generator circuitry can be configured by combination of a delta-sigma ΔΣ quantizer and factional divider so that sine wave modulation and random number modulation can be realized. Thereby, control with digital values can be performed. This clock generator prevents precipitous phase variations in the output high frequency clock and makes fine phase control possible. Consequently, EMI reduction by 20-30 dB can be expected.

This invention discloses a baseband signal processing method for GNSS receivers, particularly for common ranging-code signal for GNSS receiver, completing: the baseband signal catching, the tracking processing within frequency domain, easily for realization in large scale integrated circuit. During the signal catching step, FFT and IFFT calculation method is used for grouped calculation to simplify the time-domain related calculation. During the code-tracking, thus obtained related peak positions are found, then precision est1 mate of code phase is fulfilled by utilizing curve-fitting method. During the carrier tracking, DFT values of these points is calculated by using sliding DFT method, after the DFT point values ranges are determined based on rough carrier frequency estimate, and then proceeding estimate of carrier frequency, data demodulation by using IFFT output result.

The present invention discloses a multi-carrier digital multimedia broadcast system and the digital information transmission method thereof. After RS encoding and byte interleaving, LDPC encoding, bit interleaving and constellation mapping to an upper layer of data streams in turn, the obtained data symbol is multiplexed with scattered pilots and continual pilots which include the system information to form an OFDM frequency domain symbol and scrambled; an OFDM time domain symbol is generated by IFFT transforming, and after inserted with the frame head to build a time slot, it is connected to form a signal frame of the physical layer; the signal frame of the physical layer is transmitted after being low-pass filtered and orthogonal upconverted. The system and method thereof provide wireless broadcast with high quality such as audio, video and multimedia data and the like for mobile, fixed and portable receivers, and can use the satellite transmission and terrestrial transmission method for transmitting. The method utilizes the LDPC OFDM scheme, and the system applies the microwave and large scale integrated circuit technologies while fulfills the needs for low cast and high performance.

The invention discloses a graphene reinforced lead-free solder, which comprises, by weight parts, graphene and lead-free solder base body of the ratio of 0.75-1.75:50000. The preparation method includes: by means of process of powder metallurgy, disposing the graphene into absolute ethyl alcohol according to proportion, vibrating ultrasonically, milling and drying the absolute ethyl alcohol with the graphene, mixing and stirring the absolute ethyl alcohol and the lead-free solder base body, pressing the same into a blank, sintering the blank at the temperature of 175 DEG C under the protective atmosphere of high-purity argon, extruding the same into a bar with the diameter of 6mm, and preparing the graphene reinforced lead-free solder. The graphene reinforced lead-free solder can meet the requirements of environmental protection and reliable welding, substitutes for conventional stannum-lead solder, has higher and more reliable mechanical performance than lead-free solder in the prior art, can be used as connection materials for oversized integrated circuits and is a composite material according with development trends of the modern electronic industry.

An efficient method to compute critical area for shorts and breaks in rectilinear layouts in Very Large Scale Integrated (VLSI) circuits. The method is incremental and works in the L INFINITY geometry and has three major steps: Compute critical area for rectilinear layouts for both extra material and missing material defects (i.e., shorts and opens) by modeling defects as squares (which corresponds to the L INFINITY metric) instead of circles (Euclidean geometry). Treat the critical region for shorts and opens between any two edges or corners of the layout as a rectangle that grows uniformly as the defect radius increases. This is valid for rectilinear layouts and square defects (L INFINITY metric) . Use an incremental critical area algorithm for shorts and opens, which are computed for rectilinear layouts assuming square defects. Non-rectilinear layouts are approximated, first, by a rectilinear layout using a shape processing tool. The critical area for the rectilinear approximation is computed using the preferred incremental method.

An epoxy resin mold plastic and its production are disclosed. The mold plastic consists of liquid-crystal epoxy resin, methyl-phenolic epoxy resin, epoxy resin containing biphenyl unit structure, melamine modified linear phenolic resin, silicone micro-powder, imidazo curing improver, toughening agent and silane coupling agent. The process is carried out by treating silicone micro-powder in mixer by coupling agent for 2-5mins, adding into other components, mixing for 3-5mins, melt milling at 95-135 degree for 3-5mins, cooling, crushing, mesh screening, pressing into material cake and storing below 6degree. Its advantages include low thermal expansion coefficient, excellent heat and fire resistances, better toughness and fluidity, no phosphor, no antimony and environmental pollution. It can be used to pack large-scale circuit and electronic devices.

The invention discloses a metal etching device and method which can be used in a large-scale integrated circuit industrial manufacturing environment. Particularly, by means of the metal etching device and method, in a vacuum uninterrupted environment, magnetic tunnel junctions of a magnetic random access memory (MRAM) are subjected to etching and etching post-processing in a reactive-ion plasma etching chamber and an ion beam etching chamber and then subjected to coating surface protection in a coating chamber, so that the side wall of the magnetic tunnel junctions are free of metal contamination after being etched, the chemical and physical structures of the magnetic tunnel junctions are consistent with the chemical and physical structures before etching, the magnetic tunnel junctions can be taken out from etching equipment and not destroyed by the air environment, and the yield of MRAM devices is effectively increased. In addition, the metal etching device and method are also applicable to etching of resistive random access memories and other metals.

The invention relates to a composite micro-alloying copper alloy with high strength and high conductivity, containing micro chromium, zirconium and tellurium, and a preparation method thereof. The alloy is prepared from the following components in part by weight: 0.2-0.8 Cr, 0.1-0.3 Zr, 0.1-0.5 Te and the balance of Cu. The preparation method comprises the steps as follows: component preparation; melting; ingot preparation by semi-continuous casting; casting ingot homogenization; hot rolling; solid solution heat treatment; cold rolling; and aging treatment. The finished copper alloy with high strength and high conductivity are superior to prior similar alloy in comprehensive properties, wherein the tensile strength is 500 MPa, the conductivity is 92% IACS, and the thermal conductivity coefficient is 391cm amplitude. The alloy material of the invention can be used as contact alloy material, electrified railway contact net conductors and fittings thereof, large-scale integrated circuit lead frame material, crystallizer material and the like.