206 results about "Very large scale integrated" patented technology

The invention relates to the technical field of chip development, and discloses a chip post-simulation verification acceleration method, system and device and a storage medium, and the method comprises the steps: collecting multi-dimensional data of a large-scale chip; collecting all module names of a given chip; establishing a mapping relation between a redundant module RTL and a corresponding gate-level netlist, ensuring that interfaces before and after replacement are completely consistent, and designing an automatic script identification and processing parameterization module; establishing a post-simulation verification environment, verifying the consistency of output responses before and after replacement, analyzing the time delay change of a key path, calculating the dynamic power consumption and static power consumption of each functional module before and after replacement, and generating a simulation verification result. According to the method, the hybrid simulation model is constructed, and part of the gate-level netlist irrelevant to the current simulation function is replaced with the RTL, so that the actual simulation scale of a chip is reduced, the problem of overlong simulation time after a large-scale integrated circuit is remarkably solved, and the simulation efficiency is effectively improved.

The invention discloses a clock tree synthesis method and system based on clustering, and the method comprises the steps: carrying out the preliminary grouping of registers through employing a K-means clustering method, generating the position of a first-stage buffer under the condition that the maximum fan-out number limitation constraint, the maximum RC constraint and the position overlapping constraint are satisfied, and generating a second-stage buffer based on the position, and then constructing a subsequent clock tree by adopting a DME algorithm. The problem of clock signal distribution in large-scale integrated circuit design is solved, clock delay, clock skew and the number of buffers can be reduced, and the comprehensive quality of the clock tree is improved.

The invention discloses a VLSI circuit layout optimization method and system based on deep learning in the technical field of integrated circuits, and the method comprises the steps: abstracting a large-scale integrated circuit into a hypergraph structure, receiving the hypergraph structure, generating a node embedding matrix through a hypergraph neural network, and optimizing a segmentation loss function through unsupervised training, obtaining a probability distribution matrix, determining segmented subsets based on the probability distribution matrix, mapping each subset to a physical layout unit, generating a physical region layout of the chip according to an area equilibrium constraint and a time sequence constraint, performing constraint feedback on a physical layout result, and dynamically adjusting parameters of the segmentation loss function. The method can be used for circuit layout of a super-large-scale integrated circuit, and an optimization method and means are provided for providing a high-quality VLSI circuit layout scheme.

The invention discloses a visible infrared dual-band stealth material and a preparation method thereof. The material structurally comprises a metal Mo layer, a Ge dielectric layer and an Al2O3 dielectric layer, and the metal Mo layer, the Ge dielectric layer and the Al2O3 dielectric layer are sequentially laid from bottom to top. According to the method, the absorptivity, the refractive index and the transmittance of the thin film structure in visible light and infrared bands are calculated through combination of a transmission matrix and simulation software, and simulated absorption spectrums of the thin film structure in the visible light and infrared bands under the normal incidence condition are obtained; by changing the thickness of each layer of material in the thin film structure, different thickness absorption spectrums of the thin film structure in visible light and infrared bands are obtained through calculation; comparing the different thickness absorption spectrums with the simulated absorption spectrums to obtain an optimal thin film structure and the thickness of each layer of material; and according to the thickness of each layer of material of the optimal thin film structure, a target thin film structure is prepared by setting a preparation mode. The structure is simple, the manufacturing process is simplified, and preparation and large-scale integration are easy.

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

The invention discloses an automatic batch interface connection method, which relates to the technical field of interface connection, and comprises the following steps: S1, confirming an input / output port; s2, parameterizing macro definition; s3, a connection code is generated; s4, generating interfaces in batches; and S5, carrying out batch connection. According to the method, automatic generation of batch interface connections is achieved through parameterized macro definition, the requirement for manual coding is reduced, the risk of human errors is reduced, the efficiency of the verification process is improved, a designer only needs to specify macro parameters in the configuration file, a large number of different interface connections can be rapidly configured, complex connection codes do not need to be written, and the method is convenient and fast to operate. The reusability of codes is enhanced through parameterized macro definition, the same macro definition can be repeatedly used in different items or different verification platforms, high flexibility is provided through the parameterized macro definition, interface connection is supported to be rapidly modified and adapted, and the large-scale integrated circuit design method and device can adapt to various complex scenes in the large-scale integrated circuit design process.

The invention discloses a combinational logic clustering optimization method and system based on reinforcement learning. The method comprises the following steps: S1, counting fan-out information of registers and combinational logic units in a circuit netlist; s2, according to the fan-out information, screening out registers and combinational logic units of which the fan-out quantity is greater than a first preset threshold and the worst time sequence path time sequence violation value of the output signal is smaller than a second preset threshold, and generating a target unit list; s3, acquiring fan-out combinational logic information of each unit in the target unit list; s4, on the basis of the fan-out combinatorial logic information, clustering operation is carried out on fan-out logic units on the basis of a reinforcement learning algorithm; s5, after logic clustering is completed, revising the netlist of the circuit; after the revision is completed, carrying out equivalence check; and S6, rearranging and wiring the circuit according to the modified netlist. The method can effectively reduce key path delay, optimizes circuit performance, and is especially suitable for large-scale integrated circuit design.

Embodiments of the present application provide an electronic device, a manufacturing method thereof and an electronic device, and relate to the technical field of semiconductors. The electronic device can be used for growing nanowires in a plane. The electronic device can include a substrate and at least one nanowire. The substrate has at least one groove. The nanowire is embedded in the groove. The groove has at least one groove wall. The nanowire extends along one groove wall of the groove and is in contact with the groove bottom. The groove wall has a guiding effect, so that the nanowire can grow in the plane of the groove bottom along the extension direction of the groove wall, which is conducive to large-scale manufacturing of the electronic device. The plane of the groove bottom can be parallel to the surface of the circuit board for carrying the electronic device. Therefore, when the nanowire grows in the plane of the groove bottom, it is conducive to large-scale integration of the electronic device on the circuit board.

The invention belongs to the technical field of computers and electronics, and discloses a graph neural network hardware Trojan detection method and system fused with an attention mechanism, and the method comprises the steps: S1, mapping a netlist circuit code carrying a hardware Trojan into a directed graph; s2, performing graph embedding, graph segmentation and graph sampling on the directed graph; s3, extracting inherent characteristics of the nodes through an encoder; s4, extracting node local features through a graph neural network; s5, extracting global features of the nodes through an attention mechanism model; and S6, carrying out feature fusion on the data inherent features extracted by the auto-encoder, the local structure features extracted by the bidirectional GCN convergence model and the global structure features extracted by the self-attention mechanism, and obtaining an HT detection result through a classification model. According to the method, the Trojan horse detection accuracy and efficiency are greatly improved; compared with an existing method, the detection range or type is expanded, and the method can be applied to hardware Trojan horse detection of a large-scale integrated circuit actually.

The invention discloses a digital circuit optimization method and system based on logic clustering. The method comprises the following steps: S1, counting fan-out information of all registers in a circuit netlist; s2, according to the fan-out information of the registers, screening out the registers of which the fan-out quantity is greater than a first preset threshold value and the logic series is greater than a second preset threshold value and which are located on the critical path, and generating a candidate register list; s3, obtaining register fan-out first-level combinatorial logic information; s4, performing clustering operation on the logic units based on the first-level combinational logic information, and dividing physically adjacent logic units into the same cluster according to the physical position relationship of the logic units; s5, associating the clustered logic units together and adjusting the connection relation of the logic units; s6, carrying out equivalence check; and S7, rearranging and wiring the circuit according to the modified netlist. The physical distance of a time sequence path can be effectively reduced, the time sequence performance of the circuit is optimized, and the method is suitable for large-scale integrated circuit design.

The invention provides a node of a network-on-chip, a data transmission method of the node and the network-on-chip. A node of the network-on-chip comprises a control module, and a plurality of input ports and a plurality of output ports in east, south, west and north directions; the control module is configured to initiate a row broadcast through an east and / or west output port, wherein the row broadcast carries first data, a row broadcast identifier and a row storage mask; receiving a data packet of line broadcast initiated by other nodes through an east and / or west input port, forwarding the data packet, and determining whether to store data according to the line storage mask; initiating a column broadcast through a south and / or north output port, wherein the column broadcast carries second data, a column broadcast identifier and a column storage mask; and receiving a data packet of initiating column broadcast by other nodes through a south and / or north input port, forwarding the data packet, and determining whether to store data according to the column storage mask. According to the method, the efficiency of inter-network communication of the network-on-chip can be improved, the complexity of back-end implementation is reduced, and large-scale integration and optimization are facilitated.

The present invention belongs to the technical field of semiconductor optoelectronic devices, and specifically relates to an optical computing array based on a germanium modulator, comprising a cross matrix, wherein the cross matrix is ​​formed by crossing multiple rows of mutually parallel input optical waveguides and multiple columns of mutually parallel output optical waveguides; and a photodetector is provided at the output end of each column of the output optical waveguide; multiple optical splitters; multiple germanium modulators, each of the germanium modulators corresponds to one of the cross waveguides, and the first input end of the germanium modulator is connected to the output end of the optical splitter through a transmission optical waveguide; and multiple optical combiners, each of the optical combiners is respectively connected to the output end of the germanium modulator and the output optical waveguide. Through the above structure, the present application comprehensively provides a computing array with a high responsiveness having a thermal compensation mechanism and capable of reducing light reflection, so as to realize a solution for a low-power large-scale integrated computing array under the condition of frequent switching.

The invention relates to the technical field of very large scale integrated circuit design verification, and discloses a hierarchical cross-clock domain signal verification method, device and equipment and a medium. According to the method, on the basis of the physical layout information file corresponding to each functional module, the target functional module to be verified is dynamically, intelligently and accurately determined from the plurality of functional modules. And performing cross-clock domain signal verification on the previous level of the target function module by extracting the target sign-off abstract model of the target function module, and performing cross-clock domain signal verification on the top system of the whole chip by analogy. As clock domain crossing signal verification does not need to be carried out on all functional modules, the efficiency of chip verification can be improved, clock domain crossing signal verification, module level focusing functional module internal logic integrity verification and top layer enhanced module crossing asynchronous path analysis are carried out on the chip layer by layer through the target sign-off abstract model, and the chip verification efficiency is improved. Therefore, the accuracy of chip verification can be improved.

The invention provides a single-port input / output multi-state adjustable waveguide mode converter and a preparation method thereof, and belongs to the technical field of on-chip silicon-based polymer hybrid integrated waveguide mode converters. According to the invention, a double-layer MZI parallel combination structure is adopted, independent electrodes are configured at specific positions of interference arms, and corresponding modulation signals are applied, so that accurate regulation and control of an input light field are realized. When E00-mode signal light is input, the structure can dynamically realize the conversion function of three modes of E00 / E01 / E10 on the premise of keeping single-port output, and the mode conversion efficiency reaches 95%. And the device is compatible with a standard silicon-based CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process, is beneficial to reducing the manufacturing cost and promoting large-scale integrated application, is suitable for the fields of a high-capacity mode division multiplexing system and multi-dimensional optical signal processing, and can meet the urgent requirements of modern optical communication on high-integration-level, reconfigurable operation and low-cost devices.

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory.SOLUTION: Thin film transistor integrated circuits such as an LSI, a CPU, and a memory are manufactured using semiconductors whose channel regions are formed using semiconductors which are intrinsic or substantially intrinsic by removal of an impurity which serves as an electronic donor (donor) and whose energy gap is larger than that of silicon semiconductors. With the use of the thin film transistor, power consumption due to leakage current can be reduced.SELECTED DRAWING: Figure 1

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

The disclosure relates to compositions, methods and systems for inkjet printing of dielectric materials. Specifically, the disclosure is directed to compositions, methods and systems for the inkjet printing of three-dimensional (3D) of high-performance printed circuit boards (PCBs), high-density interconnect PCBs (HDIPs), large-scale integrated systems (LSI) and other high- performance additively manufactured electronics (AME), each having low stress, low thermal expansion, low dielectric constant, capable of being cured at relatively low temperature and once cured, undergo reflow at typical processing temperatures.

The invention belongs to the technical field of semiconductor optoelectronic devices, and particularly relates to an optical computing array based on a reverse bias germanium modulator, which comprises a cross matrix formed by crossing a plurality of rows of mutually parallel input optical waveguides and a plurality of columns of mutually parallel output optical waveguides, a photoelectric detector is arranged at the output end of each row of output optical waveguides; a plurality of optical splitters; each germanium modulator corresponds to one crossed waveguide, and the first input end of each germanium modulator is connected with the output end of the optical splitter through a transmission optical waveguide; each light combiner is connected with the output end of the germanium modulator and the output optical waveguide, through the above structure, the computing array which has a thermal compensation mechanism, can reduce light reflection and is high in responsivity is comprehensively provided, and therefore under the condition that frequent switching is met, the computing array has the advantages that the computing efficiency is improved, and the computing efficiency is improved. And a low-power-consumption large-scale integrated calculation array scheme is realized.

The invention discloses a p-type two-dimensional semiconductor top gate field effect transistor and a preparation method thereof, and the preparation method comprises the steps: preparing a source electrode and a drain electrode on the surface of a two-dimensional semiconductor material, then defining a two-dimensional semiconductor channel region, etching to remove the two-dimensional semiconductor material outside the channel region, and then preparing a p-type seed layer, a gate dielectric layer and a gate electrode, the p-type seed layer covers the substrate, the surface of the two-dimensional semiconductor material, the upper surface of the source electrode, the upper surface of the drain electrode and the side wall exposed in the range of the transistor. According to the preparation method provided by the invention, before the dielectric layer is prepared, the p-type seed layer is prepared firstly, and the Fermi level of the two-dimensional semiconductor material is fixed near a valence band, so that p doping is realized, the process stability is good, and the obtained p-type two-dimensional semiconductor top gate field effect transistor has relatively large on-state current and switch ratio, relatively small source leakage current and hysteresis, and relatively high reliability. The power consumption is reduced, an advanced process is adapted, and the method has a wide application prospect in the manufacturing of a large-scale integrated circuit.

The invention discloses a silicon-based high-mobility wide-band-gap tin-based oxide film, a preparation method thereof and a transistor, and belongs to the technical field of low-power-consumption electronic devices. The preparation method of the tin-based oxide thin film provided by the invention comprises the following steps: firstly, sequentially preparing a sacrificial layer and a single crystal tin-based oxide thin film on a temporary growth substrate to obtain an oxide heterostructure; then preparing a supporting layer, and adhering the single crystal tin-based oxide thin film by using the supporting layer to realize stripping of the single crystal tin-based oxide thin film from the single crystal substrate; and finally, transferring the single crystal tin-based oxide thin film to the silicon substrate to realize compatible integration of the single crystal tin-based oxide thin film and the silicon substrate. The single crystal tin-based oxide thin film is transferred to the silicon substrate through a substrate-free transfer technology, dependence on a high-cost specific substrate is eliminated, a mature silicon-based process is compatible, and a foundation is laid for large-scale integrated circuit application; and finally, the thin film transistor with low power consumption, high performance and low cost is prepared, the cost advantage is remarkable, and the application prospect is wide.

The present disclosure relates to a method, system, storage medium and electronic device for very large scale integrated circuit; the method for very large scale integrated circuit obtains timing information TNS of the entire netlist of the very large scale integrated circuit; all nodes are sorted according to the topology structure of the integrated circuit, and nodes with the same serial number are placed in the same queue; all sorted nodes are traversed in reverse according to the number of queues; the size reduction preprocessing is performed on all nodes in the same queue, and the slack change value of the output pin of the current node and the next level node is obtained; the slack change value of the output pin of the current node and the next level node is checked, the current node with the slack change value of the output pin meeting the requirements is subjected to size reduction processing; the timing information of the current node and the next level node is updated, the timing information new_TNS of the entire netlist is reobtained; the timing information new_TNS and TNS are compared, and the area power consumption in the physical optimization of the very large scale integrated circuit is optimized according to the comparison result. The problem of excessive area power consumption in the physical optimization design process under the condition of unchanged timing can be solved.

1. Name of the Design Product: Four-Tube Diffusion Furnace. 2. Use of the Design Product: Used for processes such as diffusion, oxidation, annealing, alloying, and sintering in industries such as large-scale integrated circuits, discrete devices, power electronics, optoelectronic devices, and optical fibers. 3. Design Key Points of the Design Product: Lies in the overall shape of the product. 4. Picture or Photograph Most Indicating the Design Key Points: Perspective View.

The application provides a high-dimensional multi-objective evolutionary method based on an improved dominance criterion, which is used for optimizing the wiring design of a very large scale integrated circuit physical design and comprises the following steps: step one, convergence of a non-dominated solution set is ensured according to a defined convergence index, and an adaptive parameter based on a genetic algorithm niche is combined to control the diversity of the solution set, the radius target and the line length target of the wiring design are optimized by minimizing MOP, and the dominance criterion is improved; step two, a convergence index and a diversity index are designed, the two indexes jointly constitute a dynamic fitness function, and individuals with better convergence and diversity are adaptively reserved to perform MaOEA-IDR environment selection; and step three, an adaptive t distribution crossover operator is provided, which can balance the global search capability of a Cauchy operator and the local exploration capability of a Gaussian operator in a high-dimensional space, and the ASDX adaptive distribution crossover operator is adaptively adjusted. t The application can effectively solve the wiring problem of the very large scale integrated circuit physical design.

This invention discloses a high-speed, high-precision voltage descent monitoring circuit, solving the problem of accurate and timely monitoring of voltage descent phenomena in large-scale integrated circuits, belonging to the fields of digital integrated circuit design and power management. This invention provides an optimized design method for ring oscillator point circuits, using standard cell type, threshold, drive capability, and power consumption as variables to find the ring oscillator circuit design with the highest voltage sensitivity, improving the resolution of the voltage descent monitoring circuit; it provides a one-fold, compact ring oscillator layout design to ensure load balance between nodes; it provides a Nyquist counter design to count the number of times nodes flip over a period of time, improving the voltage monitoring range and solving the metastable sampling problem of traditional counters; and it provides a high-speed voltage quantization circuit that processes coarse and fine quantization in parallel, improving the maximum sampling rate and quantization rate of the voltage descent monitoring circuit.

The application discloses a photoelectric memristor with a light source and a preparation method thereof, and comprises at least one LED providing a light source, a memristor body, and an insulating layer filled between the LED and the memristor body; the LED and the memristor body are vertically integrated, and adjacent LEDs are aligned two by two, and the memristor body is aligned with the adjacent LEDs. The LED structure comprises a substrate, a buffer layer, an N-type layer, a light-emitting layer, a P-type layer, an N electrode and a P electrode; the memristor body structure comprises a bottom electrode layer, a dielectric layer and a top electrode layer. The LED preparation method comprises sequentially growing the buffer layer, the N-type layer, the light-emitting layer, the P-type layer, the N electrode and the P electrode on the substrate, then filling and polishing, and finally sequentially growing the bottom electrode layer, the dielectric layer and the top electrode layer of the memristor. The photoelectric memristor with the light source integrates the light source LED and the memristor seamlessly on one device, and realizes the regulation of the conductance of the memristor by utilizing the light emission of the LED. The method is favorable for the subsequent large-scale integration of the photoelectric memristor.

The present invention provides a superconducting quantum chip packaging structure and a flip-chip packaging method for a superconducting quantum chip. By using SU-8 photoresist with characteristics such as high resolution and high aspect ratio, the photoresist is used as a supporting structure to achieve flip-chip packaging of the superconducting quantum chip. Compared with the prior art, the flip-chip packaging method can realize personalized design of the supporting structure according to different circuit wiring layer structures, which is more conducive to the large-scale integration of superconducting quantum chips, and does not require manual operation during operation. It has a high degree of mechanization, can significantly improve the flip-chip packaging efficiency of the superconducting quantum chip, thereby reducing the manufacturing cost of the superconducting quantum chip, and does not require space for flip-chip operation around the device when flip-chip packaging is performed, so that a process for flip-chip packaging on a superconducting quantum chip of 4*4mm or smaller can be achieved, which is more conducive to the large-scale integration of superconducting quantum chips.

The application provides a SOT-MRAM and a manufacturing method thereof, the SOT-MRAM comprising a substrate, a plurality of memory cells arranged on the substrate. Each memory cell comprises a SOT layer deposited on the substrate, a magnetic tunnel junction arranged on the SOT layer. Further comprising an antiferromagnetic insulating layer at least wrapping around the side surface of the free layer in each magnetic tunnel junction, and the magnetic moment direction of the antiferromagnetic insulating layer is parallel to the direction of the write current in the SOT layer. By adding the antiferromagnetic insulating layer at least wrapping around the side surface of the free layer in each magnetic tunnel junction, and further making the magnetic moment direction of the antiferromagnetic insulating layer parallel to the direction of the write current, an in-plane magnetic field can be provided for the free layer, for the field-free switching of the SOT-MRAM, solving the problem that the SOT-MRAM cannot be mass integrated due to the need to apply an external magnetic field during the writing process. And the added antiferromagnetic insulating layer is arranged around the magnetic tunnel junction, thereby also having the effect of protecting the magnetic tunnel junction from the surrounding environment.

The invention provides an integrated topological optimization photonic device reverse design method. Maxwell equation solution and objective function optimization are put in the same position. And the optimization of a target function is realized while the Maxwell equation is solved. Compared with a traditional topological optimization method which needs to solve a Maxwell equation set for multiple times, the integrated topological optimization algorithm put forward by the invention has the advantages that the Maxwell equation and the objective function are placed at the same position, the limitation that one of the Maxwell equation and the objective function must be established constantly is relaxed, Maxwell equation solving and objective function optimization are realized at the same time, the Maxwell equation does not need to be solved again after parameters are updated each time, and the optimization efficiency of the Maxwell equation and the objective function is improved. And a large amount of computing resources required by topological optimization are greatly saved. The photonic device designed by the invention has the advantages of small physical size, suitability for large-scale integration and the like.

This invention provides a cavity-enhanced germanium-silicon photodetector based on silicon corner mirrors, comprising a silicon substrate layer, a germanium absorption region on the silicon substrate layer, and silicon corner mirrors located on the front and rear sides of the germanium absorption region; a germanium via layer is provided above the germanium absorption region, the via layer having a plurality of germanium vias, and a signal electrode is provided at the top of the germanium via layer; silicon via layers are provided on the left and right sides of the germanium absorption region, the silicon via layers having a plurality of silicon vias, and a ground electrode is provided at the top of the silicon via layers; two silicon nitride waveguides are arranged opposite each other, extending from the opposite outer sides of the two silicon via layers toward the sides of the germanium absorption region. The technical solution of this invention has excellent high-power processing capability, achieves polarization-insensitive detection, effectively overcomes the contradiction between responsivity and bandwidth, is fully compatible with CMOS manufacturing processes, and is conducive to large-scale integration and mass production.

Disclosed are a method and apparatus for accelerating physical verification of a large-scale integrated circuit, and a storage medium. The method comprises: establishing a corresponding physical verification task for each round of design at every development stage of an integrated circuit design; and for any round of design at any development stage of the integrated circuit design, classifying and grouping checking rules in a physical verification checking rule base on the basis of technological process characteristics and / or physical verification requirements of the round of design, each classification comprising at least one attention group, splitting the physical verification task of the round of design into at least one sub-task, each sub-task corresponding to one attention group, and executing sub-tasks of all classifications in parallel, each sub-task using a checking rule comprised in a corresponding attention group to perform physical verification on the round of design of the integrated circuit.