98 results about "Very large scale integrated" patented technology

The invention provides a node of a network-on-chip, a data transmission method of the node and the network-on-chip. A node of the network-on-chip comprises a control module, and a plurality of input ports and a plurality of output ports in east, south, west and north directions; the control module is configured to initiate a row broadcast through an east and / or west output port, wherein the row broadcast carries first data, a row broadcast identifier and a row storage mask; receiving a data packet of line broadcast initiated by other nodes through an east and / or west input port, forwarding the data packet, and determining whether to store data according to the line storage mask; initiating a column broadcast through a south and / or north output port, wherein the column broadcast carries second data, a column broadcast identifier and a column storage mask; and receiving a data packet of initiating column broadcast by other nodes through a south and / or north input port, forwarding the data packet, and determining whether to store data according to the column storage mask. According to the method, the efficiency of inter-network communication of the network-on-chip can be improved, the complexity of back-end implementation is reduced, and large-scale integration and optimization are facilitated.

The invention relates to the technical field of very large scale integrated circuit design verification, and discloses a hierarchical cross-clock domain signal verification method, device and equipment and a medium. According to the method, on the basis of the physical layout information file corresponding to each functional module, the target functional module to be verified is dynamically, intelligently and accurately determined from the plurality of functional modules. And performing cross-clock domain signal verification on the previous level of the target function module by extracting the target sign-off abstract model of the target function module, and performing cross-clock domain signal verification on the top system of the whole chip by analogy. As clock domain crossing signal verification does not need to be carried out on all functional modules, the efficiency of chip verification can be improved, clock domain crossing signal verification, module level focusing functional module internal logic integrity verification and top layer enhanced module crossing asynchronous path analysis are carried out on the chip layer by layer through the target sign-off abstract model, and the chip verification efficiency is improved. Therefore, the accuracy of chip verification can be improved.

The invention provides a single-port input / output multi-state adjustable waveguide mode converter and a preparation method thereof, and belongs to the technical field of on-chip silicon-based polymer hybrid integrated waveguide mode converters. According to the invention, a double-layer MZI parallel combination structure is adopted, independent electrodes are configured at specific positions of interference arms, and corresponding modulation signals are applied, so that accurate regulation and control of an input light field are realized. When E00-mode signal light is input, the structure can dynamically realize the conversion function of three modes of E00 / E01 / E10 on the premise of keeping single-port output, and the mode conversion efficiency reaches 95%. And the device is compatible with a standard silicon-based CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process, is beneficial to reducing the manufacturing cost and promoting large-scale integrated application, is suitable for the fields of a high-capacity mode division multiplexing system and multi-dimensional optical signal processing, and can meet the urgent requirements of modern optical communication on high-integration-level, reconfigurable operation and low-cost devices.

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory.SOLUTION: Thin film transistor integrated circuits such as an LSI, a CPU, and a memory are manufactured using semiconductors whose channel regions are formed using semiconductors which are intrinsic or substantially intrinsic by removal of an impurity which serves as an electronic donor (donor) and whose energy gap is larger than that of silicon semiconductors. With the use of the thin film transistor, power consumption due to leakage current can be reduced.SELECTED DRAWING: Figure 1

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

The invention discloses a silicon-based high-mobility wide-band-gap tin-based oxide film, a preparation method thereof and a transistor, and belongs to the technical field of low-power-consumption electronic devices. The preparation method of the tin-based oxide thin film provided by the invention comprises the following steps: firstly, sequentially preparing a sacrificial layer and a single crystal tin-based oxide thin film on a temporary growth substrate to obtain an oxide heterostructure; then preparing a supporting layer, and adhering the single crystal tin-based oxide thin film by using the supporting layer to realize stripping of the single crystal tin-based oxide thin film from the single crystal substrate; and finally, transferring the single crystal tin-based oxide thin film to the silicon substrate to realize compatible integration of the single crystal tin-based oxide thin film and the silicon substrate. The single crystal tin-based oxide thin film is transferred to the silicon substrate through a substrate-free transfer technology, dependence on a high-cost specific substrate is eliminated, a mature silicon-based process is compatible, and a foundation is laid for large-scale integrated circuit application; and finally, the thin film transistor with low power consumption, high performance and low cost is prepared, the cost advantage is remarkable, and the application prospect is wide.

The present disclosure relates to a method, system, storage medium and electronic device for very large scale integrated circuit; the method for very large scale integrated circuit obtains timing information TNS of the entire netlist of the very large scale integrated circuit; all nodes are sorted according to the topology structure of the integrated circuit, and nodes with the same serial number are placed in the same queue; all sorted nodes are traversed in reverse according to the number of queues; the size reduction preprocessing is performed on all nodes in the same queue, and the slack change value of the output pin of the current node and the next level node is obtained; the slack change value of the output pin of the current node and the next level node is checked, the current node with the slack change value of the output pin meeting the requirements is subjected to size reduction processing; the timing information of the current node and the next level node is updated, the timing information new_TNS of the entire netlist is reobtained; the timing information new_TNS and TNS are compared, and the area power consumption in the physical optimization of the very large scale integrated circuit is optimized according to the comparison result. The problem of excessive area power consumption in the physical optimization design process under the condition of unchanged timing can be solved.

The application provides a high-dimensional multi-objective evolutionary method based on an improved dominance criterion, which is used for optimizing the wiring design of a very large scale integrated circuit physical design and comprises the following steps: step one, convergence of a non-dominated solution set is ensured according to a defined convergence index, and an adaptive parameter based on a genetic algorithm niche is combined to control the diversity of the solution set, the radius target and the line length target of the wiring design are optimized by minimizing MOP, and the dominance criterion is improved; step two, a convergence index and a diversity index are designed, the two indexes jointly constitute a dynamic fitness function, and individuals with better convergence and diversity are adaptively reserved to perform MaOEA-IDR environment selection; and step three, an adaptive t distribution crossover operator is provided, which can balance the global search capability of a Cauchy operator and the local exploration capability of a Gaussian operator in a high-dimensional space, and the ASDX adaptive distribution crossover operator is adaptively adjusted. t The application can effectively solve the wiring problem of the very large scale integrated circuit physical design.

This invention discloses a high-speed, high-precision voltage descent monitoring circuit, solving the problem of accurate and timely monitoring of voltage descent phenomena in large-scale integrated circuits, belonging to the fields of digital integrated circuit design and power management. This invention provides an optimized design method for ring oscillator point circuits, using standard cell type, threshold, drive capability, and power consumption as variables to find the ring oscillator circuit design with the highest voltage sensitivity, improving the resolution of the voltage descent monitoring circuit; it provides a one-fold, compact ring oscillator layout design to ensure load balance between nodes; it provides a Nyquist counter design to count the number of times nodes flip over a period of time, improving the voltage monitoring range and solving the metastable sampling problem of traditional counters; and it provides a high-speed voltage quantization circuit that processes coarse and fine quantization in parallel, improving the maximum sampling rate and quantization rate of the voltage descent monitoring circuit.

The application provides a SOT-MRAM and a manufacturing method thereof, the SOT-MRAM comprising a substrate, a plurality of memory cells arranged on the substrate. Each memory cell comprises a SOT layer deposited on the substrate, a magnetic tunnel junction arranged on the SOT layer. Further comprising an antiferromagnetic insulating layer at least wrapping around the side surface of the free layer in each magnetic tunnel junction, and the magnetic moment direction of the antiferromagnetic insulating layer is parallel to the direction of the write current in the SOT layer. By adding the antiferromagnetic insulating layer at least wrapping around the side surface of the free layer in each magnetic tunnel junction, and further making the magnetic moment direction of the antiferromagnetic insulating layer parallel to the direction of the write current, an in-plane magnetic field can be provided for the free layer, for the field-free switching of the SOT-MRAM, solving the problem that the SOT-MRAM cannot be mass integrated due to the need to apply an external magnetic field during the writing process. And the added antiferromagnetic insulating layer is arranged around the magnetic tunnel junction, thereby also having the effect of protecting the magnetic tunnel junction from the surrounding environment.

The invention provides an integrated topological optimization photonic device reverse design method. Maxwell equation solution and objective function optimization are put in the same position. And the optimization of a target function is realized while the Maxwell equation is solved. Compared with a traditional topological optimization method which needs to solve a Maxwell equation set for multiple times, the integrated topological optimization algorithm put forward by the invention has the advantages that the Maxwell equation and the objective function are placed at the same position, the limitation that one of the Maxwell equation and the objective function must be established constantly is relaxed, Maxwell equation solving and objective function optimization are realized at the same time, the Maxwell equation does not need to be solved again after parameters are updated each time, and the optimization efficiency of the Maxwell equation and the objective function is improved. And a large amount of computing resources required by topological optimization are greatly saved. The photonic device designed by the invention has the advantages of small physical size, suitability for large-scale integration and the like.

This invention provides a cavity-enhanced germanium-silicon photodetector based on silicon corner mirrors, comprising a silicon substrate layer, a germanium absorption region on the silicon substrate layer, and silicon corner mirrors located on the front and rear sides of the germanium absorption region; a germanium via layer is provided above the germanium absorption region, the via layer having a plurality of germanium vias, and a signal electrode is provided at the top of the germanium via layer; silicon via layers are provided on the left and right sides of the germanium absorption region, the silicon via layers having a plurality of silicon vias, and a ground electrode is provided at the top of the silicon via layers; two silicon nitride waveguides are arranged opposite each other, extending from the opposite outer sides of the two silicon via layers toward the sides of the germanium absorption region. The technical solution of this invention has excellent high-power processing capability, achieves polarization-insensitive detection, effectively overcomes the contradiction between responsivity and bandwidth, is fully compatible with CMOS manufacturing processes, and is conducive to large-scale integration and mass production.

The application discloses a micro-nano acoustic image sensor capable of large-scale integration and a control method thereof. The micro-nano acoustic image sensor comprises a plurality of pixel sensing units arranged in an array; each pixel sensing unit comprises a micro-mechanical ultrasonic transducer located at a top layer, a pixel circuit located at a bottom layer and an inter-electrode metal bonding layer connecting the two; wherein the micro-mechanical ultrasonic transducer is an acoustic-electric conversion unit with an inverted diaphragm structure, and is connected to the pixel circuit through a lower electrode layer; the pixel circuit is an integrated circuit internal unit with a "3T1D" structure, has a peak sound pressure rectification function, and synchronously senses and addresses samples the sound pressure signal of each pixel sensing unit through an inverse correlation double sampling method, and the sampling method has a global shutter function. The application can perform large-scale array integration on the pixel sensing unit, and perform tomographic sampling on the spatial distribution of ultrasonic echoes, and can directly realize dynamic intensity imaging and distance tomographic imaging of a target sound field.

The application belongs to the technical field of semiconductor optoelectronic devices, and particularly relates to a light computing array based on a reverse bias germanium modulator, which comprises a cross matrix formed by multiple rows of parallel input light waveguides and multiple columns of parallel output light waveguides; an optical detector is arranged at the output end of each column of the output light waveguides; multiple light splitters; multiple germanium modulators, each corresponding to one cross waveguide, and the first input end of the germanium modulator being connected with the output end of the light splitter through a transmission light waveguide; and multiple light combiners, each being connected with the output end of the germanium modulator and the output light waveguide. Through the above structure, the application comprehensively provides a high-response computing array with a thermal compensation mechanism and capable of reducing light reflection, so as to realize a scheme of a large-scale integrated computing array with low power consumption under the condition of meeting frequent switching.

The invention discloses an optical switch device and a complex-valued optical neural network system, and belongs to the technical field of optical computing. The optical switch device is a two-input two-output device and comprises first to sixth waveguides, and first and second multimode interference couplers. Phase shifters are attached to the third waveguide and the fifth waveguide and / or the fourth waveguide and the sixth waveguide to form a group of configuration units which are used for loading real part and imaginary part data of a complex number. The phase shifter comprises a nonvolatile phase change material layer and a heating layer which are sequentially arranged from bottom to top, is used for realizing the function of the phase shifter, greatly reduces the static power consumption, improves the energy efficiency, is suitable for realizing the complex value optical neural network, and is also beneficial to large-scale integration. The complex-valued optical neural network system constructed based on the optical switch integrates input, calculation, reference and coherent detection modules, can synchronously complete amplitude and phase detection of optical signals, effectively supports complex-valued optical calculation, and has the advantages of low power consumption and high integration level.

The invention discloses an active layer based on light regulation free radical bipolar doping, a device, an array and a visual system. The problems that existing neuromorphic vision hardware is low in integration level, single in function and difficult to meet complex requirements are solved. The active layer comprises an organic semiconductor material and a free radical dopant, and wavelength selective reversible bipolar doping can be realized: p-type doping is presented and excitatory response is generated under 808 nm irradiation, and n-type doping is presented and inhibitory response is generated under 450 nm irradiation. Based on the active layer, an optical reconfigurable bipolar neuromorphic device with a simple structure is constructed, and the device has dynamic synaptic characteristics and light-controlled bipolar photoelectric response at the same time. The device is used as a pixel unit, can be integrated on a large scale to form a neuromorphic visual array, and forms a complete system with a signal reading and processing unit. The system can synchronously execute multiple visual functions of motion detection, spatio-temporal information memory and contrast enhancement feature extraction at a sensing front end.

The present application relates to the field of artificial neuromorphics, and provides an artificial neuron circuit based on a volatile threshold switching device. A membrane potential generation circuit is used for generating different membrane potentials under different input currents and different external reset voltages; a slow variable generation circuit is used for generating a slow variable; a membrane potential reset circuit comprises a volatile threshold switching device and an external reset voltage excitation source; the external reset voltage excitation source is used for providing different external reset voltages, so that the membrane potential and the slow variable are changed, and a spiking behavior of biological neurons is simulated; and the volatile threshold switching device is used for realizing a membrane potential reset function. Compared with traditional CMOS-circuit-based neurons, the neuron circuit provided by the present application requires a greatly reduced number of transistors and reduced hardware and power consumption overhead, has the characteristics of simple structure, high flexibility and rich functions, and is beneficial to large-scale integration in a hardware pulse neural network.

The invention provides an airflow heat dissipation device of a micro piezoelectric pump, and relates to the technical field of micro electro mechanical systems. An inlet runner arranged on the lower end face of a flow guide part and an outlet runner arranged on the upper end face of the flow guide part are both communicated with a flow guide channel arranged on the flow guide part, and the cross sectional area of the outlet runner is gradually reduced in the direction from the first end to the second end of the outlet runner. The PZT piezoelectric layer is arranged on the upper end face of the flow guide part and provided with a pump film corresponding to the flow guide channel, and the first electrode can drive the pump film to move up and down. The airflow heat dissipation device of the micro piezoelectric pump is suitable for heat dissipation operation of micro components and large-scale integrated circuit systems, and ensures that the temperature of the components and the operating environment of the systems is stable.

A manufacturing method of a large-scale integrated laser ignition nuclear fusion device is characterized in that a recording machine technology is used for manufacturing equipment capable of rapidly punching holes with different angles in a large scale, the equipment is used for punching a large number of holes capable of pointing photon beams emitted by placed lasers to the same point, and the number of the holes is determined according to ignition nuclear fusion reaction requirements; the hole diameter is determined by equipment precision and ignition nuclear fusion needs.

This invention discloses a stacked packaging structure and method, including a molding compound layer. At least four layers of chips are stacked and mounted face-down within the molding compound layer. Through-holes are formed in the molding compound layer and metallized to form a solid or overlay metallized structure. A redistribution circuit structure is disposed on the molding compound layer and ball-mounted. This invention achieves vertical interconnection of multi-layer chips through staggered chip stacking combined with TMV technology, effectively utilizing space and reducing package size. The solid metallized through-holes effectively improve power integrity and signal integrity, enhance read / write performance of storage products, increase I / O density and bandwidth, and reduce power consumption. The solid metallized through-holes can be stacked, further shortening line length and reducing package size. Simultaneous fabrication of the redistribution circuit structure on both sides greatly improves packaging efficiency. The packaging structure can include multiple stacked structure arrays, suitable for large-scale integration and increasing packaging density.

LOW-POWER VLSI MICROCHIP FOR EDGE MACHINE LEARNING APPLICATION.

The application discloses a Rydberg atom electric field sensing device and system, and is applied to the field of quantum sensing.The device comprises an atom chamber, a first distributed feedback laser and a second distributed feedback laser.The first distributed feedback laser and the second distributed feedback laser each comprise a laser source resonant cavity formed inside.The first distributed feedback laser and the second distributed feedback laser generate laser based on optical feedback and optical amplification of the laser source resonant cavity inside each of them, and the laser is used as probe light and pump light respectively, and enters from one side of the atom chamber, so that the atoms in the atom chamber reach the excited state and the Rydberg state in turn.The application uses the distributed feedback laser as the pump light and the probe light for exciting the Rydberg atom, provides a miniaturized light source for the Rydberg atom electric field sensing device, improves the integration of the device, has the advantages of miniaturization, is easy to move, is suitable for a harsh outdoor environment, and can realize large-scale integration of chips.

The application discloses a high-temperature superconducting diode with break-through liquid nitrogen temperature and controllable polarity and an implementation method thereof, and belongs to the technical field of semiconductor devices. The application can adapt to different circuit function requirements by presetting a built-in magnetic field to the magnetic substrate and locking the polarity of the high-temperature superconducting diode. The high-temperature superconducting diode is integrated with a single high-temperature superconducting material and a magnetic substrate, and a complex heterojunction is not needed, so that the preparation difficulty and cost are reduced, and large-scale integration is facilitated. The magnetic moment of the magnetic substrate is used as a built-in magnetic field source, so that the dependence on a continuous external magnetic field is completely eliminated, and the convenience and reliability of practical application are improved. A copper oxide high-temperature superconducting sheet is adopted, so that the liquid nitrogen temperature bottleneck is broken through, and the application potential in practical environments is expanded. The application solves the problems of low working temperature and dynamic polarity regulation of the superconducting diode, and has important significance for promoting the development of low-power-consumption electronic circuits and quantum computing as a basic operation element of low-power-consumption high-energy-efficiency circuits.

This provides a method for predicting the biological behavior of target tissues. [Solution] The biomimetic platform includes a fluid synthesis device having a first fluid input unit selectively coupled to a source of a first input fluid solution, and a second fluid input unit selectively coupled to a source of a second input fluid solution. The fluid synthesis device further includes a fluid output unit. The biomimetic platform further includes a fluid addressing system having a fluid input unit fluidly coupled to the fluid output unit of the fluid synthesis device. The fluid addressing system further includes a first fluid output unit and a second fluid output unit. The biomimetic platform further includes a first biomimetic device having a fluid input unit fluidly coupled to the first fluid output unit of the fluid addressing system, and a second biomimetic device having a fluid input unit fluidly coupled to the second fluid output unit of the fluid addressing system.

The invention discloses a precursor treatment method for preparing a boron nitride film, and belongs to the field of two-dimensional material preparation. The precursor treatment method for preparing the boron nitride film comprises the following steps: heating ammonia borane powder in a hydrogen atmosphere at 120-140 DEG C to obtain ammonia borane with a stalactite-shaped structure. By regulating and controlling the structure and release behavior of ammonia borane, stable supply of a growth source is achieved, generation of by-products is inhibited, the film quality is improved, and the method is suitable for large-scale integrated preparation of device-level two-dimensional materials.

The application provides a D-band one-dimensional DBF-AIP microsystem architecture, comprising a quartz substrate, an on-chip antenna arranged on the upper surface of the quartz substrate, an RFIC chip arranged on the lower surface of the quartz substrate, a microwave board arranged below the quartz substrate, and BGA solder balls for connecting the quartz substrate and the microwave board. The D-band one-dimensional DBF-AIP microsystem architecture provided by the application maximally shortens the signal transmission distance, reduces the parasitic parameters, and obtains better performance, and meanwhile, the D-band one-dimensional DBF-AIP microsystem architecture is small in size, light in weight, and suitable for large-scale integration.

The invention discloses an AI-assisted time sequence report analysis method, and belongs to the technical field of integrated circuit design automation. The method comprises the following steps: acquiring a static time sequence analysis report; analyzing the report through an analysis rule base, and extracting structured information of a time sequence path; performing hierarchical grouping on the plurality of analyzed time sequence paths according to time sequence grouping, clock domains and violation types to generate time sequence statistical characteristics; and identifying a key path according to the time sequence statistical characteristics, and outputting a structured analysis result and an optimization suggestion. Through automatic analysis and intelligent analysis, the time sequence debugging efficiency is remarkably improved, dependence on experience of engineers is reduced, and the method is suitable for time sequence convergence scenes of large-scale integrated circuit design.

The present disclosure relates to a method, system, storage medium and electronic device for very large scale integrated circuit. The method for very large scale integrated circuit comprises the following steps: obtaining timing information TNS of the entire netlist of the integrated circuit; obtaining the worst timing path through each end node in the netlist; scanning all cell nodes in the worst timing path, and obtaining the number of worst timing paths of each cell node; obtaining the slack value of the worst output pin of the cell node for each cell node on the worst timing path; performing downsize estimation processing on the cell node, and obtaining the downsize estimation score of the cell node based on the number of worst timing paths of the cell node and the slack value of the worst output pin; arranging the downsize estimation scores of the cell nodes in descending order, selecting the first N cell nodes for downsize processing, and calculating the timing information new_TNS of the netlist; and optimizing the area power consumption in the physical optimization of the integrated circuit according to the timing information new_TNS and the timing information TNS of the entire netlist. The problem of excessive area power consumption in the physical optimization design process under the condition of unchanged timing can be solved.

The application discloses an interface automatic batch connection method, relates to the technical field of interface connection, and comprises the following steps: S1, confirming input / output ports; S2, parameterized macro definition; S3, connection code generation; S4, batch generation of interfaces; and S5, batch connection. In the application, the batch interface connection automation generation realized through the parameterized macro definition reduces the need for manual coding, reduces the risk of human errors, improves the efficiency of the verification process, and designers only need to specify macro parameters in a configuration file, so that a large number of different interface connections can be quickly configured without the need to write complex connection codes. The parameterized macro definition enhances the reusability of the codes, the same macro definition can be repeatedly used in different projects or different verification platforms, the parameterized macro definition provides high flexibility, supports quick modification and adaptation of the interface connection, and is helpful to adapt to various complex scenes in the large-scale integrated circuit design process.

This invention provides a streaming data management method and apparatus for a reconfigurable processor multi-port cache, relating to the field of large-scale integrated circuit technology. The method includes: when processing a cell array accessing the cache, if a cache miss occurs, evicting a cache line with a target bit set to a first preset value using a polling arbitration method, and setting the target bit of subsequent cache lines entering the cache to the first preset value; when processing a cell array accessing the cache, if a cache hit occurs, setting the target bit of the currently hit cache line to a second preset value based on the interval between the previously hit cache line and the currently hit cache line. This invention can effectively reduce the probability of cache thrashing under the flushing of streaming data, thereby reducing the frequency of accessing off-chip memory, increasing the memory access bandwidth of the PEA, mitigating potential conflicts and misses caused by set-associations, and reducing the miss rate for streaming data.