Low-overhead transient fault automatic correction circuit for high speed adder

An automatic correction and adder technology, applied in instruments, electrical digital data processing, data representation error detection/correction, etc., can solve large-area overhead or delay overhead, dual-mode redundancy can only detect errors but not correct them, etc. problem, to achieve the effect of improving resource utilization efficiency, reducing cost, and reducing area overhead

Inactive Publication Date: 2011-11-23
NAT UNIV OF DEFENSE TECH
View PDF2 Cites 6 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Although copy error correction and time-shift error correction technologies reduce the overhead of triple-mode redundancy and solve the problem that ...

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Low-overhead transient fault automatic correction circuit for high speed adder
  • Low-overhead transient fault automatic correction circuit for high speed adder
  • Low-overhead transient fault automatic correction circuit for high speed adder

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0024] The structure and working process of the low-overhead high-speed adder transient fault automatic correction circuit disclosed by the present invention will be described in detail below in conjunction with the accompanying drawings.

[0025] The low-overhead high-speed adder transient fault automatic correction circuit disclosed by the present invention consists of three parts, such as image 3 As shown, they are the group carry G / P generation part, the carry tree part and the partial sum generation and selection part respectively. In order to illustrate clearly, a 64-bit adder is taken as an example below. In fact, the structure of the present invention is applicable to adders of any bit width.

[0026] The group carry G / P generating part generates a 4-bit group G / P group carry signal. The input is a 4-bit A i+3 ~A i and B i+3 ~B i , after three stages of logic, the output group carry generates signal G i+3，i and group carry propagation signal P i+3，i ,like Fi...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

Transient faults in a combinational logic become a major challenge for the VLSI (very large scale integrated circuit) design. As a typical component in the combinational logic, an adder is widely applied to an arithmetic unit. The invention discloses a low-overhead transient fault automatic correction circuit for a high speed adder. According to the structure, through developing the abundant inherent hardware redundancy and time redundancy existing in the adder circuit, automatic correction on the transient faults in the high speed adder can be realized with lower overhead, thus the fault-tolerant area and performance overheads can be obviously reduced; and through combining a fault correction technology based on a C unit and the inherent hardware redundancy and time redundancy, the transient fault correction capacity of the adder can be further enhanced. The adder provided by the invention has preferably compromised area-delay overhead compared with other structures.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, mainly relates to the field of transient fault prevention and recovery of integrated circuit chips, in particular refers to the use of circuit design reinforcement technology to realize automatic correction of transient faults of high-speed adders with low overhead, thereby improving circuit reliability structure and technology. Background technique [0002] Transient faults in integrated circuits are mainly caused by various high-energy particles. When high-energy particles are injected into the integrated circuit, instantaneous charge and discharge will occur, and the charged and discharged charge will be absorbed by the sensitive area, which will cause the logic state of the integrated circuit to change, cause operation errors or output errors, and seriously affect the reliability of the integrated circuit. The high-energy particles that cause transient faults mainly come from the cos...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H03M13/03G06F7/57
Inventor 张民选孙岩陈吉华李少青赵振宇马卓张明何小威乐大珩张均安谭晓强段志奎
Owner NAT UNIV OF DEFENSE TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap