Data retention device for power-down applications and method

A data retention and data technology, applied in electrical components, generation of electrical pulses, climate sustainability, etc., can solve the problems of slow shadow latches, shadow latches cannot work, etc., to extend battery life, reduce Area overhead, effect of reducing die size

Inactive Publication Date: 2008-07-30
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Also, shadow latches may not work at low operating voltages
Due to the higher threshold voltage (V t ), transferring flip-flop data into and out of the shadow latch may become slower as the supply voltage decreases

Method used

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  • Data retention device for power-down applications and method
  • Data retention device for power-down applications and method
  • Data retention device for power-down applications and method

Examples

Experimental program
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Embodiment Construction

[0016] [016] Depending on the application requirements, the functionality of the various circuits, devices, or elements described herein can be implemented in hardware (including discrete components, integrated circuits, and system-on-chip "SoCs"), firmware (including application-specific integrated circuits and programmable chips) and / or software or a combination thereof.

[0017] [017] Many conventional data-hold flip-flops based on MTCMOS technology employ a third latch for data retention. This technique results in an increase in area per flip-flop and, depending on the number of data-holding flip-flops used in the chip, can result in a large increase in die area. Furthermore, shadow latches may not work with scalable voltage sources used in those power savers. These issues can be addressed with an improved data retention technique with reduced area overhead per flip-flop and operation in a scalable low voltage environment. In the improved data retention system and method...

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PUM

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Abstract

In a method and system for data retention, a data input is latched by a first latch. A second latch coupled to the first latch receives the data input for retention while the first latch is inoperative in a standby power mode. The first latch receives power from a first power line that is switched off during the standby power mode. The second latch receives power from a second power line. A controller receives a clock input and a retention signal and provides a clock output to the first latch and the second latch. A change in the retention signal is indicative of a transition to the standby power mode. The controller continues to hold the clock output at a predefined voltage level and the second latch continues to receive power from the second power line in the standby power mode, thereby retaining the data input.

Description

technical field [0001] [001] The present disclosure relates generally to integrated circuits (ICs); and, more particularly, to apparatus and methods for providing data retention with reduced power consumption. Background technique [0002] [002] Many portable electronic devices, such as cellular telephones, digital cameras / camcorders, personal digital assistants, laptop computers and electronic game consoles, are battery operated. During periods of inactivity, these devices may not be performing processing operations and so may be placed in a power down or standby power mode to save power. The power supplied to the IC within the electronic device may be turned off in the backup power mode. However, the occurrence of leakage currents during backup power mode presents challenges for designing portable battery operated devices. Data retention circuitry within the device, such as flip-flops and / or latches, may be used to store status information for later use before the device...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K3/356H03K3/286
CPCH03K3/356008H04W52/0283Y02D30/70
Inventor S·K·古鲁拉贾拉奥H·T·迈尔D·B·斯科特U·科
Owner TEXAS INSTR INC
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