Three-dimensional memory device, manufacturing method thereof and electronic device

Abstract

The invention discloses a three-dimensional memory device, a manufacturing method thereof and an electronic device. The manufacturing method comprises the following steps: providing a substrate; doping the substrate to form a source electrode; forming a control gate stack structure on the substrate, wherein the control gate stack structure comprises a plurality of interlevel dielectric layers and control gate layers which are stacked in a staggered manner, the control gate layers are formed between adjacent interlevel dielectric layers, the control gate layers comprise transition metal sulfide; patterning the control gate stack structure to form a hole exposing the source electrode in the control gate stack structure; forming a charge trapping layer on the side wall of the hole; depositing a channel material layer to fill the hole; and forming a drain electrode on the control gate stack structure. According to the manufacturing method of the three-dimensional memory device provided by the invention, the height of the control gate stack structure can be effectively reduced, so that the difficulties of forming a channel, depositing in the channel and the like are reduced.

Description

technical field [0001] The invention relates to the field of electronic storage, in particular to a three-dimensional storage device, a manufacturing method thereof, and an electronic device. Background technique [0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered in planar flash memory and to seek lower production costs per unit storage unit, various three-dimensional (3D) memory structures have emerged, such as 3D NOR (3D or not) flash memory and 3D NAND (3D NAND) flash memory. Wherein, in the 3D flash memory of the NOR structure, memory cells are arranged in parallel between the bit line and the ground line, while in the 3D flash memory of the NAND ...

AI Technical Summary

Problems solved by technology

[0003] In order to obtain a larger storage capacity per unit chip area, the number of stacked structures in 3D NAND flash memory is required to increase, and the height of the stacked structure continues to increase, which makes it more and more difficult to form channels in three-dimensional memories. , the process cost rises, which seriously restricts the development of 3D NAND flash memory technology

Not only that, the realization of epitaxial growth, deposition, ion implantation and other processes in the channel becomes more and more difficult as the height of the stack structure increases

In addition, 3D NAND flash memory with polysilicon as the gate layer still has problems such as large die size, high power consumption, and signal propagation delay that need to be solved urgently.

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