8 results about "Carry propagation" patented technology

This invention discloses a fully pipelined AES real-time encryption system for high-speed transmission, aiming to solve the technical bottlenecks of limited throughput and excessive processing latency in traditional encryption architectures in high-speed networks. The system mainly includes a data input buffer module, a fully pipelined encryption operation module, a round key pre-computation module, and a data output driver module. The core of this invention lies in the operator-level hardware reconstruction of the AES underlying algorithm: the S-box nonlinearity is replaced and embedded in the distributed ROM of the FPGA to achieve zero-clock-cycle asynchronous table lookup, and a carry-free XOR tree architecture based on the XTime operator is used to reconstruct column hybrid operations, eliminating deep carry propagation chains.

This invention discloses a binary adder array and method based on node decision, relating to the field of integrated circuits. It aims to solve the problems of high dynamic power consumption, reliance on critical path delay, and complex asynchronous adder circuitry in traditional adders. The method includes: calculating the carry propagation signal Pi and the carry generation signal Gi in parallel using operands A and B; generating a decision node Di for each bit i based on Pi and Gi; setting Di low when Gi=1, setting Di high when Gi=0 and Pi=0, and assigning the state Di-1 to Di when Pi=1; generating the next bit sum signal Si+1 based on Di; outputting ~Pi+1 when Di is low, and outputting Pi+1 when Di is high. Signal transmission is achieved by controlling the on / off state of physical channels, rather than cascading logic gates. The device includes a logic operation module and an output control module. The output control module includes a node control network with level injection units and level transmission switches, all connected to the decision node Di. This invention also provides an asynchronous adder array composed of multiple cascaded adder units and a chip integrating this circuit. This invention achieves conditional signal propagation through a unique decision node network and physical channel control, which can significantly reduce dynamic power consumption when the input data is sparse, and naturally supports asynchronous operation, with the advantages of high energy efficiency and easy expansion.

The present application discloses a carry logic circuit, a carry cascade circuit, and a chip. The carry logic circuit comprises Y stages of cascaded carry operation modules and a carry output module; each stage of carry operation module is used for receiving i pairs of arithmetic signals; a first-stage carry operation module is used for outputting a first-stage carry generation signal and outputting a first-stage carry propagation signal; an x th-stage carry operation module is further used for receiving a previous-stage carry generation signal and a previous-stage carry propagation signal, outputting an x th-stage carry generation signal, and outputting an x th-stage carry propagation signal; and the carry output module is used for receiving an initial carry signal, a Y th-stage carry generation signal, and a Y th-stage carry propagation signal, and outputting a first carry signal. The present application improves the carry operation performance of the carry logic circuit.

The invention relates to an adder circuit, a multi-bit adder, a chip and electronic equipment. According to an exemplary embodiment, the present disclosure discloses an adder circuit, an input signal of which includes a carry pass signal and a carry generation signal generated based on a standard addend; or, the input signal of the adder circuit comprises a complementary signal of a carry transfer signal generated based on a standard addend and a complementary signal of a carry generation signal generated based on the standard addend; wherein the carry transfer signal or the complementary signal of the carry transfer signal is generated by a carry transfer signal generation circuit located outside the adder circuit, and the carry generation signal or the complementary signal of the carry generation signal is generated by a carry generation signal generation circuit located outside the adder circuit. The technical scheme disclosed by the invention has the effects of reducing the use number of transistors, reducing the power consumption and the area of the adder, and improving the operation speed of the adder circuit at the same time.

The high-speed selective carry propagation adder circuit consists of a full adder that performs selective carry propagation in the critical path, rather than the conventional carry propagation method that limits operating speed. Instead of propagating the carry and using it for summation, it is proposed to propagate a selective carry in the critical path and use it for summation. As a result, the number of transistors required for the full adder cell is reduced, and high-speed operation and low power consumption are achieved by reducing parasitic resistance and capacitance. Furthermore, the proposed circuit design reduces the number of transistors required for a 1-bit full adder cell to 14 for static CMOS logic, 10 for transmission gate type, and 8 for pass transistor type. In addition, the proposed adder circuit provides a versatile and efficient solution for multi-bit adders in various logic schemes and is expected to have applications in various fields.

The application discloses a programmable logic circuit, which comprising: a first lookup table circuit for generating and outputting a first output signal based on a received input signal; a second lookup table circuit for generating a carry propagation signal and a carry generation signal based on a received input signal, selecting one of the signals as the output; a first selection circuit for receiving a carry input signal and a carry generation signal, selecting one of the signals as the output based on the carry propagation signal; a second selection circuit for receiving a first output signal and a second output signal, selecting one of the signals as the output based on the selection output signal. The circuit provided in this application includes the addition operation of multivariate functions, which improves the configuration flexibility and logic resource utilization efficiency of programmable logic devices in addition operation mode.

A bounded-carry partial-sum adder for FP8 accumulation in a pipelined mixed-precision processing element is disclosed. The adder limits carry propagation to a predetermined depth, ensuring deterministic fixed delay independent of operand magnitude. The accumulator forms the second stage of a two-stage fused multiply-add pipeline and supports a one-cycle initiation interval while accumulating products of FP4 weight operands and FP8 activation operands. The architecture enables uniform high-frequency timing across dense arrays of processing elements.

The invention discloses an RISC-V processor-oriented finite field modular operation acceleration implementation method. Comprising the following steps: 1, constructing an unsaturated multi-limb representation model of finite field elements in a 64-bit general register of a processor; 2, based on a multiplication instruction execution delay characteristic of the RISC-V processor, designing a calculation and memory access interleaved instruction scheduling strategy; 3, carrying out decoupling scheduling on carry propagation and a modular reduction path by adopting a delay correction mechanism in the general register; 4, aiming at modular square operation, constructing an instruction level reduction path in a processor instruction set environment, and realizing cross-limb carry processing through a logic shift instruction and an unsigned comparison instruction; and 5, realizing a delay accumulation and mask correction mechanism of modular addition and subtraction operation on a register level by using a redundant bit width represented by unsaturation. According to the method, on the premise of not changing the mathematical structure of the original cryptographic algorithm, the operation acceleration which is several times of the existing implementation is realized by optimizing the register resources and instruction scheduling of the processor.