3 results about "Carry propagation" patented technology

This invention discloses a fully pipelined AES real-time encryption system for high-speed transmission, aiming to solve the technical bottlenecks of limited throughput and excessive processing latency in traditional encryption architectures in high-speed networks. The system mainly includes a data input buffer module, a fully pipelined encryption operation module, a round key pre-computation module, and a data output driver module. The core of this invention lies in the operator-level hardware reconstruction of the AES underlying algorithm: the S-box nonlinearity is replaced and embedded in the distributed ROM of the FPGA to achieve zero-clock-cycle asynchronous table lookup, and a carry-free XOR tree architecture based on the XTime operator is used to reconstruct column hybrid operations, eliminating deep carry propagation chains.

This invention discloses a binary adder array and method based on node decision, relating to the field of integrated circuits. It aims to solve the problems of high dynamic power consumption, reliance on critical path delay, and complex asynchronous adder circuitry in traditional adders. The method includes: calculating the carry propagation signal Pi and the carry generation signal Gi in parallel using operands A and B; generating a decision node Di for each bit i based on Pi and Gi; setting Di low when Gi=1, setting Di high when Gi=0 and Pi=0, and assigning the state Di-1 to Di when Pi=1; generating the next bit sum signal Si+1 based on Di; outputting ~Pi+1 when Di is low, and outputting Pi+1 when Di is high. Signal transmission is achieved by controlling the on / off state of physical channels, rather than cascading logic gates. The device includes a logic operation module and an output control module. The output control module includes a node control network with level injection units and level transmission switches, all connected to the decision node Di. This invention also provides an asynchronous adder array composed of multiple cascaded adder units and a chip integrating this circuit. This invention achieves conditional signal propagation through a unique decision node network and physical channel control, which can significantly reduce dynamic power consumption when the input data is sparse, and naturally supports asynchronous operation, with the advantages of high energy efficiency and easy expansion.

A bounded-carry partial-sum adder for FP8 accumulation in a pipelined mixed-precision processing element is disclosed. The adder limits carry propagation to a predetermined depth, ensuring deterministic fixed delay independent of operand magnitude. The accumulator forms the second stage of a two-stage fused multiply-add pipeline and supports a one-cycle initiation interval while accumulating products of FP4 weight operands and FP8 activation operands. The architecture enables uniform high-frequency timing across dense arrays of processing elements.