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Conditional selection adder and method of conditional selection adding

A technology of condition selection and adder, applied in the direction of using non-contact manufacturing equipment for calculation, instrumentation, calculation, etc., can solve the problem of increasing the area occupied by the adder

Inactive Publication Date: 2008-02-06
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the number of bits increases, the area occupied by the adder increases

Method used

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  • Conditional selection adder and method of conditional selection adding
  • Conditional selection adder and method of conditional selection adding
  • Conditional selection adder and method of conditional selection adding

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Embodiment Construction

[0018] Embodiments of the invention will now be described more fully with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements in this application.

[0019] It will be understood that, although the terms first, second etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, th...

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Abstract

Conditional selection adders include first and second signal generators and a summation circuit. The first signal generator is configured to generate a carry generation signal and a carry propagation signal in response to a pair of operands to be added. The second signal generator is configured to generate a carry input signal and a block carry signal in response to the carry generation signal and the carry propagation signal. This second signal generator includes a plurality of groups of leaf-cells arranged in ascending order from a first group containing the fewest number of leaf-cells to a second group containing a largest number of leaf-cells. The summation circuit is configured to generate a sum of the pair of operands in response to the block carry signal, the carry propagation signal and the carry input signal. The summation circuit may include a group bypass circuit and a summation unit.

Description

[0001] This application claims priority from Korean Patent Application No. 2006-71890 filed on Jul. 31, 2006, the contents of which are hereby incorporated by reference. technical field [0002] The present invention relates to integrated circuit devices and, more particularly, to binary adders for use in integrated circuit devices. Background technique [0003] Semiconductor integrated circuits (ICs) can be classified into standard ICs and application specific integrated circuits (ASICs). ASICs are manufactured for specific purposes based on customer requirements. Full custom ICs are designed and manufactured into final chips according to user requirements. Semi-custom ICs include pre-fabricated standard cells and gate arrays and the desired logic circuits formed by routing interconnects on the gate arrays. [0004] In addition, various ICs can be manufactured by placing and routing pre-prepared leaf-cells according to the compiled macrocell library of the ASIC library, s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/507
CPCG06F7/506G06F7/50G06F7/485G06F7/503
Inventor 李光柱
Owner SAMSUNG ELECTRONICS CO LTD
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