A fast algorithm for calculating the undercurrent path of an adder based on a memristor array

A fast computing and memristor technology, applied in computing, instruments, electrical digital data processing, etc., can solve the problem of consuming memristor array hardware resources and achieve the effect of improving computing performance

Active Publication Date: 2019-03-26
SHANGHAI JIAO TONG UNIV
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  • Claims
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Problems solved by technology

The disadvantage of this implementation is the same as that based on the lookup table, that is, it is not a real memory calculation, and it consumes a lot of hardware resources of the memristor array.

Method used

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  • A fast algorithm for calculating the undercurrent path of an adder based on a memristor array
  • A fast algorithm for calculating the undercurrent path of an adder based on a memristor array
  • A fast algorithm for calculating the undercurrent path of an adder based on a memristor array

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Embodiment

[0047] The logical expression of the 1-bit full adder can be expressed as the following two formulas:

[0048]

[0049] C o =AB+AC i +BC i

[0050] For a multi-bit adder, if the calculation is performed step by step in a logical iterative manner, the operation efficiency will be low, thus losing the advantage of memory computing technology due to the reduction of data movement overhead. However, if the carry of all bits can be obtained in an efficient manner, the sum of all bits can be obtained at one time by using the parallel feature of the array structure.

[0051] According to the above thought, Figure 1a and 1b The schematic diagram of the carry calculation based on the memristor is given. Note that the memristor represents the logic value through the resistance value, the low resistance state (LRS) represents logic 1, and the high resistance state (HRS) represents logic 0. in Figure 1a Three undercurrent paths for carry generation are shown:

[0052] 1) Carry ...

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Abstract

The invention discloses a fast algorithm for calculating the undercurrent path of an adder based on a memristor array, comprising the following steps: 1) carrying subsurface current path mapping, calculating the states of RG, RD and RP in advance, and determining the carrying calculation paths of different bits; 2) constructing a serial carry chain, and as a transmission path cannot be formed by the array structure, a carry propagation path control by the RP needs to be customized to cope with the RP in step 1); 3) after that carry calculation of the summation calculation bits is completed, completing the summation calculation of all the bits in parallel through the corresponding logic. The invention is based on the design of the adder of the memristor memory array, and utilizes HSPICE anda novel non-volatile memory simulation tool NVSim to test the design, so as to remarkably improve the computational performance, the area overhead and the power consumption overhead.

Description

technical field [0001] The invention relates to the technical field of memory computing, in particular to a fast computing method for an adder based on a memristor array undercurrent path. Background technique [0002] At present, there are three main methods for adding calculations based on memristor memory arrays. [0003] They are based on Boolean logic, look-up table (LUT) and programmable logic array (PLA). [0004] The method based on Boolean logic is the most simple and intuitive, that is, the logic expression based on addition is stitched together through the basic logic organization supported by the circuit. Typical implementations include IMPLY circuits, MAGIC circuits, etc. However, the disadvantage of this calculation method is also obvious, that is, the calculation efficiency is low. For a 1-bit full adder, using IMPLY circuit and MAGIC circuit requires 29 and 12 steps of operation, respectively. Contemporary computing systems are usually 32-bit wide. Under th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/505
CPCG06F7/5052
Inventor 景乃锋李桃中李彤王琴蒋剑飞贺光辉毛志刚
Owner SHANGHAI JIAO TONG UNIV
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