35 results about "Programmable logic array" patented technology

The invention discloses a financial auditing system based on artificial intelligence, which belongs to the technical field of artificial intelligence and comprises a heterogeneous data dynamic adaptation device, a trusted data pipeline system and a central auditing processing unit. The heterogeneous data dynamic adaptation device comprises a multi-protocol PHY chip set, an FPGA programmable logic array, a protocol sensing antenna array and an AI coprocessor. The protocol sensing antenna array is annularly arranged on the inner wall of the device shell and comprises at least 12 miniature receiving and transmitting modules with adjustable directions; a protocol reverse learning model is arranged in the AI coprocessor, and a protocol analysis scheme is dynamically generated by analyzing electromagnetic radiation characteristics of an interface. According to the financial auditing system based on artificial intelligence, real-time dynamic data adaptation and credible traceability of a cross-heterogeneous financial system can be achieved, the problems of format conflict, semantic ambiguity and transmission delay of multi-source heterogeneous data in the auditing process are solved, and meanwhile verifiability and non-tampering performance of the data extraction process are ensured.

The invention relates to the field of petroleum and petrochemical fire fighting, in particular to an SIS-based interlocked control device for petroleum and petrochemical fire fighting, which comprises a sensing fusion unit for acquiring optical fiber, radar, acoustics, an event camera and dual-band images, and generating a feature tensor and an attitude matrix through multi-scale synchronization and gating sparse fusion. And the prediction and risk assessment unit outputs disaster prediction data, a propagation potential energy matrix and a risk entropy by using the graph neural network spatial-temporal model and the generative adversarial correction. The interlocking control unit constructs a binary optimization model by taking the minimum action number and the residual potential energy as targets, obtains a minimum action set by means of quantum annealing and a minimum-maximum game, and writes the minimum action set into the memristive programmable logic array to generate an interlocking instruction stream. And the execution and feedback unit controls the two-phase flow jetting device, the robot unit and the heat shielding device to complete treatment, and feedback event flow is used for model incremental learning and action deviation correction. According to the invention, millisecond interlocking triggering is realized, the action redundancy is reduced, and the fire spreading radius is obviously reduced.

Examples herein describe a three-dimensional (3D) die stack. The 3D die stack includes a programmable logic (PL) die and a computing die stacked on top of the PL die. The PL die includes a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die. The computing die includes a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the computing die. The three-dimensional die stack includes a plurality of tiles, each tile including M configurable blocks included in the plurality of configurable blocks and N data processing engines included in the plurality of data processing engines.

This application discloses a control system for a controllable vibration source, belonging to the field of controllable vibration sources. This control system achieves precise control of the controllable vibration source through a host computer and a system-on-a-chip (SoC) integrating a processor and a programmable logic array (PLA). The host computer transmits configuration information to the PCA, where the processor generates a reference scan signal based on the configuration information. The processor then controls the vibrator of the controllable vibration source to perform vibration operations based on the reference scan signal. Furthermore, to ensure that the vibration signal generated by the vibrator meets requirements, a control algorithm can be executed through the PCA to generate control signals. These control signals can then be used to precisely adjust the vibration signal generated by the vibrator, thus achieving precise control of the controllable vibration source.

The invention discloses train control vehicle-mounted equipment, which comprises two main control subsystems, and each main control subsystem comprises a safety controller module. The safety controller module is composed of symmetrical physical double channels, and each channel comprises an independent voltage system, an SOC system, a storage system, a communication interface, an IO interface, a panel connector and a backboard connector. The SOC system comprises a single chip, the single chip comprises a processing system and a programmable logic array, the processing system is used for undertaking operation system scheduling management, peripheral communication management and logic operation functions, and the programmable logic array is used for undertaking clock distribution, bottom layer driving and implementation of a general protocol. According to the equipment provided by the invention, the integration level of the SOC system is relatively high, and the processing performance is improved based on the integration level, so that the processing performance can meet ever-increasing control requirements.

The invention provides a simulation system of power conversion equipment and a simulation method thereof, and belongs to the technical field of power electronics. An upper computer in the system is used for issuing a circuit model of the power conversion equipment to a programmable logic array; and the programmable logic array is used for updating the current values of the current sources in the plurality of switch branches at the current simulation moment according to the branch voltage values and the branch current values of the plurality of switch branches at the previous simulation moment in the simulation process of the circuit model. Wherein the current value I (t) of the current source in each switch branch at the current simulation moment meets the condition that I (t) = alpha * G * v (t-t) + beta * i (t-t) + gamma; alpha is a voltage coefficient, G is an admittance value of the switch branch, v (t-t) is a branch voltage value at the previous simulation moment, beta is a current coefficient, i (t-t) is a branch current value at the previous simulation moment, gamma is a current compensation value, and t is a simulation step length. And the simulation precision of the simulation system is improved.

The utility model provides a test circuit and a test system for a memory chip. The test circuit comprises a test circuit and a plurality of sub test circuits, the test circuit is provided with a programmable logic array and a plurality of I / O expansion circuits. The programmable logic array expands pins of the programmable logic array through a plurality of I / O expansion circuits to obtain a plurality of test pins; different sub test circuits are provided with different ball grid arrays; a corresponding memory chip is placed in each ball grid array; the test pin is connected with the memory chip through the ball grid array; the upper computer receives the test instruction, controls the programmable logic array to send a test electric signal to the storage chip, receives an actual electric signal corresponding to the test electric signal output by the storage chip, and transmits the actual electric signal to the upper computer; the upper computer is also used for determining the performance of the storage chip according to the actual electric signal. According to the circuit, different types of to-be-tested memory chips are connected with the upper computer through different types of ball grid arrays, so that the test efficiency is improved.

In accordance with various embodiments of the present disclosure, a programmable logic array circuit is provided. In some embodiments, the programmable logic array circuit comprises an AND plane comprising a plurality of groups of product term straps, an OR plane comprising a plurality of output lines, a first plurality of dynamically driven shield lines in the AND plane, and a second plurality of dynamically driven shield lines in the OR plane. Each of the plurality of groups of product term straps is adjacent to only one corresponding one of the first plurality of dynamically driven shield lines. Each of the plurality of output lines is adjacent to only one corresponding one of the second plurality of dynamically driven shield lines.

This paper discloses a method, computer storage medium, and terminal for implementing self-testing. In this embodiment, a first acquisition function unit and a second acquisition function unit are instantiated inside a field-programmable logic array (FPGA). After inputting analog signals to the first and second acquisition function units, the input of the i-th acquisition processing channel of the first acquisition function unit is adjusted to a preset waveform occupied by the track. By comparing the output results of the acquisition processing performed by the first and second acquisition function units, the self-testing function of the track circuit signal acquisition module is realized.

Examples herein describe a three-dimensional (3D) die stack. The 3D die stack includes a programmable logic (PL) die and a compute die stacked on top of the PL die. The PL die includes a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die. The compute die includes a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the compute die. The three-dimensional die stack includes a plurality of tiles, each tile comprising M configurable blocks included in the plurality of configurable blocks and N data processing engines included in the plurality of data processing engines.

The invention relates to active capacitive shielding for programmable logic arrays. According to various embodiments of the present disclosure, a programmable logic array circuit is provided. In some embodiments, a programmable logic array circuit includes an AND plane including a plurality of sets of product term bands, an OR plane including a plurality of output lines, a first plurality of dynamic drive shield lines in the AND plane, and a second plurality of dynamic drive shield lines in the OR plane. Each of the plurality of sets of product term bands is only adjacent to a corresponding line of the first plurality of dynamically driven shielded lines. Each of the plurality of output lines is only adjacent to a corresponding line of the second plurality of dynamic drive shield lines.

The application discloses a logic control method and system of a programmable controller, and the method comprises the following steps: step 1, capturing discrete state transition events of a physical device in real time through a heterogeneous sensor network, generating a time-stamped asynchronous event stream, and filtering out steady-state redundant signals; step 2, constructing a temporary logic unit cluster in a programmable logic array according to the space-time correlation of the event stream, and each unit sharing an event context in real time and dynamically establishing a logic relationship mapping; step 3, triggering a distributed computing node based on the event type priority of the logic unit cluster, executing a preset control rule in parallel, generating a non-blocking control instruction set, and synchronously injecting an output buffer channel; and step 4, monitoring the deviation degree of an execution result and an expected state, automatically deconstructing a current logic unit cluster and recombining it into a new logic unit cluster that is topologically optimized when the deviation exceeds a threshold, and forming an adaptive control loop. The application significantly improves the control precision, response speed and system reliability of an automobile stamping production line.

The invention relates to a measurement method and circuit for improving ultrasonic flow measurement precision, and the method comprises the steps: receiving a start signal generated and output from the interior of a programmable logic array FPGA, and starting a flowmeter to trigger an enable signal; when the flow meter detects the rising edge of the starting signal, initializing the timing reference of flow measurement to zero time; performing time sequence analysis on the ultrasonic original echo signal through a time delay method, and determining a starting time node corresponding to the effective original data; based on the starting time node, filtering all invalid pulse signals in a time period from the zero moment to the starting time node; starting a signal acquisition process from a moment corresponding to the starting time node, and receiving an externally input pulse signal; accurate control over the measurement time sequence is achieved through the FPGA, time delay method time sequence analysis and a multi-stage pulse screening mechanism are combined, invalid signal interference is effectively filtered, and the effectiveness of original data is improved.

The present invention relates to the field of oil and petrochemical fire protection, and particularly to an interlock control device for oil and petrochemical fire protection based on SIS, including: a perception fusion unit that collects optical fibers, radars, acoustics, event cameras, and dual-band images, and generates a feature tensor and an attitude matrix through multi-scale synchronization and gated sparse fusion. A prediction and risk assessment unit uses a graph neural network spatio-temporal model and generative adversarial correction to output disaster prediction data, a propagation potential matrix, and a risk entropy. An interlock control unit constructs a binary optimization model with the goal of minimizing the number of actions and residual potential energy, obtains a minimum action set by means of quantum annealing and min-max game, and writes it into a memristive programmable logic array to generate an interlock instruction stream. An execution and feedback unit controls a two-phase flow injection device, a robot team, and a heat shield device to complete the disposal, and the feedback event stream is used for model incremental learning and action correction. The present invention realizes millisecond-level interlock triggering, reduces action redundancy, and significantly reduces the fire spread radius.

The invention provides a vehicle-mounted data acquisition gateway device, which comprises a programmable logic array, a multi-path CAN (Controller Area Network) equipment interface circuit, a multi-path Ethernet interface circuit, a solid-state storage circuit and a high-speed serial interface circuit, the solid-state storage circuit, the multi-path CAN equipment interface circuit, the multi-path Ethernet interface circuit and the high-speed serial interface circuit are respectively connected with the programmable logic array, each path of CAN equipment interface circuit is correspondingly connected with each path of CANBUS bus system, and the multi-path Ethernet interface circuit is respectively connected with the host terminal and the network terminal. The high-speed serial interface circuit is connected with the mobile storage device; and the programmable logic array is used for controlling the driving of each interface circuit and realizing the transceiving management and storage of data under the condition of no operating system, and sending a timing pulse frame to the host terminal so as to enable the host terminal to carry out state monitoring on the vehicle-mounted data acquisition gateway device.

The invention discloses a modular addressing ultrasonic sensor array receiving circuit system, belongs to the field of ultrasonic nondestructive testing instruments, and can be used for receiving echo signals detected by array elements with different apertures in a 64 array element addressing receiving ultrasonic sensor array. Each channel of the circuit system takes a row array element of an addressing ultrasonic sensor array as a receiving unit, and is matched with a column gating switch circuit to realize integral or selective receiving of different array elements in the row, so that the row number is taken as the channel number, and receiving, preprocessing, A / D conversion and decoding of 64 array element signals are realized; and the data can be stored in an FPGA (field programmable gate array) or transmitted to an upper computer so as to facilitate secondary development and utilization of echo signals. The circuit system provided by the invention adopts a modular structure, takes 8 channels as independent modules, and can provide a solution for a 64-array-element addressing ultrasonic sensor array receiving circuit.

An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.

The invention relates to an image registration method and device, an electronic device and a storage medium, and the method comprises the steps: obtaining a to-be-registered video image, caching the to-be-registered video image to a programmable logic array, obtaining a target registration coordinate and a registration parameter, and carrying out the registration of the to-be-registered video image according to the target registration coordinate and the registration parameter. And determining a to-be-registered original image coordinate corresponding to the target registration coordinate in the to-be-registered video image, determining to-be-registered original image data corresponding to the to-be-registered original image coordinate in the to-be-registered video image, and determining a target video image corresponding to the to-be-registered video image according to the to-be-registered original image data and the target registration coordinate. Through the image registration method and device, the problem of how to quickly realize image registration without occupying memory bandwidth in related technologies is solved, time delay is reduced, the real-time performance of an image registration application scene is improved, resources are saved, and the cost is reduced.

The invention provides a programmable logic array, a configuration method, a terminal and a chip. The programmable logic array comprises a preceding-stage filtering control module and n configurable operation channels; n inputs and n outputs of the programmable logic array are respectively connected to the preceding-stage filtering control module; 2n outputs of the preceding-stage filtering control module are used as inputs of each configurable operation channel; the outputs of the n configurable operation channels are n outputs of the programmable logic array; and according to the obtained target signal generation demand, respectively configuring the pre-stage filtering control module and each configurable operation channel, so that the output of the programmable logic array meets the target signal generation demand. The programmable logic array can be flexibly configured according to the target signal generation requirement, the flexibility of the programmable logic array is improved, and then the universality of the control device adopting the programmable logic array is improved.

Reconfigurable device components such as look up tables (LUT), D-flip flop registers and internal switch designs for programmable array of logic (PLA), programmable logic array (PLA), programmable logic device (PLD), complex PLD (CPLD), field programmable gate arrays (FPGAs), eASIC, structured ASIC, embedded FPGAs, and other programmable hardware devices are provided.

The invention relates to the field of inner coating of small-diameter steel pipe sintered epoxy powder, in particular to a thermal management device of a small-diameter steel pipe sintered epoxy powder pipeline, which comprises a control unit, a refrigeration unit, a monitoring unit and an outer pipe. The control unit is installed outside the outer pipe and electrically connected to the refrigeration unit and the monitoring unit, reads monitoring information from the monitoring unit, sends alarm information and further sends control information to the refrigeration unit. The refrigeration unit is installed in the outer pipe, and the monitoring unit is arranged across the outer pipe and enters the steel pipe along with the outer pipe in the working process. And the powder conveying pipe is sleeved in the outer pipe. The refrigeration unit wraps the powder conveying pipe. The monitoring unit is attached to the powder conveying pipe. The invention also comprises a method. Through integration of a semiconductor refrigeration technology, a heat pipe heat conduction technology, a temperature sensor and a programmable logic array technology, effective heat management of the small-diameter steel pipe sintering epoxy powder inner coating powder conveying pipeline is achieved, and then the problems of powder blocking and caking caused by the too high temperature of the powder outlet end of the powder conveying pipe are thoroughly solved.

A control system an unmanned vehicle includes a first processing unit configured to execute a primary autopilot process for controlling the unmanned vehicle. The control system further includes a programmable logic array in operative communication with the first processing unit. The control system also includes a state machine configured in the programmable logic array. The state machine is configured to enable control of the unmanned vehicle according to a backup autopilot process in response to an invalid output of the first processing unit.

A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.

The utility model discloses a two-way CAN interface adapter plate based on a 3U-CPCI bus, and relates to the technical field of integrated circuits, the two-way CAN interface adapter plate comprises an adapter plate, the adapter plate is provided with a CPCI interface, a bottom plate interface and a power supply module, the input end of the power supply module is electrically connected with the bottom plate interface, the whole adapter plate adopts a 3U size, and the power supply module is electrically connected with the CPCI interface. The adapter plate can be widely applied to the fields of military computers and industrial personal computers, a main control unit in the adapter plate takes an XC7Z020-2CLG484 chip as a main control, adopted CPCI interfaces and the like are high in applicability, a CPCI interface bus is directly connected to the main control unit, slave interface equipment is realized by a programmable logic array end in the main control unit, a bridging or adapter chip is not needed, the integration degree is high, and the adapter plate can be widely applied to the fields of military computers and industrial personal computers. The coding unit is connected to the PS end of a control chip in the main control unit, the main control unit serves as a controller of the coding unit and a main controller at the same time, the size is saved, the development difficulty is low, the bottom plate interface provides two CAN interfaces, and the structure is simple.

Examples herein describe a three-dimensional (3D) die stack. The 3D die stack includes a programmable logic (PL) die and a compute die stacked on top of the PL die. The PL die includes a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die. The compute die includes a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the compute die. The three-dimensional die stack includes a plurality of tiles, each tile comprising M configurable blocks included in the plurality of configurable blocks and N data processing engines included in the plurality of data processing engines.

The invention provides a circuit structure of a programmable logic array, a configuration method, a terminal, a medium and a chip. The circuit structure comprises a front-stage filtering control module, a front-stage configurable arithmetic logic module, a rear-stage filtering control module, a rear-stage configurable arithmetic logic module and a configurable trigger module which are connected in sequence, wherein the pre-stage filtering control module, the pre-stage configurable arithmetic logic module, the post-stage filtering control module, the post-stage configurable arithmetic logic module and the configurable trigger module are configured according to the obtained target signal generation requirement, so that the output of the circuit structure meets the target signal generation requirement. The programmable logic array can be flexibly configured according to the signal generation requirement, the flexibility of the programmable logic array is improved, and the universality of a control system in which the programmable logic array is introduced is improved.

The invention discloses a novel polarization insensitive space arithmetic unit. The structure of the novel polarization insensitive space arithmetic unit comprises a plasma layer and a dielectric layer, the plasma layer is mainly composed of internal inert gas and electrodes used for excitation, a specific excitation source needs to be used for forming the plasma layer, the excitation source is controlled by the programmable logic array, and therefore effective excitation of plasmas is achieved. The dielectric layer comprises two kinds of media with different dielectric constants, namely porous silicon and air. The plasma layer and the dielectric layer form an inclined laminated structure, and plasmas of the first layer and the middle layer are split cross-shaped structures. The space arithmetic unit designed by the invention can perform asymmetric transmission operation on incident electromagnetic waves in different polarization states, the operation precision and stability are not influenced by the polarization state of incident light, and the space arithmetic unit has the characteristics of polarization insensitivity, compact structure, easiness in integration and the like, and is expected to be applied to many fields such as optical information processing, optical communication and the like.

A control system an unmanned vehicle includes a first processing unit configured to execute a primary autopilot process for controlling the unmanned vehicle. The control system further includes a programmable logic array in operative communication with the first processing unit. The control system also includes a state machine configured in the programmable logic array. The state machine is configured to enable control of the unmanned vehicle according to a backup autopilot process in response to an invalid output of the first processing unit.

The present invention discloses a data processing method, apparatus, non-volatile storage medium, and computer equipment. The method comprises: detecting an original video stream to obtain signal characteristic parameters of the original video stream, wherein the original video stream is used to transmit video data; writing the signal characteristic parameters into the original video stream to obtain a target video stream; and transmitting the target video stream to a display driver programmable logic array, wherein the display driver programmable logic array drives a display device to display the video based on the signal characteristic parameters and video data read from the target video stream. The present invention solves the technical problem of poor user experience caused by time delays in video display in the prior art.

The invention discloses a general test board card for a radar signal processing unit, and mainly solves the problems that an existing test device is deficient in interfaces, single in function, low in reuse rate and incapable of performing batch test. The system comprises a programmable logic array FPGA, a voltage converter, an IO level converter, an interface conversion circuit, a first network port chip, a second network port chip, an AD converter and a DA converter which are integrated on a board card, and unified scheduling and resource reconstruction are carried out through the FPGA. The test board card realizes comprehensive test and performance analysis of power supply, digital IO, serial communication, network communication and AD / DA signal chains of various radar signal processing board cards through programmable configuration, so that a single hardware platform is used for replacing various special test devices. The system is rich in interface, high in reusability, high in test efficiency and wide in application range, can greatly reduce the test cost and the development period, remarkably improves the test coverage rate and the resource reuse rate, and can be used for function verification and signal performance analysis of embedded hardware in radar signal processing.