16 results about "Programmable logic array" patented technology

Examples herein describe a three-dimensional (3D) die stack. The 3D die stack includes a programmable logic (PL) die and a computing die stacked on top of the PL die. The PL die includes a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die. The computing die includes a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the computing die. The three-dimensional die stack includes a plurality of tiles, each tile including M configurable blocks included in the plurality of configurable blocks and N data processing engines included in the plurality of data processing engines.

This application discloses a control system for a controllable vibration source, belonging to the field of controllable vibration sources. This control system achieves precise control of the controllable vibration source through a host computer and a system-on-a-chip (SoC) integrating a processor and a programmable logic array (PLA). The host computer transmits configuration information to the PCA, where the processor generates a reference scan signal based on the configuration information. The processor then controls the vibrator of the controllable vibration source to perform vibration operations based on the reference scan signal. Furthermore, to ensure that the vibration signal generated by the vibrator meets requirements, a control algorithm can be executed through the PCA to generate control signals. These control signals can then be used to precisely adjust the vibration signal generated by the vibrator, thus achieving precise control of the controllable vibration source.

The invention discloses train control vehicle-mounted equipment, which comprises two main control subsystems, and each main control subsystem comprises a safety controller module. The safety controller module is composed of symmetrical physical double channels, and each channel comprises an independent voltage system, an SOC system, a storage system, a communication interface, an IO interface, a panel connector and a backboard connector. The SOC system comprises a single chip, the single chip comprises a processing system and a programmable logic array, the processing system is used for undertaking operation system scheduling management, peripheral communication management and logic operation functions, and the programmable logic array is used for undertaking clock distribution, bottom layer driving and implementation of a general protocol. According to the equipment provided by the invention, the integration level of the SOC system is relatively high, and the processing performance is improved based on the integration level, so that the processing performance can meet ever-increasing control requirements.

In accordance with various embodiments of the present disclosure, a programmable logic array circuit is provided. In some embodiments, the programmable logic array circuit comprises an AND plane comprising a plurality of groups of product term straps, an OR plane comprising a plurality of output lines, a first plurality of dynamically driven shield lines in the AND plane, and a second plurality of dynamically driven shield lines in the OR plane. Each of the plurality of groups of product term straps is adjacent to only one corresponding one of the first plurality of dynamically driven shield lines. Each of the plurality of output lines is adjacent to only one corresponding one of the second plurality of dynamically driven shield lines.

This paper discloses a method, computer storage medium, and terminal for implementing self-testing. In this embodiment, a first acquisition function unit and a second acquisition function unit are instantiated inside a field-programmable logic array (FPGA). After inputting analog signals to the first and second acquisition function units, the input of the i-th acquisition processing channel of the first acquisition function unit is adjusted to a preset waveform occupied by the track. By comparing the output results of the acquisition processing performed by the first and second acquisition function units, the self-testing function of the track circuit signal acquisition module is realized.

Examples herein describe a three-dimensional (3D) die stack. The 3D die stack includes a programmable logic (PL) die and a compute die stacked on top of the PL die. The PL die includes a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die. The compute die includes a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the compute die. The three-dimensional die stack includes a plurality of tiles, each tile comprising M configurable blocks included in the plurality of configurable blocks and N data processing engines included in the plurality of data processing engines.

The application discloses a logic control method and system of a programmable controller, and the method comprises the following steps: step 1, capturing discrete state transition events of a physical device in real time through a heterogeneous sensor network, generating a time-stamped asynchronous event stream, and filtering out steady-state redundant signals; step 2, constructing a temporary logic unit cluster in a programmable logic array according to the space-time correlation of the event stream, and each unit sharing an event context in real time and dynamically establishing a logic relationship mapping; step 3, triggering a distributed computing node based on the event type priority of the logic unit cluster, executing a preset control rule in parallel, generating a non-blocking control instruction set, and synchronously injecting an output buffer channel; and step 4, monitoring the deviation degree of an execution result and an expected state, automatically deconstructing a current logic unit cluster and recombining it into a new logic unit cluster that is topologically optimized when the deviation exceeds a threshold, and forming an adaptive control loop. The application significantly improves the control precision, response speed and system reliability of an automobile stamping production line.

The invention relates to a measurement method and circuit for improving ultrasonic flow measurement precision, and the method comprises the steps: receiving a start signal generated and output from the interior of a programmable logic array FPGA, and starting a flowmeter to trigger an enable signal; when the flow meter detects the rising edge of the starting signal, initializing the timing reference of flow measurement to zero time; performing time sequence analysis on the ultrasonic original echo signal through a time delay method, and determining a starting time node corresponding to the effective original data; based on the starting time node, filtering all invalid pulse signals in a time period from the zero moment to the starting time node; starting a signal acquisition process from a moment corresponding to the starting time node, and receiving an externally input pulse signal; accurate control over the measurement time sequence is achieved through the FPGA, time delay method time sequence analysis and a multi-stage pulse screening mechanism are combined, invalid signal interference is effectively filtered, and the effectiveness of original data is improved.

The invention relates to an image registration method and device, an electronic device and a storage medium, and the method comprises the steps: obtaining a to-be-registered video image, caching the to-be-registered video image to a programmable logic array, obtaining a target registration coordinate and a registration parameter, and carrying out the registration of the to-be-registered video image according to the target registration coordinate and the registration parameter. And determining a to-be-registered original image coordinate corresponding to the target registration coordinate in the to-be-registered video image, determining to-be-registered original image data corresponding to the to-be-registered original image coordinate in the to-be-registered video image, and determining a target video image corresponding to the to-be-registered video image according to the to-be-registered original image data and the target registration coordinate. Through the image registration method and device, the problem of how to quickly realize image registration without occupying memory bandwidth in related technologies is solved, time delay is reduced, the real-time performance of an image registration application scene is improved, resources are saved, and the cost is reduced.

The invention relates to the field of inner coating of small-diameter steel pipe sintered epoxy powder, in particular to a thermal management device of a small-diameter steel pipe sintered epoxy powder pipeline, which comprises a control unit, a refrigeration unit, a monitoring unit and an outer pipe. The control unit is installed outside the outer pipe and electrically connected to the refrigeration unit and the monitoring unit, reads monitoring information from the monitoring unit, sends alarm information and further sends control information to the refrigeration unit. The refrigeration unit is installed in the outer pipe, and the monitoring unit is arranged across the outer pipe and enters the steel pipe along with the outer pipe in the working process. And the powder conveying pipe is sleeved in the outer pipe. The refrigeration unit wraps the powder conveying pipe. The monitoring unit is attached to the powder conveying pipe. The invention also comprises a method. Through integration of a semiconductor refrigeration technology, a heat pipe heat conduction technology, a temperature sensor and a programmable logic array technology, effective heat management of the small-diameter steel pipe sintering epoxy powder inner coating powder conveying pipeline is achieved, and then the problems of powder blocking and caking caused by the too high temperature of the powder outlet end of the powder conveying pipe are thoroughly solved.

A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.

Examples herein describe a three-dimensional (3D) die stack. The 3D die stack includes a programmable logic (PL) die and a compute die stacked on top of the PL die. The PL die includes a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die. The compute die includes a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the compute die. The three-dimensional die stack includes a plurality of tiles, each tile comprising M configurable blocks included in the plurality of configurable blocks and N data processing engines included in the plurality of data processing engines.

A control system an unmanned vehicle includes a first processing unit configured to execute a primary autopilot process for controlling the unmanned vehicle. The control system further includes a programmable logic array in operative communication with the first processing unit. The control system also includes a state machine configured in the programmable logic array. The state machine is configured to enable control of the unmanned vehicle according to a backup autopilot process in response to an invalid output of the first processing unit.

The invention discloses a general test board card for a radar signal processing unit, and mainly solves the problems that an existing test device is deficient in interfaces, single in function, low in reuse rate and incapable of performing batch test. The system comprises a programmable logic array FPGA, a voltage converter, an IO level converter, an interface conversion circuit, a first network port chip, a second network port chip, an AD converter and a DA converter which are integrated on a board card, and unified scheduling and resource reconstruction are carried out through the FPGA. The test board card realizes comprehensive test and performance analysis of power supply, digital IO, serial communication, network communication and AD / DA signal chains of various radar signal processing board cards through programmable configuration, so that a single hardware platform is used for replacing various special test devices. The system is rich in interface, high in reusability, high in test efficiency and wide in application range, can greatly reduce the test cost and the development period, remarkably improves the test coverage rate and the resource reuse rate, and can be used for function verification and signal performance analysis of embedded hardware in radar signal processing.

The utility model relates to a binocular zoom camera, which belongs to the technical field of optical imaging and camera equipment and comprises a box body, two camera modules for receiving image information are arranged in an inner cavity of the box body, two threaded blocks are fixed at the top of the box body, and a central processing unit for receiving and processing images is arranged in the inner cavity of the box body. And the inner top wall of the box body is provided with a transmission mechanism for providing telescopic zooming power. According to the binocular zoom camera, through cooperation of the camera module and the central processing unit, images can be rapidly processed, through introduction of a highly customized algorithm framework support, the three-dimensional reconstruction speed is greatly improved, the power consumption pressure is greatly reduced, through cooperation of the transmission mechanism and the camera module, the coordination of the two eyes is remarkably improved, and the reconstruction efficiency is improved. And finally, a programmable logic array (PLD) with higher flexibility is introduced, so that the future rapid iteration upgrading is facilitated to meet the emerging application scene appeal, and the shooting quality is improved through the cooperation of the camera module and the central processing unit.

The invention discloses an airborne heterogeneous computing general control board card based on DSP and FPGA, which comprises a discrete magnitude circuit, an analog quantity circuit, a reset circuit, two external connectors, a DSP processor and an FPGA circuit, the input end of the DSP processor and the input end of the FPGA circuit are connected with a power supply circuit, the DSP processor and the FPGA circuit are in communication connection through Xintf, and the FPGA circuit is in communication connection with the DSP processor. An ADC interface of the DSP processor is connected with an ADC converter with a voltage stabilizer; the DSP is matched with the FPGA programmable logic array control architecture, 16-bit ADC conversion, Flash and RAM circuits are externally expanded, the functions of collection, data processing, storage, communication and data recording are integrated, the expansibility and universality are high, the FPGA is high in flexibility and has the parallel processing capacity, different application scenes and requirements can be adapted through reprogramming, and the application range is wide. And the comprehensive requirements of an airborne environment on high-intensity numerical calculation, strong real-time response and high-universality interface control are met.