135 results about "Transistor stacking" patented technology

Dipole engineering techniques for devices of stacked device structures are disclosed herein. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming a p-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives a p-dipole dopant from the p-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the p-dipole dopant source layer. A drive-in temperature of the thermal drive-in process is less than 600° C. (e.g., about 300° C. to about 500° C.). The p-dipole dopant can be titanium. The method can further include tuning thermal drive-in process parameters to provide the gate dielectric with a p-dipole dopant profile having a peak located at a high-k / interfacial interface ±0.5 nm.

Integrated circuit devices and methods of forming the same are provided. An integrated circuit device may include a substrate and a transistor stack on the substrate, the transistor stack including a first transistor and a second transistor on the first transistor. The first transistor may be between the substrate and the second transistor and the first transistor may include first and second source / drain regions, a first channel region between the first and second source / drain regions, and a first gate structure on the first channel region. A lower surface of the first source / drain region may be higher than a lower surface of the first gate structure relative to the substrate.

A multi-port memory cell has a write-only cell and a buffered read port. The write-only cell has cross-coupled inverters and transmission gates to write bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing but remain off for reading. A node in the cross-coupled inverters is applied to a gate of a buffer transistor that has a channel in series with a channel of a read pass transistor to a read bit line. The buffered read port can be an inverter and a transmission gate, or can have p-channel and n-channel buffer and pass transistors in a four-transistor stack. The number of p-channel and n-channel transistors can be equal for use in a standard-cell or macro library layout, and the standard-cell logic power supply can be used for the memory cells even for ultra-low supply voltages.

A semiconductor IC structure includes a stacked transistor that has a top transistor stacked upon a bottom transistor. The bottom transistor includes at least a bottom source / drain region. The semiconductor IC structure further includes a replacement bottom source / drain region contact that includes a deep via region through at least the top semiconductor IC device and a monolithic region within the bottom semiconductor IC device directly coupled against a top surface of the bottom source / drain region. There is no interfacial impedance between the deep via region and the monolithic region. For example, there is no liner (e.g., such as a diffusion barrier, adhesion liner, or the like) between the deep via region and the monolithic region.

An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor and a second transistor stacked vertically. A conductive via extends vertically from a first source / drain region of the first transistor past the second transistor. The second transistor includes an asymmetric second source / drain region. The asymmetry of the second source / drain region helps ensure that the second source / drain region does not contact the conductive via.

Described herein are memory cells that include two transistors stacked above one another above a support structure where neither one of the transistors is coupled to a capacitor and where at least one of the two transistors is a thin-film transistor. In such 2T capacitorless memory cells, a first transistor may be referred to a write transistor, and a second transistor may be a read transistor. The first transistor may be a three-terminal device having two S / D terminals and a gate terminal, while the second transistor may be a four-terminal device having two S / D terminals and two gate terminals.

Integrated circuitry comprising high voltage (HV) and low voltage (LV) ribbon or wire (RoW) transistor stack structures. In some examples, a gate electrode of the HV and LV transistor stack structures may include the same work function metal. A metal oxide may be deposited around one or more channels of the HV transistor stack, thereby altering the dipole properties of the gate insulator stack from those of the LV transistor stack structure.

Integrated circuitry comprising a ribbon or wire (RoW) transistor stack structure including a plurality of individual source and / or drain material bodies of a same conductivity type. A metallization interfaces with an individual one of the source and / or drain material bodies, achieving a larger interface area for lower contact resistance. In some examples, a source and / or drain material protrusion is formed at opposite ends of each of a plurality of channel structures. The protrusions may be of a first composition, such as p-type SiGex for a PMOS device. The protrusions may then be augmented into larger bodies through the formation of another layer of material, such as SiGey for a PMOS device, where y is larger than x. In some further examples, an outer layer of an individual layered source and / or drain body may be enriched with Ga (e.g., SiGe:Ga) to further reduce contact resistance of a transistor stack structure.

Dipole engineering techniques for devices of stacked device structures are disclosed herein. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming an n-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives an n-dipole dopant from the n-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the n-dipole dopant source layer. A drive-in temperature of the thermal drive-in process is less than 600° C. (e.g., about 300°° C. to about 500°° C.). The n-dipole dopant is strontium, erbium, magnesium, or a combination thereof. The method can further include tuning thermal drive-in process parameters to provide the gate dielectric with an n-dipole dopant profile having a peak located at a high- k / interfacial interface ±0.5 nm.

A switch circuit includes first and second transistor stacks coupled in parallel between first and second ports. The first transistor stack includes a first plurality of transistors coupled in series between the first and second ports to provide a first variably-conductive path between the first and second ports. A first network of one or more balancing capacitors includes a first capacitor coupled across multiple transistors of the first plurality of transistors. The second transistor stack includes a second plurality of transistors coupled in series between the first and second ports to provide a second variably-conductive path between the first and second ports. A second network of one or more balancing capacitors includes a second capacitor coupled across multiple transistors of the second plurality of transistors.

A high voltage driver is provided that includes a PMOS stack of transistors arranged in series between a power supply node and an output node. The high voltage driver also includes an NMOS stack of transistors arranged between the output node and ground.

The application provides a static random access memory structure and a preparation method thereof. The static random access memory structure comprises a substrate, an isolation structure, at least two static random access memory cells sharing a word line, and a plurality of active regions defined by the isolation structure on the substrate. Each static random access memory cell comprises at least two inverter groups and at least two transfer transistor groups. Each inverter group comprises two inverters cross-coupled, each inverter being formed by a pull-up transistor and a pull-down transistor stacked in the same active region along the vertical direction of the substrate. The plurality of active regions comprises at least two common regions shared by different static random access memory cells. Each transfer transistor group is formed by two transfer transistors stacked in the same common region along the vertical direction of the substrate, and the two transfer transistors in the same common region belong to different static random access memory cells. Thus, the coupled two static random access memory cells save 50% of the area.

The application provides a preparation method of a stacked transistor, a stacked transistor and a semiconductor device. The method comprises: etching a fin structure on a semiconductor substrate in one time, wherein the fin structure comprises a first part and a second part stacked along a first direction, and the first part is farther away from the semiconductor substrate than the second part; forming a first transistor based on the first part, wherein the first transistor comprises: a first gate structure formed by a first gate preparation process; removing the semiconductor substrate; and forming a second transistor stacked along the first direction with the first transistor based on the second part, wherein the second transistor comprises: a second gate structure formed by a second gate preparation process; the second gate preparation process and the first gate preparation process are different at least in preparation steps; and a heat resistance of the first gate structure is greater than a heat resistance of the second gate structure.

An integrated circuit includes a first temperature-sensitive device having a first stacked gate device formed and a second stacked gate device, and a second temperature-sensitive device having a third stacked gate device. The first temperature-sensitive device is configured to generate a first voltage which monotonically increases with an absolute temperature. The second temperature-sensitive device is configured to generate a second voltage which monotonically decreases with the absolute temperature. The integrated circuit also includes an output terminal configured to generate a reference voltage which is based on the first voltage from the first temperature-sensitive device and the second voltage from the second temperature-sensitive device. Each of the first stacked gate device, the second stacked gate device, and the third stacked gate device is formed with a first group of field-effect transistors stacked together.

A transistor stack circuit including a first signal transmission port, a second signal transmission port, an impedance unit, a plurality of transistors, and a plurality of resistors is provided. The transistors are connected in series and coupled between the first signal transmission port and the second signal transmission port. A first terminal of each resistor is coupled to a common path. A second terminal of each resistor is coupled to a control terminal of a corresponding transistor among the transistors. The impedance unit is coupled between the common path and a reference voltage terminal. When an electrostatic discharge event occurs, an impedance value of the impedance unit is greater than twice of a resistance value of each resistor, and the transistors form a low-impedance path.

The embodiment of the invention provides a semiconductor structure. The semiconductor structure includes: a first transistor having a first source / drain (S / D) region; a second transistor having a second S / D region, the second transistor stacked on top of the first transistor; and a first S / D contact shared by the first S / D region of the first transistor and the second S / D region of the second transistor, where the first S / D contact has a first portion in direct contact with a top surface of the first S / D region of the first transistor and a second portion in direct contact with a bottom surface of the second S / D region of the second transistor, and the second portion is in direct contact with an inner sidewall of the second S / D region of the second transistor. A method of manufacturing a semiconductor structure is also provided.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a stack of transistors including a second transistor on top of a first transistor on a substrate, the first and the second transistor each having a first source / drain (S / D) region with the first S / D region of the second transistor being on top of the first S / D region of the first transistor; and a shared S / D contact with the shared S / D contact having a first portion being wrapped around by the first S / D region of the first transistor and a second portion being wrapped around by the first S / D region of the second transistor. A method of forming the same is also provided.

A voltage generator includes a temperature-dependent voltage generator and a reference voltage node. The temperature-dependent voltage generator generates a voltage that increases with temperature and includes a first transistor stack and a second transistor stack, each of which has a first source / drain terminal and a gate terminal connected to each other at a temperature-dependent voltage generator node. The reference voltage node is connected to the temperature-dependent voltage generator and provides a reference voltage substantially independent of temperature. A method for generating the temperature-independent reference voltage is also disclosed.

A stacked semiconductor structure including a top transistor stacked above a bottom transistor, and a single gate contact in electrical contact with a top gate conductor of the top transistor and a bottom gate conductor of the bottom transistor.

A method for fabricating a semiconductor device is disclosed, the method comprising: forming a first stack of a first transistor structure on a substrate; and forming a second stack of a second transistor structure adjacent to the first stack on the substrate. The second stack is formed adjacent to the first stack such that a stacked S / D region at one end of the first stack faces a corresponding stacked S / D region at one end of the second stack. A first pair of facing S / D regions of the first stack and the second stack are connected by forming an interconnect structure extending horizontally to physically connect the first pair of facing S / D regions to each other. Second pairs of facing S / D regions of the first stack and the second stack are maintained as a pair of physically separated facing S / D regions. A first metal interconnect structure and a second metal interconnect structure are connected to corresponding S / D regions in the second pair of facing S / D regions.

This application relates to thin-film transistor stack selection in a memory device. The memory device may include memory arrays disposed in a stack of layers formed over a substrate, and stack selection components distributed between the layers to utilize a shared substrate-based circuitry. For example, each memory array in the stack may include a set of digital lines corresponding to the stack, and a stack selection circuitry operable to couple the set of digital lines to a column decoder shared across multiple stacks. To access a memory cell in a selected memory array on one stack, the stack selection circuitry corresponding to that memory array can be activated, while the stack selection circuitry corresponding to a non-selected memory array on another stack can be deactivated. The stack selection circuitry, such as transistors, may utilize thin-film fabrication techniques, such as various techniques for forming vertical transistors.

A semiconductor device and a manufacturing method thereof, and an electronic apparatus, the semiconductor device comprising: at least one memory cell, the memory cell comprising a first transistor and a second transistor which are vertically stacked, the first transistor and the second transistor being vertical channel transistors; a second semiconductor layer of the second transistor is connected to a first gate electrode of the first transistor; the first semiconductor layer of the first transistor comprises a first vertical part which vertically extends; the second semiconductor layer of the second transistor comprises a second vertical part which vertically extends; the first gate electrode is distributed on the side wall of the first vertical part, the first electrode and the third electrode extend along a first direction parallel to the substrate, and the second gate electrode and the third gate electrode extend along a second direction parallel to the substrate; the first direction and the second direction intersect. According to the scheme provided by the embodiment of the invention, the storage unit comprises the two vertical channel transistors which are vertically stacked, so that the area of the storage unit can be reduced, and high-density integration can be realized.

A method of operating a non-volatile memory device, wherein the non-volatile memory device includes a cell string, wherein the cell string includes a plurality of cell transistors stacked in a direction perpendicular to a substrate in series between a bit line and a common source line, the method comprising: programming an erase control transistor in the plurality of cell transistors; and after the erase control transistor is programmed, applying an erase voltage to the common source line or the bit line and applying an erase control voltage to an erase control line connected to the erase control transistor, wherein the erase control voltage is less than the erase voltage and greater than a ground voltage, and wherein the erase control transistor is between a ground select transistor in the plurality of cell transistors and the common source line or between a string select transistor in the plurality of cell transistors and the bit line.

The present disclosure provides a semiconductor device, an electronic device, a transistor stack, and a manufacturing method therefor. The manufacturing method comprises: forming a stack structure by one etching on a semiconductor substrate; forming, on the semiconductor substrate, an oxide layer covering the stack structure; forming, within a gate region of the transistor stack, a dummy gate structure covering the oxide layer; forming a first transistor on the basis of a first active structure covered with the oxide layer; flipping the wafer and removing the semiconductor substrate; forming a second transistor on the basis of a second active structure covered with the oxide layer; and oxidizing a first portion of a first dummy gate structure to form a first gate isolation structure between a first gate structure and a second gate structure; and / or oxidizing a first portion of a second dummy gate structure to form a second gate isolation structure between the first gate structure and the second gate structure.

The invention discloses a stacked power amplifier based on transformer synthesis, and aims to solve the problem that the output power, synthesis efficiency and dynamic reliability of a power amplifier are difficult to synergistically improve under a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process. The amplifier adopts a symmetrical double-branch architecture and comprises a T-shaped power distribution network, two power amplification branches and a T-shaped power synthesis network. The power amplifier is characterized in that each power amplification branch comprises an amplifier adopting a multi-transistor stacking topology, and grids of stacked transistors are biased or coupled through a series capacitor so as to realize dynamic voltage distribution in a radio frequency period; the T-type transformer distribution / synthesis network and the stacked amplification branch adopting the capacitor dynamic voltage division work cooperatively, and unification of high output power, high synthesis efficiency and high working reliability is achieved jointly. Through the collaborative design of the architecture and the circuit level, the performance bottleneck in the traditional design is effectively broken through, and the method is suitable for high-frequency and high-power wireless communication systems such as 5G, Internet of Things and the like.

A method for microfabrication of a three-dimensional transistor stack with a gate-all-around field-effect transistor device. Channels are suspended between source and drain regions. Each channel is selectively deposited with a material layer designed to adjust the threshold voltage of the channel. These layers can be oxides, high-k materials, work function materials, and metallizations. The three-dimensional transistor stack forms an array of high-threshold-voltage devices and low-threshold-voltage devices in a single package.

A semiconductor device including a second nanosheet transistor stacked over a first nanosheet transistor is provided which accommodates for having source / drain separating dielectric layers and / or stacked source / drain regions having a wide variety of vertical heights. The wide variety of heights can be along the same source / drain canyon or across different source / drain canyons.

A three-dimensional stacked field-effect transistor including a silicon substrate; a partial bottom dielectric isolation layer on the silicon substrate; a punch through stopper layer on the silicon substrate and on opposite sides of the partial bottom dielectric isolation layer; a first transistor on the partial bottom dielectric isolation layer and the punch through stopper layer; and a second transistor stacked on the first transistor. Each of the first transistor and the second transistor includes a channel, a source region on one side of the channel, and a drain region on another side of the channel. The partial bottom dielectric isolation layer is below the channel of the first transistor. The punch through stopper layer is below the source region and the drain region of the first transistor.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a stack of transistors with a first transistor on top of a second transistor, where a gate of the first transistor has a first width; a gate of the second transistor has a second width; and the first width is narrower than the second width, and where the first and the second transistor respectively have a first gate extension at a first side of the stack and a second gate extension at a second side of the stack, the first gate extension at the first side of the stack being narrower than the second gate extension at the second side of the stack, with the first side being opposite the second side. A method of manufacturing the semiconductor structure is also provided.

A semiconductor device includes a top transistor stacked over a bottom transistor. The top transistor comprises horizontally oriented nanosheet gates, and the bottom transistor comprises vertically oriented nanosheet gates. The top transistor and the bottom transistor are staggered.