195 results about "Transistor stacking" patented technology

Dipole engineering techniques for devices of stacked device structures are disclosed herein. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming a p-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives a p-dipole dopant from the p-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the p-dipole dopant source layer. A drive-in temperature of the thermal drive-in process is less than 600° C. (e.g., about 300° C. to about 500° C.). The p-dipole dopant can be titanium. The method can further include tuning thermal drive-in process parameters to provide the gate dielectric with a p-dipole dopant profile having a peak located at a high-k / interfacial interface ±0.5 nm.

A radio frequency (RF) switch includes a transistor stack with different sections having different configurations for achieving different parasitic capacitances. Specifically, a first section is connected to an input terminal and a second section is connected between the first section and an output terminal. The second section has over-gate gaps for reduced source-to-drain capacitance, whereas the first section does not. Additionally, gate-to-source / drain contact spacing can be larger in the second section than in the first section, transistor layout length can be longer in the second section than in the first section and / or source and drain interconnect interdigitation can be less in the second section than in the first section. Optionally, sub-sections of the series-connected transistors within the first and / or second sections also have different configurations. Thus, numbers and sizes of compensation capacitors within the switch and overall chip area consumed by the switch are reduced while maintaining a high Pmax.

Transistor devices are provided. A transistor device includes a substrate and a transistor stack on the substrate. The transistor stack includes a lower transistor and an upper transistor that is on top of the lower transistor. Moreover, the transistor device includes a gate-cut on the substrate, adjacent the transistor stack. The gate-cut has a first sloped sidewall and a second sloped sidewall that is opposite the first sloped sidewall. Related methods of forming transistor devices are also provided.

A semiconductor device is provided and includes a first transistor including a first source / drain (S / D) region, a second transistor stacked over the first transistor and including a second S / D region, a first backside power rail (BPR) disposed below the first transistor, a second BPR disposed below the first BPR, a via by which the second S / D region and the first BPR are connected and metallization. The metallization passes through and is insulated from the first BPR. The first S / D region and the second BPR are connected by the metallization.

Front end systems and related devices, integrated circuits, modules, and methods are disclosed. One such front end system includes a low noise amplifier in a receive path and a multi-mode power amplifier circuit in a transmit path. The low noise amplifier includes a first inductor, an amplification circuit, and a second inductor magnetically coupled to the first inductor to provide negative feedback to linearize the low noise amplifier. The multi-mode power amplifier circuit includes a stacked output stage including a transistor stack of two or more transistors. The multi-mode power amplifier circuit also includes a bias circuit configured to control a bias of at least one transistor of the transistor stack based on a mode of the multi-mode power amplifier circuit. Other embodiments of front end systems are disclosed, along with related devices, integrated circuits, modules, methods, and components thereof.

The invention discloses an ultra-wideband high-linearity phased array switch, which comprises three ports, namely a transmitting end TX port, an antenna end ANT port and a receiving end RX port, and is characterized in that when a transmitting branch is switched on, a signal is transmitted from the TX port to the ANT port; when the receiving branch is conducted, a signal is transmitted from the ANT port to the RX port; the transmitting branch comprises a matching inductor L2, a transistor M5, a transistor M6, a transistor M1, a transistor M2 and a matching inductor L1, the receiving branch comprises a matching inductor L1, a transistor M3, a transistor M4, a transistor M7, a transistor M8 and a matching inductor L3, the proposed switch is designed by adopting a classic series-parallel structure, a deep N-well NMOS (N-channel Metal Oxide Semiconductor) transistor is used, and the matching inductor L1, the transistor M5, the transistor M6, the transistor M1, the transistor M2 and the matching inductor L3 are matched. The isolation degree of the transistor of the turn-off branch is improved by adopting a negative body bias technology, and meanwhile, the power processing capacity of the turn-off transistor is improved by adopting a negative voltage bias technology and a transistor stacking technology together.

Integrated circuit devices and methods of forming the same are provided. An integrated circuit device may include a substrate and a transistor stack on the substrate, the transistor stack including a first transistor and a second transistor on the first transistor. The first transistor may be between the substrate and the second transistor and the first transistor may include first and second source / drain regions, a first channel region between the first and second source / drain regions, and a first gate structure on the first channel region. A lower surface of the first source / drain region may be higher than a lower surface of the first gate structure relative to the substrate.

A multi-port memory cell has a write-only cell and a buffered read port. The write-only cell has cross-coupled inverters and transmission gates to write bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing but remain off for reading. A node in the cross-coupled inverters is applied to a gate of a buffer transistor that has a channel in series with a channel of a read pass transistor to a read bit line. The buffered read port can be an inverter and a transmission gate, or can have p-channel and n-channel buffer and pass transistors in a four-transistor stack. The number of p-channel and n-channel transistors can be equal for use in a standard-cell or macro library layout, and the standard-cell logic power supply can be used for the memory cells even for ultra-low supply voltages.

A semiconductor IC structure includes a stacked transistor that has a top transistor stacked upon a bottom transistor. The bottom transistor includes at least a bottom source / drain region. The semiconductor IC structure further includes a replacement bottom source / drain region contact that includes a deep via region through at least the top semiconductor IC device and a monolithic region within the bottom semiconductor IC device directly coupled against a top surface of the bottom source / drain region. There is no interfacial impedance between the deep via region and the monolithic region. For example, there is no liner (e.g., such as a diffusion barrier, adhesion liner, or the like) between the deep via region and the monolithic region.

A semiconductor device is provided that includes at least one stacked FET device including two top transistors stacked over a single bottom transistor. The at least one stacked FET includes a full gate cut structure that is used to separate different device areas from each other, a top gate cut structure that used to separate the two top transistors, and a bottom gate cut structure that is used to provide the single bottom transistor. The at least one FET device can be used to provide a SRAM containing six transistors.

Embodiments of present invention provide a SRAM memory. The SRAM memory includes a frontside and a backside; a first pull-up (PU) transistor stacked over a first pull-down (PD) transistor; a second PU transistor stacked over a second PD transistor; a frontside cross-couple at the frontside, above the first and second PU transistors, that connects a first source / drain (S / D) region of the first PU transistor with a gate of the second PU transistor; and a backside cross-couple, at the backside underneath the first and second PD transistors, that connects a first S / D region of the second PD transistor with a gate of the first PD transistor. A method of manufacturing the SRAM memory is also provided.

An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor and a second transistor stacked vertically. A conductive via extends vertically from a first source / drain region of the first transistor past the second transistor. The second transistor includes an asymmetric second source / drain region. The asymmetry of the second source / drain region helps ensure that the second source / drain region does not contact the conductive via.

Described herein are memory cells that include two transistors stacked above one another above a support structure where neither one of the transistors is coupled to a capacitor and where at least one of the two transistors is a thin-film transistor. In such 2T capacitorless memory cells, a first transistor may be referred to a write transistor, and a second transistor may be a read transistor. The first transistor may be a three-terminal device having two S / D terminals and a gate terminal, while the second transistor may be a four-terminal device having two S / D terminals and two gate terminals.

Transistor devices are provided. A transistor device includes a substrate and a transistor stack including first and second transistors on the substrate. The first transistor or the second transistor includes a plurality of semiconductor channel layers, a gate on the plurality of semiconductor channel layers, and an insulating spacer that is on a sidewall of the gate and between the plurality of semiconductor channel layers. Moreover, the insulating spacer includes: a first portion on a sidewall of the gate; and a second portion that is spaced apart from the sidewall of the gate by the first portion, and that has a lower dielectric constant than the first portion. Related methods of forming transistor devices are also provided.

Integrated circuitry comprising high voltage (HV) and low voltage (LV) ribbon or wire (RoW) transistor stack structures. In some examples, a gate electrode of the HV and LV transistor stack structures may include the same work function metal. A metal oxide may be deposited around one or more channels of the HV transistor stack, thereby altering the dipole properties of the gate insulator stack from those of the LV transistor stack structure.

Integrated circuitry comprising a ribbon or wire (RoW) transistor stack structure including a plurality of individual source and / or drain material bodies of a same conductivity type. A metallization interfaces with an individual one of the source and / or drain material bodies, achieving a larger interface area for lower contact resistance. In some examples, a source and / or drain material protrusion is formed at opposite ends of each of a plurality of channel structures. The protrusions may be of a first composition, such as p-type SiGex for a PMOS device. The protrusions may then be augmented into larger bodies through the formation of another layer of material, such as SiGey for a PMOS device, where y is larger than x. In some further examples, an outer layer of an individual layered source and / or drain body may be enriched with Ga (e.g., SiGe:Ga) to further reduce contact resistance of a transistor stack structure.

Transistor devices are provided. A transistor device includes a substrate and a transistor stack on the substrate. The transistor stack includes a lower transistor and an upper transistor that is on top of the lower transistor. Moreover, the transistor device includes an isolation region that separates the upper transistor from the lower transistor. The isolation region has a dielectric constant that is lower than that of silicon nitride and lower than that of silicon boron carbonitride. Related methods of forming transistor devices are also provided.

Dipole engineering techniques for devices of stacked device structures are disclosed herein. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming an n-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives an n-dipole dopant from the n-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the n-dipole dopant source layer. A drive-in temperature of the thermal drive-in process is less than 600° C. (e.g., about 300°° C. to about 500°° C.). The n-dipole dopant is strontium, erbium, magnesium, or a combination thereof. The method can further include tuning thermal drive-in process parameters to provide the gate dielectric with an n-dipole dopant profile having a peak located at a high- k / interfacial interface ±0.5 nm.

A switch circuit includes first and second transistor stacks coupled in parallel between first and second ports. The first transistor stack includes a first plurality of transistors coupled in series between the first and second ports to provide a first variably-conductive path between the first and second ports. A first network of one or more balancing capacitors includes a first capacitor coupled across multiple transistors of the first plurality of transistors. The second transistor stack includes a second plurality of transistors coupled in series between the first and second ports to provide a second variably-conductive path between the first and second ports. A second network of one or more balancing capacitors includes a second capacitor coupled across multiple transistors of the second plurality of transistors.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a dynamic random-access-memory (DRAM), and the DRAM includes a vertical transistor and a nanosheet transistor, the vertical transistor being stacked on top of the nanosheet transistor, where a bottom source / drain of the vertical transistor is directly above and connected to a gate of the nanosheet transistor through a conductive via. A method of manufacturing the semiconductor structure is also provided.

A high voltage driver is provided that includes a PMOS stack of transistors arranged in series between a power supply node and an output node. The high voltage driver also includes an NMOS stack of transistors arranged between the output node and ground.

The application provides a static random access memory structure and a preparation method thereof. The static random access memory structure comprises a substrate, an isolation structure, at least two static random access memory cells sharing a word line, and a plurality of active regions defined by the isolation structure on the substrate. Each static random access memory cell comprises at least two inverter groups and at least two transfer transistor groups. Each inverter group comprises two inverters cross-coupled, each inverter being formed by a pull-up transistor and a pull-down transistor stacked in the same active region along the vertical direction of the substrate. The plurality of active regions comprises at least two common regions shared by different static random access memory cells. Each transfer transistor group is formed by two transfer transistors stacked in the same common region along the vertical direction of the substrate, and the two transfer transistors in the same common region belong to different static random access memory cells. Thus, the coupled two static random access memory cells save 50% of the area.

The application provides a preparation method of a stacked transistor, a stacked transistor and a semiconductor device. The method comprises: etching a fin structure on a semiconductor substrate in one time, wherein the fin structure comprises a first part and a second part stacked along a first direction, and the first part is farther away from the semiconductor substrate than the second part; forming a first transistor based on the first part, wherein the first transistor comprises: a first gate structure formed by a first gate preparation process; removing the semiconductor substrate; and forming a second transistor stacked along the first direction with the first transistor based on the second part, wherein the second transistor comprises: a second gate structure formed by a second gate preparation process; the second gate preparation process and the first gate preparation process are different at least in preparation steps; and a heat resistance of the first gate structure is greater than a heat resistance of the second gate structure.

The invention discloses a three-dimensional memory device and a manufacturing method thereof. A semiconductor structure includes a plurality of layers of a transistor stacked in a vertical direction. Each layer of transistors includes: a first array of transistors sharing a first common first type of terminal line; and a second transistor array sharing a second common first type terminal line. The first transistor array and the second transistor array share a common second type terminal line. The semiconductor structure further includes a first common first type terminal contact structure coupled with the first common first type terminal line in the first first type terminal contact region, a second common first type terminal contact structure coupled with the second common first type terminal line in the second first type terminal contact region; and a common second type terminal contact structure coupled with the common second type terminal line in the common second type terminal contact region.

The invention provides a semiconductor structure and a forming method thereof. The forming method comprises the following steps: providing a substrate; forming a memory cell on the substrate, wherein the memory cell comprises a first transistor and a second transistor which are used as pull-down transistors, a third transistor and a fourth transistor which are used as pull-up transistors, and a fifth transistor and a sixth transistor which are used as transmission gate transistors; wherein the first transistor and the third transistor are stacked, the top of a first grid electrode of the first transistor is connected with the bottom of a third grid electrode of the third transistor, and the first grid electrode and a fifth grid electrode of the fifth transistor share a channel layer; the second transistor and the fourth transistor are stacked, the top of a second grid electrode of the second transistor is connected with the bottom of a fourth grid electrode of the fourth transistor, and the second grid electrode of the second transistor and a sixth grid electrode of the sixth transistor share a channel layer. According to the technical scheme, the integration level of the semiconductor structure can be improved.

An integrated circuit includes a first temperature-sensitive device having a first stacked gate device formed and a second stacked gate device, and a second temperature-sensitive device having a third stacked gate device. The first temperature-sensitive device is configured to generate a first voltage which monotonically increases with an absolute temperature. The second temperature-sensitive device is configured to generate a second voltage which monotonically decreases with the absolute temperature. The integrated circuit also includes an output terminal configured to generate a reference voltage which is based on the first voltage from the first temperature-sensitive device and the second voltage from the second temperature-sensitive device. Each of the first stacked gate device, the second stacked gate device, and the third stacked gate device is formed with a first group of field-effect transistors stacked together.

A transistor stack circuit including a first signal transmission port, a second signal transmission port, an impedance unit, a plurality of transistors, and a plurality of resistors is provided. The transistors are connected in series and coupled between the first signal transmission port and the second signal transmission port. A first terminal of each resistor is coupled to a common path. A second terminal of each resistor is coupled to a control terminal of a corresponding transistor among the transistors. The impedance unit is coupled between the common path and a reference voltage terminal. When an electrostatic discharge event occurs, an impedance value of the impedance unit is greater than twice of a resistance value of each resistor, and the transistors form a low-impedance path.

Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.

The embodiment of the invention provides a semiconductor structure. The semiconductor structure includes: a first transistor having a first source / drain (S / D) region; a second transistor having a second S / D region, the second transistor stacked on top of the first transistor; and a first S / D contact shared by the first S / D region of the first transistor and the second S / D region of the second transistor, where the first S / D contact has a first portion in direct contact with a top surface of the first S / D region of the first transistor and a second portion in direct contact with a bottom surface of the second S / D region of the second transistor, and the second portion is in direct contact with an inner sidewall of the second S / D region of the second transistor. A method of manufacturing a semiconductor structure is also provided.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a stack of transistors including a second transistor on top of a first transistor on a substrate, the first and the second transistor each having a first source / drain (S / D) region with the first S / D region of the second transistor being on top of the first S / D region of the first transistor; and a shared S / D contact with the shared S / D contact having a first portion being wrapped around by the first S / D region of the first transistor and a second portion being wrapped around by the first S / D region of the second transistor. A method of forming the same is also provided.