73 results about "Transistor stacking" patented technology

Described herein are memory cells that include two transistors stacked above one another above a support structure where neither one of the transistors is coupled to a capacitor and where at least one of the two transistors is a thin-film transistor. In such 2T capacitorless memory cells, a first transistor may be referred to a write transistor, and a second transistor may be a read transistor. The first transistor may be a three-terminal device having two S / D terminals and a gate terminal, while the second transistor may be a four-terminal device having two S / D terminals and two gate terminals.

A high voltage driver is provided that includes a PMOS stack of transistors arranged in series between a power supply node and an output node. The high voltage driver also includes an NMOS stack of transistors arranged between the output node and ground.

The application provides a static random access memory structure and a preparation method thereof. The static random access memory structure comprises a substrate, an isolation structure, at least two static random access memory cells sharing a word line, and a plurality of active regions defined by the isolation structure on the substrate. Each static random access memory cell comprises at least two inverter groups and at least two transfer transistor groups. Each inverter group comprises two inverters cross-coupled, each inverter being formed by a pull-up transistor and a pull-down transistor stacked in the same active region along the vertical direction of the substrate. The plurality of active regions comprises at least two common regions shared by different static random access memory cells. Each transfer transistor group is formed by two transfer transistors stacked in the same common region along the vertical direction of the substrate, and the two transfer transistors in the same common region belong to different static random access memory cells. Thus, the coupled two static random access memory cells save 50% of the area.

An integrated circuit includes a first temperature-sensitive device having a first stacked gate device formed and a second stacked gate device, and a second temperature-sensitive device having a third stacked gate device. The first temperature-sensitive device is configured to generate a first voltage which monotonically increases with an absolute temperature. The second temperature-sensitive device is configured to generate a second voltage which monotonically decreases with the absolute temperature. The integrated circuit also includes an output terminal configured to generate a reference voltage which is based on the first voltage from the first temperature-sensitive device and the second voltage from the second temperature-sensitive device. Each of the first stacked gate device, the second stacked gate device, and the third stacked gate device is formed with a first group of field-effect transistors stacked together.

The embodiment of the invention provides a semiconductor structure. The semiconductor structure includes: a first transistor having a first source / drain (S / D) region; a second transistor having a second S / D region, the second transistor stacked on top of the first transistor; and a first S / D contact shared by the first S / D region of the first transistor and the second S / D region of the second transistor, where the first S / D contact has a first portion in direct contact with a top surface of the first S / D region of the first transistor and a second portion in direct contact with a bottom surface of the second S / D region of the second transistor, and the second portion is in direct contact with an inner sidewall of the second S / D region of the second transistor. A method of manufacturing a semiconductor structure is also provided.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a stack of transistors including a second transistor on top of a first transistor on a substrate, the first and the second transistor each having a first source / drain (S / D) region with the first S / D region of the second transistor being on top of the first S / D region of the first transistor; and a shared S / D contact with the shared S / D contact having a first portion being wrapped around by the first S / D region of the first transistor and a second portion being wrapped around by the first S / D region of the second transistor. A method of forming the same is also provided.

A voltage generator includes a temperature-dependent voltage generator and a reference voltage node. The temperature-dependent voltage generator generates a voltage that increases with temperature and includes a first transistor stack and a second transistor stack, each of which has a first source / drain terminal and a gate terminal connected to each other at a temperature-dependent voltage generator node. The reference voltage node is connected to the temperature-dependent voltage generator and provides a reference voltage substantially independent of temperature. A method for generating the temperature-independent reference voltage is also disclosed.

A stacked semiconductor structure including a top transistor stacked above a bottom transistor, and a single gate contact in electrical contact with a top gate conductor of the top transistor and a bottom gate conductor of the bottom transistor.

A method for fabricating a semiconductor device is disclosed, the method comprising: forming a first stack of a first transistor structure on a substrate; and forming a second stack of a second transistor structure adjacent to the first stack on the substrate. The second stack is formed adjacent to the first stack such that a stacked S / D region at one end of the first stack faces a corresponding stacked S / D region at one end of the second stack. A first pair of facing S / D regions of the first stack and the second stack are connected by forming an interconnect structure extending horizontally to physically connect the first pair of facing S / D regions to each other. Second pairs of facing S / D regions of the first stack and the second stack are maintained as a pair of physically separated facing S / D regions. A first metal interconnect structure and a second metal interconnect structure are connected to corresponding S / D regions in the second pair of facing S / D regions.

A semiconductor device and a manufacturing method thereof, and an electronic apparatus, the semiconductor device comprising: at least one memory cell, the memory cell comprising a first transistor and a second transistor which are vertically stacked, the first transistor and the second transistor being vertical channel transistors; a second semiconductor layer of the second transistor is connected to a first gate electrode of the first transistor; the first semiconductor layer of the first transistor comprises a first vertical part which vertically extends; the second semiconductor layer of the second transistor comprises a second vertical part which vertically extends; the first gate electrode is distributed on the side wall of the first vertical part, the first electrode and the third electrode extend along a first direction parallel to the substrate, and the second gate electrode and the third gate electrode extend along a second direction parallel to the substrate; the first direction and the second direction intersect. According to the scheme provided by the embodiment of the invention, the storage unit comprises the two vertical channel transistors which are vertically stacked, so that the area of the storage unit can be reduced, and high-density integration can be realized.

A method of operating a non-volatile memory device, wherein the non-volatile memory device includes a cell string, wherein the cell string includes a plurality of cell transistors stacked in a direction perpendicular to a substrate in series between a bit line and a common source line, the method comprising: programming an erase control transistor in the plurality of cell transistors; and after the erase control transistor is programmed, applying an erase voltage to the common source line or the bit line and applying an erase control voltage to an erase control line connected to the erase control transistor, wherein the erase control voltage is less than the erase voltage and greater than a ground voltage, and wherein the erase control transistor is between a ground select transistor in the plurality of cell transistors and the common source line or between a string select transistor in the plurality of cell transistors and the bit line.

The present disclosure provides a semiconductor device, an electronic device, a transistor stack, and a manufacturing method therefor. The manufacturing method comprises: forming a stack structure by one etching on a semiconductor substrate; forming, on the semiconductor substrate, an oxide layer covering the stack structure; forming, within a gate region of the transistor stack, a dummy gate structure covering the oxide layer; forming a first transistor on the basis of a first active structure covered with the oxide layer; flipping the wafer and removing the semiconductor substrate; forming a second transistor on the basis of a second active structure covered with the oxide layer; and oxidizing a first portion of a first dummy gate structure to form a first gate isolation structure between a first gate structure and a second gate structure; and / or oxidizing a first portion of a second dummy gate structure to form a second gate isolation structure between the first gate structure and the second gate structure.

The invention discloses a stacked power amplifier based on transformer synthesis, and aims to solve the problem that the output power, synthesis efficiency and dynamic reliability of a power amplifier are difficult to synergistically improve under a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process. The amplifier adopts a symmetrical double-branch architecture and comprises a T-shaped power distribution network, two power amplification branches and a T-shaped power synthesis network. The power amplifier is characterized in that each power amplification branch comprises an amplifier adopting a multi-transistor stacking topology, and grids of stacked transistors are biased or coupled through a series capacitor so as to realize dynamic voltage distribution in a radio frequency period; the T-type transformer distribution / synthesis network and the stacked amplification branch adopting the capacitor dynamic voltage division work cooperatively, and unification of high output power, high synthesis efficiency and high working reliability is achieved jointly. Through the collaborative design of the architecture and the circuit level, the performance bottleneck in the traditional design is effectively broken through, and the method is suitable for high-frequency and high-power wireless communication systems such as 5G, Internet of Things and the like.

A semiconductor device including a second nanosheet transistor stacked over a first nanosheet transistor is provided which accommodates for having source / drain separating dielectric layers and / or stacked source / drain regions having a wide variety of vertical heights. The wide variety of heights can be along the same source / drain canyon or across different source / drain canyons.

A three-dimensional stacked field-effect transistor including a silicon substrate; a partial bottom dielectric isolation layer on the silicon substrate; a punch through stopper layer on the silicon substrate and on opposite sides of the partial bottom dielectric isolation layer; a first transistor on the partial bottom dielectric isolation layer and the punch through stopper layer; and a second transistor stacked on the first transistor. Each of the first transistor and the second transistor includes a channel, a source region on one side of the channel, and a drain region on another side of the channel. The partial bottom dielectric isolation layer is below the channel of the first transistor. The punch through stopper layer is below the source region and the drain region of the first transistor.

A semiconductor device includes a top transistor stacked over a bottom transistor. The top transistor comprises horizontally oriented nanosheet gates, and the bottom transistor comprises vertically oriented nanosheet gates. The top transistor and the bottom transistor are staggered.

A semiconductor device includes a substrate, a transistor stack on the substrate, a first source / drain structure on a first side of the transistor stack, and a second source / drain structure on a second side of the transistor stack, where the transistor stack includes a lower transistor on the substrate, the lower transistor including a lower channel layer and a lower gate structure surrounding the lower channel layer, an upper transistor on the lower transistor, the upper transistor including an upper channel layer and an upper gate structure surrounding the upper channel layer, and a first connecting layer between the lower gate structure and the upper gate structure, and the first source / drain structure and the second source / drain structure are connected via the first connecting layer.

Storage array device comprising: a stack of transistors (204) over a semiconductor substrate (50), wherein the stack of transistors (204) comprises a first thin-film transistor (204) over a second thin-film transistor (204), wherein the first thin-film transistor (204) comprises: a first storage film (90) along a first word line (54); and a first channel region (92), a first source line (108) and a first bit line (106), wherein the first storage film (90) is arranged between the first channel region (92) and the first word line (54); the second thin-film transistor (204) has: a second storage film (90) along a second word line (54); and a second channel region (92) along the first source line (108) and the first bit line (106), wherein the second storage film (90) is arranged between the second channel region (92) and the second word line (54); a first stairwell via (110) which is electrically connected to the first word line (54), wherein the first stairwell via (110) has a first width that is uniform from top to bottom; and a second stairwell via (110) which is electrically connected to the second word line (54), wherein the second stairwell via (110) has a second width that is uniform from top to bottom, the second width being greater than the first width.

Various implementations described herein are related to a device having a multi-transistor structure for use in circuit architecture. The multi-transistor structure may have a multi-transistor stack of at least one of N-type transistors or P-type transistors that are arranged in a multi-device stack configuration. Also, a physical layout of the multi-device stack configuration may provide a common-centroid configuration for process mismatch cancellation in at least one of the X-Y-Z axes.

Provided are a transistor, a 3D stacked semiconductor device, a manufacturing method thereof, and an electronic device. The transistor includes a first electrode and a second electrode arranged on a substrate, a semiconductor layer arranged between the first electrode and the second electrode, and a gate electrode insulated from the semiconductor layer; the first electrode and the second electrode are separated in a first direction parallel to the substrate; the gate electrode extends along a second direction parallel to the substrate, the gate electrode includes a sidewall extending along the second direction and two end surfaces, one end surface is configured to be connected with a word line; at least a portion of the sidewall of the gate electrode is surrounded by a semiconductor layer; the first direction intersects with the second direction.

An optoelectronic device including an optoelectronic circuit including light-emitting diodes, thin-film transistors, and a stack of electrically-insulating layers, said stack being located between the light-emitting diodes, and the transistors stack further including conductive elements, between and through the insulating layers, the conductive elements connecting at least some of the transistors to the light-emitting diodes The device further includes a support having a surface, the support being flexible and / or the surface being curved and non-planar, the optoelectronic circuit being connected to the surface on the side of the thin-film transistors.

An integrated circuit device includes a first transistor having a first-type channel and a second transistor having a second-type channel at a front side of a substrate. The first transistor is stacked over the second transistor. The integrated circuit device also includes a power line connected to a source terminal of the first transistor. The first transistor has a gate terminal configured to receive a control signal and has a drain terminal connected to both a gate terminal and a drain terminal of the second transistor. The integrated circuit device further includes a memory power line connected to a source terminal of the second transistor and a memory circuit configured to receive a supply voltage from the memory power line.

Memory cells, semiconductor devices, semiconductor stacked structures, and fabrication methods are provided. An example memory cell includes a capacitor and a transistor stacked over the capacitor in a compact configuration. The capacitor includes a floating gate, a high-k dielectric layer, and a metal gate. The metal gate extends horizontally from a first sidewall to a second sidewall and vertically from a bottom surface to a top surface. The transistor includes the metal gate and a gate dielectric layer disposed on the metal gate. The gate dielectric layer includes two side portions respectively disposed on the two sidewalls of the metal gate and, and a top portion disposed on the top surface of the metal gate. The transistor further includes two separate S / D regions respectively formed on the two side portions of the gate dielectric layer, and a channel region formed on the top portion of the gate dielectric layer.

A nonvolatile memory device is provided. The nonvolatile memory device includes a first memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate, the plurality of cell transistors being interconnected with a plurality of ground selection lines, a plurality of word lines, and a plurality of string selection lines; a block selection circuit connected with the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines, and providing respective driving voltages to the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines, respectively, in response to a block selection signal; and a block unselection circuit connected only with a specific string selection line among the plurality of string selection lines, and providing an off voltage to only the specific string selection line in response to a block unselection signal.

A memory structure includes a pull-down transistor and a pull-up transistor stacked vertically in a Z-direction, a pass-gate transistor and a dummy transistor stacked vertically in the Z-direction, a dielectric structure, a connection structure, and a butt contact. The pull-down transistor and the pull-up transistor share a first gate structure. The pass-gate transistor and the dummy transistor share a second gate structure. The dielectric structure is between the first gate structure and the second gate structure in a Y-direction. The connection structure is over and electrically connected to the first gate structure and is over and electrically isolated from the second gate structure. The connection structure is an L-shape in a Y-Z cross-sectional view. The butt contact is directly over the connection structure and the second gate structure. The butt contact is electrically connected to the connection structure and a source / drain feature of the pass-gate transistor.

This invention relates to a synaptic unit, its fabrication method, and a synaptic array. The synaptic unit comprises a first transistor, a vertical interconnect layer, and a second transistor stacked vertically from bottom to top. The first transistor includes a first source, a first drain, and a first gate. The second transistor includes a second source, a second drain, and a second gate. A channel layer is provided between the second source and the second drain, and a dielectric layer is adjacent to the channel layer. The vertical interconnect layer enables input signals to be input from the first source, pass through the first drain, and be transmitted to the second source. The second transistor is a photosensitive carbon nanotube transistor. A second control signal and a control light are generated at the control terminal. The second control signal and the control light jointly drive the second gate. When the second transistor is irradiated by the control light, photogenerated carriers are generated, which move between the channel layer and the dielectric layer. This invention features dual-mode optical and electrical low-power control, reducing control voltage, effectively reducing dynamic power consumption, and extending the battery life of edge devices.

Certain aspects of the present disclosure provide an inductively coupled multi-stack amplifier. An example amplifier includes a first transistor stack comprising a first input node, a first transistor, and a second transistor. The amplifier further includes a second transistor stack comprising a second input node, a third transistor, and a fourth transistor, wherein the first input node and the second input node form an input pair for a differential input signal. The amplifier further includes a first inductive element having a first terminal coupled between the first transistor and the second transistor. The amplifier further includes a second inductive element having a second terminal coupled to a drain of the second transistor, wherein the first inductive element is arranged to be inductively coupled to the second inductive element.

Embodiments of the present application relate to controlled regulation transitions. An apparatus (102) includes an amplifier (306) having non-inverting and inverting inputs and an output. The apparatus includes a capacitor (312) coupled to a first node (311) and ground (309), a resistor (310) coupled to the first node and the amplifier output, and a first switch (320) coupled to the first node and a current sink (322) coupled to ground. The apparatus includes an AND gate (318) having inputs and an output coupled to a control terminal of the first switch. The apparatus includes a first comparator (314) having non-inverting and inverting inputs and an output coupled to an input of the AND gate, a second comparator (324) having a non-inverting input coupled to the amplifier output, an inverting input coupled to a transistor stack (328), and an output coupled to an input of the AND gate, and a second switch (327) coupled to the transistor stack and a current source (326), the second switch having a control terminal coupled to the output of the first comparator.

A semiconductor device includes: transistors stacked in a vertical direction; a bit line electrically connected to a first end of each of the transistors; and a data storage structure electrically connected to a second end of each of the transistors. The data storage structure includes: conductive pillars extending in a first horizontal direction; an electrode pattern covering the conductive pillars; and a dielectric layer between each of the conductive pillars and the electrode pattern. The first horizontal direction is perpendicular to the vertical direction and is a direction oriented from the bit line to the data storage structure, each of the conductive pillars has a first side surface adjacent to a corresponding transistor among the transistors, and a second side surface opposite to the first side surface, and the second side surface of a first conductive pillar among the conductive pillars has a convex shape.

A level shifter may include a first transistor stack including at least four transistors arranged from a first voltage source to ground, including second and third transistors coupled with bias voltage source, and a fourth transistor coupled with an input to receive an input signal at a second voltage or ground. The level shifter may include a second transistor stack comprising at least four transistors arranged from the first voltage source to ground, including second and third transistors coupled with the bias voltage source, and a fourth transistor to receive an inverse of the input signal. A first transistor of the first transistor stack is cross-coupled with a first transistor of the second transistor stack. A level shifter may include a first output coupled with the second transistor stack between the second and third transistors to provide a first output signal at the first voltage or ground.