7results about How to "Improve RF performance" patented technology

The embodiment of the utility model provides an antenna assembly and a wearable device, the antenna assembly comprises an antenna main body, a printed circuit board and a metal bezel arranged on a shell of the wearable device, the metal bezel is coupled with the antenna main body to form a circular polarization radiation structure, the antenna main body is connected with a feeding point on the printed circuit board, and the printed circuit board is connected with the metal bezel. And the antenna main body is manufactured through a PDS printing process to form a three-dimensional structure. According to the antenna assembly provided by the utility model, through the coupling design of the metal bezel and the antenna and the PDS printing technology, the antenna performance bottleneck of a miniaturized terminal is broken through, and the radio frequency performance of the antenna is improved.

The invention discloses a millimeter wave radio frequency chip cavity QFN packaging structure optimization method and system, and the method comprises the following steps: 1, collecting the core electrical parameters and thermal power consumption parameters of a millimeter wave radio frequency chip and the performance requirements of a target application scene, and determining the basic structure parameters of cavity QFN packaging, the basic structure parameters comprise the size of a packaging body, the number and arrangement spacing of pins, and the size range of a cavity opening; step 2, suppressing requirements based on millimeter wave frequency band signal transmission characteristics and electromagnetic coupling; the millimeter wave radio frequency chip has the beneficial effects that optimization is performed from multiple dimensions of cavity structure, heat dissipation layout, pin and bonding design specially aiming at the high-frequency characteristic of the millimeter wave radio frequency chip, and the problem that millimeter wave frequency band signal transmission characteristics are not considered in the prior art is solved; through cavity electromagnetic shielding design, differential heat dissipation layout and impedance matching optimization, the radio frequency performance, the heat dissipation performance and the mechanical reliability of the packaging structure are remarkably improved, and the application requirements of chips with the frequency bands of 120 GHz and above are met.

The invention discloses a grounding stacking integrated radio frequency front-end chip stacking structure and a preparation method thereof, and belongs to the technical field of radio frequency microsystems. Based on silicon-based packaging, radio frequency front-end chips including a power divider, a low-noise amplifier and a multifunctional chip are subjected to function division, and four-channel radio frequency chips are respectively subjected to silicon-based embedded packaging and are led out through silicon through holes (TSV). An upper layer chip packaging module and a lower layer chip packaging module which are used for packaging two channel radio frequency chips respectively are bonded and integrated in a back-to-back mode, and the radio frequency chips which are packaged differently on the upper layer and the lower layer are connected through TSV via holes. Fanout lead-out is carried out in a bottom layer radio frequency chip, so that high-density integrated stacking is realized. By the adoption of the integrated stacking structure, the packaging size can be greatly reduced, and compared with a traditional silicon-based embedded fan-out structure, the size can be further reduced, and the packaging weight is reduced.

An RF transistor amplifier includes an RF transistor amplifier die having a semiconductor layer structure; an interconnect structure having opposite first and second sides, wherein the first side of the interconnect structure is adjacent to a surface of the RF transistor amplifier die such that the interconnect structure and the RF transistor amplifier die are in a stacked arrangement; and one or more circuit elements at the first side and / or the second side of the interconnect structure.

This application relates to a wireless signal optimization method for tire pressure information data transmission, comprising the following steps: a sensor node initiates a relay transmission mode based on link quality judgment, selects a relay node through a micro-routing protocol, and forwards data packets to a distributed slot antenna formed by coupling through vehicle body gaps via neighboring nodes; a central signal aggregator fuses the data received from multiple paths to reconstruct the complete tire pressure data stream. This application achieves reliable and continuous transmission of tire pressure signals under extreme obstruction environments, while also meeting the requirements of low power consumption and real-time performance.

The application relates to a coaxial connector dynamic assembly control method based on time domain reflection feedback. The method comprises the following steps: constructing a target impedance model; calibrating an assembly zero point; driving a shielding shell to quickly approach a preset safe depth; performing a fine regulation cycle of step-by-step pressing and impedance detection to obtain an instantaneous impedance characteristic value; and stopping pressing and fixing the position of the shielding shell when the instantaneous impedance characteristic value falls within the target impedance parameter range. The application controls the mechanical assembly depth through the electrical performance feedback closed loop, effectively eliminates the influence of the manufacturing tolerance on the characteristic impedance, solves the impedance dispersion problem in the assembly of special-shaped terminals, and significantly improves the high-frequency performance consistency and assembly yield of the connector.

The invention relates to the technical field of semiconductor devices, in particular to a preparation method of a GaN HEMT with an air dielectric layer and a composite passivation layer structure, and the method comprises the following steps: 1, cleaning an epitaxial wafer, and defining ohmic contact regions of a source electrode and a drain electrode; carrying out metal evaporation, metal lift-off and annealing treatment on the epitaxial wafer to prepare a source electrode and a drain electrode; 2, depositing a first passivation layer on the epitaxial wafer on which the source electrode and the drain electrode are prepared, and performing isolation; step 3, etching two lower layer cavities on the isolated first passivation layer; step 4, preparing two columnar light resistors on the two lower layer cavities; and step 5, depositing a second passivation layer on the first passivation layer of the two prepared columnar photoresistors. The air dielectric layer is introduced between the composite passivation layers on the two sides of the grid electrode. As the air medium has a very low dielectric constant, parasitic capacitance between the gate electrode and the source electrode and between the gate electrode and the drain electrode of the device can be effectively reduced.