Integrated circuit structure with complementary field effect transistor and buried metal interconnect and method

Abstract

Disclosed are structures with a complementary field effect transistor (CFET) and a buried metal interconnect that electrically connects a source / drain region of a lower-level transistor of the CFET with another device. The structure can include a memory cell with first and second CFETs, where each CFET includes a pull-up transistor stacked on and having a common gate with a pull-down transistor and each pull-down transistor has a common source / drain region with a pass-gate transistor. The metal interconnect connects a lower-level source / drain region of the first CFET (i.e., the common source / drain region of first pass-gate and pull-up transistors) to the common gate of the second CFET (i.e., to the common gate of second pull-down and pull-up transistors). Formation methods include forming an interconnect placeholder during lower-level source / drain region formation. After upper-level source / drain regions and replacement metal gates are formed, the interconnect placeholder is exposed, removed and replaced with a metal interconnect.

Description

BACKGROUNDField of the Invention[0001]The present invention relates to complementary field effect transistors (CFETs) and, more particularly, to an integrated circuit (IC) structure with a CFET and a buried metal interconnect that enables an electrical connection to a source / drain region of a lower-level transistor within the CFET and to a method of forming the IC structure.Description of Related Art[0002]Gate-all-around field effect transistors (GAAFETs) (e.g., nanowire-type GAAFETs or nanosheet-type GAAFETs) have been developed in order to improve drive current and electrostatics and to allow for device size scaling, increased device density and reduced area consumption. A GAAFET includes elongated nanoshape(s) (e.g., nanowire(s) or nanosheet(s)), which extend laterally between source / drain regions, and a wrap-around gate structure, which wraps around the nanoshape(s) such that the nanoshape(s) function as channel region(s).[0003]Recently, complementary field effect transistors (C...

AI Technical Summary

Benefits of technology

The patent text describes an integrated circuit (IC) structure that includes a complementary field effect transistor (CFET) with a common gate that is connected to another component through a buried metal interconnect. The IC structure can be used in a static random access memory (SRAM) cell, where the lower-level CFET has source / drain regions that are connected to the common gate of the upper-level CFET. The method for forming the IC structure includes forming interconnect placement during the formation of source / drain regions for the lower-level CFET, and replacing the interconnect placeholder with a buried metal interconnect to connect the common gate to the other component. The technical effect of this patent is to provide a more efficient and reliable method for forming an integrated circuit structure with a common gate that improves performance and reliability.

Problems solved by technology

While using CFETs can increase on-chip device density and reduce area consumption, providing signal connections to the source / drain regions of the lower-level GAAFETs (e.g., to achieve the cross-couple connection in an SRAM cell) can be quite complex.

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