22 results about "Macrocell" patented technology

The embodiment of the invention provides a direction sensing macro cell layout optimization method and device for chip design. The method comprises the steps that population initialization of an evolutionary algorithm is set; calculating fitness scores and candidate solution probabilities of candidate solutions of the population; calculating a quality score of each macro; visual features are extracted from the current layout state through a reinforcement learning agent, an encoder in the reinforcement learning agent extracts multi-scale spatial features of visual feature layout layer by layer, and the encoder and a decoder generate placement probability distribution in a direction position joint action space; outputting the orientation and placement coordinates of the macro-cells; multiple bottlenecks of an existing learning driving frame are broken through, in a layout frame of the reinforcement learning agent, the orientation (rotation and mirror image) and the position of a macro unit are jointly contained in the same action space for the first time, so that the agent can sample at a time and determine the position and direction of the macro unit, an explorable solution space is expanded, and the synergistic effect between the explorable solution space and the macro unit is captured.

One embodiment of the present invention provides an apparatus comprising a transceiving unit and a control unit, and a communication method using the same, wherein the transceiving unit is configured to perform communication with at least one network node in a macro cell, the macro cell comprising at least one small cell and communicating in an FDD mode, and wherein the control unit is configured to control the small cell to communicate in a TDD mode, generate control information for preventing the occurrence of handover when a terminal moves between the small cells within the macro cell, and perform control to transmit the control information to the terminal.

The invention belongs to the technical field of integrated circuit testing, and discloses an in-memory computing chip testing device and method based on a scan chain architecture, and the method comprises the steps: employing three groups of independent scan chains (input, weight and partial sum) to cooperate with an on-chip configurable controller (Config Regs + FSM), and achieving the automatic testing of a memory Mode and a computing Mode of an in-memory computing macro cell (CIM Macro). According to the technical scheme provided by the invention, the storage and calculation functions of the CIM chip can be comprehensively verified with lower hardware overhead and lower external IO rate.

Low-performing cells, serving a telecom deployment in a given geographical area, are commonly identified by the telecom operators based on one or more Network KPIs computed for each of the cells being part of the deployment. However, most of these KPIs describe the overall state of affairs of the cell without any insight into the user usage profile of the cell. The present disclosure proposes a novel method to adjust the network KPIs based on scores of the macro cell or the small cell (101) with the user usage profile of the cell to obtain the user correlated network scores of the cells and prioritize the low-performing cells in the network in order of degree of impact on users and their usage. Another aspect of this disclosure is that it shall predict and compute a realistic user score to get predictive insights into user profiles for solutions and preventive measures.

In traditional macrocell deployments, User Equipment (UE) communicates with a single Transmission Receiver Point (TRP) on the same cell for both downlink (DL) and uplink (UL) transmissions. However, to minimize both cost and interference (and improve UL transmission performance), dense deployment of UL Transmission Receiver Points (TRPs) is considered. Therefore, enhanced UL transmissions for multiple-input / multiple-output wireless communication are desired, especially in “asymmetric” scenarios, such as DL single-TRP (sTRP) / UL multiple-TRP (mTRP) wireless communication. To support UL-only TRPs, several issues need to be addressed, such as how the UE should perform UL power control for UL-only TRPs and how to account for scenarios where DL and UL transmissions from a given UE are associated with different TRPs. Solutions to these issues are disclosed, along with more efficient sounding reference signal (SRS) power control methods (especially when transmitting different sets of SRS resources to different TRPs).

At a high level, the technology disclosed herein relates to methods, systems, media, etc., for cell deployment optimization (e.g., via a cell deployment optimization engine). In embodiments, cell deployment optimization relates to particular technological approaches to deploying a cell (e.g., such as a macro cell or a small cell) based on user experiences (e.g., user device network coverage experiences), home locations for user devices, historical locations for user devices, churn rates, predicted cell deployment coverage data, etc. For example, in embodiments, a user experience for subscribers located within a threshold distance of a proposed cell deployment location may be determined. In addition, one or more user experience adjustments to the user experience for the subscribers may be determined based on deploying a cell at the proposed cell deployment location. A cell deployment prediction may be generated based on the user experience adjustments.

The invention discloses a macro cell legalization method, system and device for an FPGA chip and a medium, and the method comprises the steps: carrying out the global layout of an FPGA design netlist, and determining the initial positions of a macro cell and other design units in a global layout coordinate system; acquiring coordinate positions of other design units directly connected with each macro unit in the global layout coordinate system; respectively sequencing the coordinate positions of all other design units connected with each macro unit along the X-axis direction and the Y-axis direction to obtain an X coordinate sequence and a Y coordinate sequence; determining an anchor point corresponding to the macro cell based on the X coordinate sequence and the Y coordinate sequence; minimizing the distance between the candidate placement position of each macro cell and the corresponding anchor point to determine the legal placement position of each macro cell on the FPGA chip; according to the method and the device, the limitation of determining the anchor point of the macro cell in the global layout can be avoided, the deviation between the position of the macro cell and the anchor point after legalization is reduced, and the layout time sequence performance of the FPGA chip is optimized.

The invention discloses an AI-assisted macro cell layout multiplexing method and system, and relates to the technical field of integrated circuit design. The method comprises the following steps: acquiring first position information in a target design environment, wherein the first position information comprises a target placement position of a first macro cell; acquiring second position information in the source design environment, wherein the second position information comprises original coordinates of a plurality of circuit elements in a second macro cell; automatically generating new coordinates of the plurality of circuit elements in the target design environment by utilizing a trained AI model based on the target placement position and the original coordinates; and generating a target layout file of the second macro-cell in the target design environment based on the new coordinates. According to the method, the coordinates are automatically adjusted through the AI, efficient multiplexing of the small macro-cells in the large macro-cells is achieved, manual modification is not needed, errors are remarkably reduced, the iteration period is shortened, PPA income is improved, and design flexibility is enhanced.

This invention belongs to the field of AI algorithm optimization technology for chip back-end component placement. It discloses a chip thermal placement method based on reinforcement learning. The method includes: obtaining the chip's register transfer level description file and electronic design automation tool output file; mapping the chip's three-dimensional thermal field onto a two-dimensional plane, pre-setting the chip's boundary conditions, initially analyzing the chip's temperature distribution and determining the rectangular shape of each macrocell and the heat source intensity function, further determining the chip's thermal field distribution and performing key optimizations using finite element analysis; modeling the chip placement process, processing the mask based on a policy network, obtaining macrocell placement actions, and determining the optimal thermal placement of the chip. This invention effectively ensures chip performance by simultaneously optimizing heat dissipation and line length, and avoids the local optima and non-convergence problems of traditional algorithms through reinforcement learning algorithms.

A system (101) and a method (300) for generating a very large-scale integration layout plan (400). One method includes receiving (302) inputs (322, 324, 326) for automatically placing macrocells in the layout plan (400). The method includes performing (304) an automatic macrocell placement process based on the received inputs (322, 324, 326). The method includes generating (308) the layout plan (400) according to the automatic macrocell placement process. The layout plan (400) can then be used to generate a physical layout, and can subsequently be used to manufacture physical chips based on the generated physical layout.

This invention discloses a highly active exogenous cell care preparation derived from natural biological macrocells and its applications, belonging to the fields of biomedicine and cell care technology. This invention uses natural biological macrocells from algae, woody plants, herbaceous plants, fungi, and animals as raw materials, employing a low-temperature, mild purification process to retain the original active substances, and then compounding them with medical excipients to produce oral or sterile intravenous infusion preparations. The active ingredients of the preparation are natural, native components, mild and safe, with no obvious toxic side effects. At conventional doses, they are essentially metabolized within 24 hours, and at high doses, they are completely excreted within 1-2 days, without long-term accumulation in the body. This invention achieves cell activity repair, microenvironment regulation, and cell homeostasis maintenance through an exogenous, non-invasive method, without involving invasive cell modification. It has a wide range of applications, high safety, and a clearly defined scope of protection, possessing significant scientific research and industrial application value.

One embodiment of the present invention provides an apparatus comprising a transceiving unit and a control unit, and a communication method using the same, wherein the transceiving unit is configured to perform communication with at least one network node in a macro cell, the macro cell comprising at least one small cell and communicating in an FDD mode, and wherein the control unit is configured to control the small cell to communicate in a TDD mode, generate control information for preventing the occurrence of handover when a terminal moves between the small cells within the macro cell, and perform control to transmit the control information to the terminal.

This invention discloses an accelerator design method based on a dual 6T-SRAM memory cell with split word lines and a dual-bit local computation unit. Employing in-memory computing technology, it is used to accelerate artificial intelligence (AI) neural networks. Compared to traditional in-memory local computation units, this macrocell utilizes the characteristics of split-word-line 6T-SRAM. During operation, it simultaneously selects two word lines (WL) and read word lines (RWL) of a local cell, allowing data to be imported into the computation unit through the local bit lines and their inverse logic (LBL and LBLB) to complete the operation. This design can significantly improve the parallelism of operations while efficiently utilizing bit line pre-filling.

The macro-cell layout method comprises the following steps: acquiring connection relation information of t macro-cells and alternative layouts of the t macro-cells; inputting the connection relation information and the position information into an index prediction model to output a predicted value of the evaluation index; and obtaining a target layout of the t macro-cells according to the predicted value of the evaluation index and the alternative layout. According to the method, the evaluation indexes can be any indexes, such as the worst negative time sequence margin, the total negative time sequence margin, the semi-cycle length, the congestion degree and the like, so that the problem that an existing macro-cell layout method mainly focuses on optimizing an intermediate agent index which is easy to obtain in the current stage and ignores a cross-stage index which really reflects the final chip quality is solved; the time sequence performance of the circuit is optimized, and it is ensured that the circuit has higher design quality and manufacturability. In the application, the purpose of improving the evaluation index of the circuit in an end-to-end manner is realized, manual participation is not needed, the cost is lower, and the efficiency is higher.

This invention provides a low-power design method for inserting power gating units and creating a ground grid, comprising: inserting power gating units during the physical implementation layout planning stage to achieve power-off design of macrocell and standard cell regions; completing the cascading of the power scan chain to form a loop chain, facilitating the access of power gating signals from any position; creating the ground grid to enable access of normally-on power supplies and the supply of power to the design by power-off and ground; and inserting boundary cells and tap cells to avoid violations of physical design rules. This method solves problems such as the inability of electronic design automation tools to completely cover the macrocell channel area and adjacent areas above and below when inserting power gating units, the limitations of the power gating signal scan chain on the placement of power gating signal interfaces, and the area waste caused by automatically inserting physical cell tap cells; it can also be used in the physical design of integrated circuits without macrocells.

The invention relates to the field of integrated circuit chip rear-end design, in particular to an advanced process standard unit row lattice point layout planning method, which comprises the following steps: S1, module initialization and layout planning; s2, adjusting a macro cell; s3, checking and verifying; and S4, finally adjusting and optimizing. According to the design layout requirement rule of the standard unit, the script provided by the embodiment of the invention is used for quickly and accurately carrying out standard unit row lattice point layout planning on the module; a back-end design implementation engineer only needs to operate the script according to the embodiment of the invention in a module initialization stage and a floorplan design stage to quickly and accurately complete the layout planning of the row lattice points of the standard cell, so that the layout design of the chip standard cell can meet the requirement rule of a FinFET process on the row lattice points of the standard cell; and the back-end layout and wiring design of the chip is ensured to be smoothly advanced, so that the chip can be smoothly tapped out.

This invention discloses a low-power Bluetooth SoC adaptive clock gating structure and chip. The structure includes a clock source, a backbone clock network, a baseband logic state machine with an internal RF wake-up counter, and an adaptive integrated clock gating macrocell connected to an RF warning feedforward. The macrocell is divided into an environmental sensing region containing a ring oscillator network and a gating logic region containing asymmetric configuration logic gates. The first transistor in the inverter sub-unit and the pull-up transistors within the logic gates are located within a continuously shared N-type well surrounded by a grounded P-type substrate contact ring. The macrocell includes a dynamic compensation unit that dynamically determines the compensation window based on the delay count value and activates the parallel drive buffer. This application can achieve zero-delay, high-precision voltage drop feedback, eliminate glitches and metastability generated during RF wake-up, and reduce unnecessary switching power consumption.

The application discloses a macro cell layout method, equipment and computer readable storage medium, and relates to the technical field of integrated circuits. The macro cell layout method comprises the following steps: obtaining circuit netlist information to be laid out and a trained layout model; preprocessing the circuit netlist information to be laid out to obtain a current layout state; inputting the current layout state into the trained layout model to obtain a first to-be-placed position of a macro cell to be placed in the current layout state; updating the current layout state according to the first to-be-placed position to obtain a new current layout state, and inputting the new current layout state into the trained layout model again; after obtaining the first to-be-placed positions of all the macro cells to be placed in the circuit netlist information to be laid out, generating a corresponding macro cell layout result, and performing macro cell layout based on the macro cell layout result. The application solves the technical problem that the current macro cell layout method has poor layout effect.

The invention relates to the technical field of layout optimization in integrated circuit physical design, in particular to a staged preview collaborative optimization method for collaborative layout of macro cells and standard cells, and aims to solve the problems of poor collaboration, low overlap repair efficiency and high wiring congestion risk in mixed layout of the macro cells and the standard cells. According to the technical scheme, the method comprises the steps that firstly, a component neighborhood is constructed based on modularity and pairing weight, a neighborhood mode is dynamically switched through a differential evolution operator to generate a rehearsal population, and high-quality individuals are maintained through a double-end queue file; two-stage collaborative optimization is adopted, and adaptability optimization and typed overlap repair (only corresponding types of units are moved) are executed for macro units and standard units; the effect is evaluated through a combined cost function containing a line length and overlapping area weighted item, when any one condition of evaluation budget, overlapping standard reaching or too low improvement rate is met, termination is carried out, and local search optimization is disturbed through a tail end weight at the global optimal position. The layout quality and optimization efficiency can be improved, and the method is suitable for chip back-end layout design, power-assisted balance time sequence performance and wiring feasibility.

Apparatuses, systems, and methods for network interface management for Citizens Broadband Radio Service (CBRS) deployments, e.g., in LTE and / or 5G NR systems and beyond, including methods for coarse selection of CBRS networks and fine selection of CBRS networks as well as support for multiple CBRS networks. Coarse selection of CBRS networks may include various triggers for automatic CBRS profile enabling and / or disabling, user management and overriding of system selections, tiered hierarchy for CBRS network enabling and / or disabling, as well as mechanisms to avoid ping-ponging between network selection. Fine selection of CBRS networks may include data slot switching between mobile network operators (MNOs, e.g., LTE / NR macro cells) and CBRS eSIM as well as prioritization of CBRS networks over Wi-Fi networks. Multiple CBRS networks support may include CBRS network identifier (NID) matching for unique identification as well as user-ranked CBRS priority.

The present invention relates to a reading device for determining a signal propagation time of a light pulse between a lidar transmission unit and a lidar receiving unit of a lidar measuring device in a focal plane array arrangement, comprising: an input interface for receiving detections from multiple sensor elements of the lidar receiving unit, said sensor elements being arranged in a macrocell paired with a transmission element of the lidar transmission unit; a weighting unit for determining a respective individual weighting parameter for each of the plurality of sensor elements, said weighting parameter being based on a signal-to-noise ratio of the sensor element; a summation unit for generating a histogram with an allocation of the detections to the detection times of the detections, said summation unit being configured to weight the detections on the basis of the individual weighting parameters; a propagation time unit for determining the signal propagation time on the basis of the generated histogram; and an output unit for outputting the signal propagation time. The invention additionally relates to a method for determining a signal propagation time and to a lidar measuring device in a focal plane array arrangement for detecting objects in a surroundings of a vehicle.

This invention relates to the field of integrated circuit design technology and discloses an optimization method and system for series power gating units. The method includes: grouping multiple power switch units by columns; connecting the power switch units in each column using an odd-even interleaved series connection method; and for the relationships between multiple columns, based on pre-calculated inter-column distance information, using a greedy strategy to sequentially determine the connection relationship between each unconnected column and the set of connected columns, wherein each unconnected column can be connected to any column in the set of connected columns. This application can significantly shorten the overall trace length, avoid the insertion of additional relay buffer units, efficiently adapt to irregular layouts such as the periphery and edge regions of macrocells, and greatly improve the automation, connection efficiency, and physical implementation reliability of low-power chip design.