17 results about "Macro cell" patented technology

A receiver includes at least one detector macro-cell. Each of the at least one detector macro-cell includes a first detector, configured to capture first invisible radiation emitted from a first source and reflected by an object, a second detector, configured to capture first visible radiation reflected by or originating from the object, a third detector, configured to capture second visible radiation reflected by or originating from the object, and a fourth detector, configured to capture third visible radiation reflected by or originating from the object. The first visible radiation, the second visible radiation, and the third visible radiation may be red, green, and blue, respectively; alternatively red, green, and yellow, respectively; or alternatively cyan, magenta, and yellow, respectively. The first detector to the fourth detector are arranged in a first array to constitute one detector macro-cell.

This invention belongs to the field of AI algorithm optimization technology for chip back-end component placement. It discloses a chip thermal placement method based on reinforcement learning. The method includes: obtaining the chip's register transfer level description file and electronic design automation tool output file; mapping the chip's three-dimensional thermal field onto a two-dimensional plane, pre-setting the chip's boundary conditions, initially analyzing the chip's temperature distribution and determining the rectangular shape of each macrocell and the heat source intensity function, further determining the chip's thermal field distribution and performing key optimizations using finite element analysis; modeling the chip placement process, processing the mask based on a policy network, obtaining macrocell placement actions, and determining the optimal thermal placement of the chip. This invention effectively ensures chip performance by simultaneously optimizing heat dissipation and line length, and avoids the local optima and non-convergence problems of traditional algorithms through reinforcement learning algorithms.

The application discloses a method and device for determining the staying duration of a target object in a target area. The method comprises: obtaining record time sequence data of the target object within a first preset duration, the record time sequence data being used for indicating the staying time of the target object recorded by a base station, and the record time sequence data comprising staying data of the target object recorded by a base station of an edge macro cell in the target area and staying data of the target object recorded by a base station of a neighboring cell of the edge macro cell; dividing the record time sequence data into a plurality of time sequence data sets in a second preset duration; determining the staying duration of the target object recorded by the base station in the target area in each time sequence data set; and adding the durations of the target object recorded by the base station in the target area in all time sequence data sets to obtain the target staying duration of the target object in the target area. The application solves the technical problem of low accuracy of the obtained staying duration of the target object.

Various embodiments provide for adjusting routing capacity of a grid cell of one or more layers of a circuit design based on detected regions, such as notch regions (e.g., corners of macros, blockage corners) and input / output (IO) pin regions. More particularly, various embodiments detect one or more notch regions in a circuit design, detect one or more I / O pin regions in the circuit design, and adjust (e.g., reduce) routing capacity of one or more grid cells of one or more detected regions.

A system (101) and a method (300) for generating a very large-scale integration layout plan (400). One method includes receiving (302) inputs (322, 324, 326) for automatically placing macrocells in the layout plan (400). The method includes performing (304) an automatic macrocell placement process based on the received inputs (322, 324, 326). The method includes generating (308) the layout plan (400) according to the automatic macrocell placement process. The layout plan (400) can then be used to generate a physical layout, and can subsequently be used to manufacture physical chips based on the generated physical layout.

The application discloses a method for modular design of a logic control chip and the logic control chip. The logic control chip comprises at least two first-level submodules, each first-level submodule comprises at least one second-level submodule and at least one macro unit, the first-level submodule controls the macro unit through the second-level submodule to perform read and write operations on a storage chip, and the storage chip is connected with the logic control chip in three-dimensional heterogeneous integration. The processing capacity of the first-level submodule is determined based on the storage capacity of the storage chip, and the processing capacity of the second-level submodule is determined based on the processing capacity of the first-level submodule to which the second-level submodule belongs. The logic control chip is modularized, the second-level submodule realizes self timing and physical convergence, the first-level submodule calls and judges whether the second-level submodule converges in the first-level submodule, the first-level submodule realizes self timing and physical convergence, and the top layer calls and judges whether the first-level submodule converges in the top layer, thereby realizing parallel design, increasing design redundancy and solving problems such as a large number of timing violations and difficult physical convergence of a large-scale chip.

An automatic design and parameter optimization system of SRAM circuit in in-memory computing architecture, first data collection and input are carried out, then simulation and model training are carried out, the artificial neural network after training convergence is used as a proxy model, and is combined with a quantum genetic algorithm optimization engine to obtain a QGA-ANN joint optimization system, the optimal design parameters of the candidate are obtained through global extreme value optimization, and after verification and evaluation, the globally optimal design parameters are output. The application is based on the high stability in-memory computing SRAM circuit and optimization system of quantum genetic algorithm and neural network, the BP proxy model with extremely low time delay is used to perfectly replace the traditional SPICE physical simulation, and the quantum genetic algorithm with the elite reservation mechanism is used to completely solve the bottleneck of local extreme value and slow convergence. The time-consuming and long analog integrated circuit "trial and error" design is converted into efficient and accurate "one-key" automatic optimization design, and the efficiency and stability of the in-memory computing macro cell reliability design are effectively improved.

The application provides a chip layout optimization method and related device, the method comprises: obtaining a chip netlist and a library exchange format LEF file; the chip netlist comprises a connection relationship between a plurality of units to be laid out, the LEF file comprises geometric characteristics and electrical characteristic information of each unit to be laid out; the plurality of units to be laid out comprises one or more of a module, a division, a macro unit, a standard unit or an intellectual property core IP; a plurality of target units are determined from the plurality of units to be laid out; constraint solidification modeling is performed on the plurality of target units based on the chip netlist and the LEF file, and a modeling result is output; the modeling result comprises one or more first solidification constraint regions and an affinity relationship of the plurality of target units; wherein one of the first solidification constraint regions comprises at least one unit in the plurality of target units. The embodiments of the application can improve the layout quality of the chip layout.

One embodiment of the present invention provides an apparatus comprising a transceiving unit and a control unit, and a communication method using the same, wherein the transceiving unit is configured to perform communication with at least one network node in a macro cell, the macro cell comprising at least one small cell and communicating in an FDD mode, and wherein the control unit is configured to control the small cell to communicate in a TDD mode, generate control information for preventing the occurrence of handover when a terminal moves between the small cells within the macro cell, and perform control to transmit the control information to the terminal.

A method includes obtaining a plurality of macro cells, wherein each macro cell comprises a corresponding plurality of transistors and determining whether each of the plurality of macro cells is compliant with a set of one or more design rules associated with one or more backside wiring layers. The method includes providing, based on a result of the determining, one or more conductive shunt paths for at least one of the macro cells, where each transistor in each macro cell comprises a respective conductive shunt path between a gate structure and a source / drain region of the corresponding transistor.

The application discloses a macro unit automatic synthesis method based on splicable analog unit and belongs to the technical field of electronic design automation (EDA). The method aims to solve the problem that device matching constraint, layout area efficiency and design rule check cannot be considered in the existing analog layout automatic process. The method mainly comprises the following steps: receiving a circuit netlist with layout intention annotation, mapping devices into Acells; placing initial row bases according to a symmetric mode; executing a compression algorithm for keeping constraints, optimizing area by removing specific redundant polysilicon structures at the interfaces of adjacent Acells; performing legalization processing based on contact polysilicon spacing and power ground line spacing; finally, adopting a wiring method based on the satisfiability of module theory, automatically generating internal connections under the premise of ensuring geometric symmetry. The application can generate analog macro units meeting the requirements of DRC / LVS, compact in area and high in matching characteristics, and can be directly integrated into a digital layout and wiring process.

This invention discloses a low-power Bluetooth SoC adaptive clock gating structure and chip. The structure includes a clock source, a backbone clock network, a baseband logic state machine with an internal RF wake-up counter, and an adaptive integrated clock gating macrocell connected to an RF warning feedforward. The macrocell is divided into an environmental sensing region containing a ring oscillator network and a gating logic region containing asymmetric configuration logic gates. The first transistor in the inverter sub-unit and the pull-up transistors within the logic gates are located within a continuously shared N-type well surrounded by a grounded P-type substrate contact ring. The macrocell includes a dynamic compensation unit that dynamically determines the compensation window based on the delay count value and activates the parallel drive buffer. This application can achieve zero-delay, high-precision voltage drop feedback, eliminate glitches and metastability generated during RF wake-up, and reduce unnecessary switching power consumption.

Apparatuses, systems, and methods for network interface management for Citizens Broadband Radio Service (CBRS) deployments, e.g., in LTE and / or 5G NR systems and beyond, including methods for coarse selection of CBRS networks and fine selection of CBRS networks as well as support for multiple CBRS networks. Coarse selection of CBRS networks may include various triggers for automatic CBRS profile enabling and / or disabling, user management and overriding of system selections, tiered hierarchy for CBRS network enabling and / or disabling, as well as mechanisms to avoid ping-ponging between network selection. Fine selection of CBRS networks may include data slot switching between mobile network operators (MNOs, e.g., LTE / NR macro cells) and CBRS eSIM as well as prioritization of CBRS networks over Wi-Fi networks. Multiple CBRS networks support may include CBRS network identifier (NID) matching for unique identification as well as user-ranked CBRS priority.

The application discloses a macro layout optimization method and system based on reinforcement learning and a clustering algorithm. The method comprises the following steps: S10, circuit analysis and graph construction; S20, adaptive clustering of standard cells and generation of pseudo macros; S30, placement sequence optimization; S40, global layout based on reinforcement learning; and S50, detailed layout correction. The application analyzes the connection density and topological structure characteristics of standard cells in a chip circuit, generates pseudo macro cells by dynamically clustering the standard cells with fine granularity, and takes the pseudo macro cells as basic operation objects in the process of macro layout and reinforcement learning optimization, so that the reconstruction and optimization of the layout abstraction level are realized.

This invention relates to the field of integrated circuit design technology and discloses an optimization method and system for series power gating units. The method includes: grouping multiple power switch units by columns; connecting the power switch units in each column using an odd-even interleaved series connection method; and for the relationships between multiple columns, based on pre-calculated inter-column distance information, using a greedy strategy to sequentially determine the connection relationship between each unconnected column and the set of connected columns, wherein each unconnected column can be connected to any column in the set of connected columns. This application can significantly shorten the overall trace length, avoid the insertion of additional relay buffer units, efficiently adapt to irregular layouts such as the periphery and edge regions of macrocells, and greatly improve the automation, connection efficiency, and physical implementation reliability of low-power chip design.