131 results about "Macro cell" patented technology

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

The embodiment of the invention provides a processor architecture supporting in-memory matrix operation based on a static memory and a processor. Wherein the processor is provided with the provided processor architecture. A tensor core module in the processor architecture comprises a plurality of matrix operation units, a plurality of in-memory computing macro units are arranged in the matrix operation units, the plurality of in-memory computing macro units are connected by adopting a pulsation data path to form a two-dimensional pulsation array, and each in-memory computing macro unit comprises a plurality of parallel memory banks. And the memory bank comprises a static memory array supporting in-memory matrix operation. Therefore, according to the processor architecture provided by the scheme, the in-memory calculation macro unit based on the static memory is introduced to serve as the matrix operation unit to support in-memory matrix operation, and by adopting the matrix operation unit, the overall performance of the processor can be improved, and the high energy efficiency requirements of generative model reasoning and training can be better met.

A method, device and system for performing wireless communication in a wireless communication system that includes a low power node and a macro base station with common baseband and user equipment. The user equipment communicates with the low power node and the macro base station via a plurality of component carriers. The method includes: receiving, by the user equipment, a downlink signal transmitted by the low power node and the macro base station; and transmitting uplink signals to the low power node and the macro base station, wherein the method further includes: transmitting all first uplink signals of the uplink signals to the low power node as a receiving node. Accordingly, efficiency of uplink power control of a terminal may be increased and / or the burden for uplink control channel transmission of a macro cell may be reduced.

The invention provides a high-speed communication chip macro placement method based on reinforcement learning. The high-speed communication chip macro placement method comprises the following steps: extracting static features and dynamic features from a netlist; fusing the static features and the dynamic features, and inputting the fused static features and dynamic features into a shared graph neural network based on a reinforcement learning architecture; the strategy network outputs action probability distribution according to the current environment state, and the legal action with the maximum probability value is selected for execution; the value network outputs accumulated value estimation of the current environment state; after the action is executed, instant rewards and next state information are obtained, and the strategy network and the value network are updated according to the obtained information; and constructing a multi-objective optimization function based on macro placement constraint. According to the method, through deep fusion of reinforcement learning and constraint modeling, the automation level and design quality of macro cell placement are improved, and therefore the requirements of a high-speed communication chip for low power consumption, high performance and compact area are met.

The invention provides an integrated circuit collaborative layout method, device and equipment, which are applied to the technical field of integrated circuit design, and are characterized in that a proper net model is selected through a net relationship, and a matrix and a vector of quadratic programming layout are constructed according to the net model, so that an initial unit layout is efficiently solved; a batch processing strategy is adopted to carry out overlapping optimization on a standard cell and a macro cell to generate a legalized layout solution, an interaction force between anchor point simulation units is introduced, the layout is continuously iterated and refined until the line length converges, and a final high-quality layout solution is obtained, so that the overall performance of a chip is improved, the power consumption is reduced, and the overall performance of the chip is improved. And the macro cells and the standard cells are distributed to different chips in the three-dimensional stacked structure, so that the requirement that different chip layers adopt different design processes is met, and the production cost is effectively reduced.

The invention provides a method and device for optimizing the layout of a digital logic circuit and a storage medium, and the method comprises the steps: determining a first layout of the digital logic circuit, the first layout comprises a plurality of macro cells and a plurality of standard cells, determining channels formed between the adjacent macro cells, and optimizing the layout of the digital logic circuit based on an optimization target of the digital logic circuit, according to the positions of the standard unit and the channel, the target step length parameter of the standard unit is determined, the optimization target comprises at least one of a line length target, a density target and a time sequence target, and the standard unit is adjusted based on the target step length parameter so as to optimize the layout of the digital logic circuit. By means of the method, automatic layout optimization of the digital logic circuit can be achieved, the influence of a channel on layout optimization is reduced, and the performance of a chip is further improved.

The invention relates to the technical field of storage and calculation integration, in particular to a multi-core storage and calculation integration-oriented routing system and electronic equipment, the system comprises a plurality of storage and calculation integration cores, each storage and calculation integration core comprises a plurality of storage and calculation macro units, a plurality of direction output interfaces, an analysis network-on-chip and a router, and the storage and calculation macro units are bound with the direction output interfaces; the analysis network-on-chip analyzes the header information of the data packet to determine the target transmission direction of the data packet, and when the target transmission direction is the same as the position direction of the target core, the direction output interface outputs data to the target core; and the router is used for generating a target planning path according to the target transmission direction and the position direction of the target core when the target transmission direction is different from the position direction of the target core, and transmitting the data packet to the target core according to the target planning path. Therefore, the problems of congestion of high-parallel signal winding between the memory macro-cell and the route, blockage caused by improper matching of data transmission directions, low path planning efficiency and the like in the prior art are solved.

The invention discloses an in-memory encryption circuit, encryption method and system based on a resistive random access memory, and relates to the technical field of semiconductors and in-memory encryption, the in-memory encryption circuit comprises an in-memory calculation chip integrating a true random number generator, a physical unclonable function, a logic calculation function and a storage function, the computing macro unit is used for storing and processing bit data containing an encrypted plaintext and a key; the master control unit is used for uniformly managing control signals of the computing macro-units and ensuring cooperative work of the computing macro-units; the switch matrix is used for realizing external input and output of logic signals and data interaction among the computing macro units; and the input and output module is used for realizing external driving and internal driving of the in-memory computing chip and completing signal and data butt joint between the in-memory computing chip and external equipment. According to the method, deep integration of encryption algorithms can be realized, and the security of in-memory encryption is improved while the area overhead is reduced.

The invention provides a macro-cell layout evaluation optimization method based on a large language model, and belongs to the field of electronic design automation. According to the method, a large language model is introduced to assist layout generation, a current initial layout is improved in combination with connection weight analysis, on the other hand, an improved result is judged and continuously iterated according to natural language feedback of an experience manual or an expert, and closed-loop optimization is formed; carrying out weight quantization on direct and indirect signal paths among macro units, constructing a logic association strength matrix, and realizing accurate identification and priority ranking of key time sequence paths; the availability score of each candidate layout scheme is calculated through a layout availability scoring module, dynamic measurement is carried out on surrounding standard unit resources, the resource distribution state is evaluated in real time, the position of a macro unit is actively adjusted, and resource congestion or waste is avoided; the method is deeply integrated with an open source EDA tool, the dependence on a commercial tool is reduced, the tool chain deployment and iteration period is shortened, and the transportability and usability of the method are guaranteed.

The invention discloses an in-memory computing architecture compiling method and device, electronic equipment and a system on chip, and belongs to the technical field of in-memory computing. The method comprises the following steps: determining an initial iteration space of a polyhedral model according to a nested loop structure of a neural network operator in a compiling process; segmenting the initial iteration space into a plurality of sub-iteration spaces, and mapping iteration vectors in the plurality of sub-iteration spaces to a target base direction based on the target base transformation matrix to obtain an affine scheduling space; the method comprises the following steps: mapping an affine scheduling space to a plurality of macro units of an in-memory computing device to obtain a target mapping strategy, performing layout on memory access data corresponding to the affine scheduling space, and optimizing data handling operation of the memory access data according to a preset data handling cost function to obtain a target iteration space; and generating a compiled code according to the target iteration space. In this way, the data transmission overhead can be reduced, and the utilization rate of the macro-cell can be improved.

An artificial intelligence acceleration system based on an 8T-SRAM calculation and storage integrated macro cell is provided with a digital-analog hybrid calculation array, the digital-analog hybrid calculation array is provided with m * n 8T-SRAM storage and calculation integrated units, and each 8T-SRAM storage and calculation integrated unit is provided with a 6T-SRAM unit, a transistor T7 and a transistor T8; the 6T-SRAM unit is provided with a storage unit, a transistor T5 and a transistor T6; the grid electrode of the T7 is connected with the output end Qb of the storage unit, the source electrode of the T7 is grounded, and the drain electrode of the T7 is connected with the source electrode of the T8; the grid electrode end of the T8 is connected with a read word line RWL, and the drain electrode of the T8 is connected with a read bit line RBL; one ends of the column calculation line BL and the column calculation line BLb are connected with the column address decoder, and the other ends are connected with the read-write calculation control unit; the word line WL and the read word line RWL are connected with the row address decoder; one end of the read bit line RBL is connected with a power supply, and the other end is connected with the column simulation accumulation unit which outputs a calculation result through the analog-to-digital converter. The device has the advantages of being simple and clear in structure, capable of achieving efficient on-chip multiply-accumulate operation, easy to control, low in power consumption, high in precision and the like.

The invention relates to a wiring layout method based on reinforcement learning, which combines a macro-cell layout model and a congestion prediction model, and introduces a wiring evaluation mechanism in a layout stage, so as to improve the manufacturability and wiring success rate of chip design. The method specifically comprises the following steps: carrying out macro-cell layout by utilizing a layout model driven by reinforcement learning; performing congestion prediction on the layout result by using a congestion prediction model; extracting three types of features of a macro region, wiring density (RUDY) and pin density (Pin RUDY) after each layout iteration, normalizing the features, and combining the features into a three-channel feature map as the input of a congestion prediction model; and dynamically adjusting a reward function of reinforcement learning according to a prediction result, and guiding the layout model to avoid a high-congestion area. According to the method, the realizability of the layout scheme in the subsequent wiring stage can be remarkably improved, reworking is reduced, the design cost is reduced, and the method has high engineering practicability and expansibility.

The present application discloses a sense-in-memory macrocell circuit, system, and analog-to-digital conversion method, including the steps: a tag module reads an analog signal from the iSC bus; the tag module traverses and compares the read analog signal with a plurality of reference analog signals; according to the comparison result, a corresponding digital signal is obtained; the plurality of reference analog signals are data that gradually increase or decrease according to a functional relationship. This method does not require a dedicated ADC circuit and utilizes the existing circuits of the PE to implement the conversion function.

Methods, systems, and devices for wireless communication are described. A user equipment (UE) may avoid frequent handovers in a small cell by triggering a handover to a macro cell. The UE may determine that the UE has performed multiple handovers within a time period. The UE may determine to trigger a handover to the macro cell. The UE may identify the macro cell based on measuring the macro cell during the multiple handovers. The UE may determine to avoid indicating signal measurements of the small cell in a measurement report. Accordingly, the measurement report may include signal measurements of the macro cell and omit signal measurements of the small cell. The UE may send the measurement report to the small cell serving as the serving cell of the UE. Based on the measurement report, the UE may receive a message initiating a handover procedure to the macro cell.

Methods, media, and systems are provided for controlling cell site selection by a user device in a telecommunications network. A System Information Block (SIB) message (e.g., an SIB Type 1 message) is transmitted (e.g., by a cell site) for receipt by the user device for cell site selection. In some aspects, the SIB message is transmitted while the user device is camping on a serving cell of a base station other than the cell site. The SIB message comprises information that identifies a type of the cell site. The type of the cell site is a cell site other than a macro cell, such as a small cell for example. Upon selection of the cell site by the user device based on the SIB message and the type of the cell site, the user device is provided access to a telecommunications service.

The embodiment of the invention provides a direction sensing macro cell layout optimization method and device for chip design. The method comprises the steps that population initialization of an evolutionary algorithm is set; calculating fitness scores and candidate solution probabilities of candidate solutions of the population; calculating a quality score of each macro; visual features are extracted from the current layout state through a reinforcement learning agent, an encoder in the reinforcement learning agent extracts multi-scale spatial features of visual feature layout layer by layer, and the encoder and a decoder generate placement probability distribution in a direction position joint action space; outputting the orientation and placement coordinates of the macro-cells; multiple bottlenecks of an existing learning driving frame are broken through, in a layout frame of the reinforcement learning agent, the orientation (rotation and mirror image) and the position of a macro unit are jointly contained in the same action space for the first time, so that the agent can sample at a time and determine the position and direction of the macro unit, an explorable solution space is expanded, and the synergistic effect between the explorable solution space and the macro unit is captured.

The present application discloses a method for placing a design unit and related equipment, comprising: generating a placement area according to design input parameters of a target integrated circuit; placing the boundary unit at the boundary of the placement area according to the definition of the boundary unit in a library exchange format file, and dividing the placement area into a plurality of placement grids; placing all standard units and all macro units in each placement grid according to a target optimization function, and inserting units for power consumption optimization and units for timing optimization into corresponding positions in the placement grid; evaluating each placement grid according to a wiring pre-evaluation function to obtain an evaluation result corresponding to each placement grid, and if the evaluation result does not meet a preset requirement, optimizing the evaluation result until the evaluation result meets the preset requirement; after the optimization is completed, if there is a blank area in the placement area, inserting a filler unit in the blank area.

One embodiment of the present invention provides an apparatus comprising a transceiving unit and a control unit, and a communication method using the same, wherein the transceiving unit is configured to perform communication with at least one network node in a macro cell, the macro cell comprising at least one small cell and communicating in an FDD mode, and wherein the control unit is configured to control the small cell to communicate in a TDD mode, generate control information for preventing the occurrence of handover when a terminal moves between the small cells within the macro cell, and perform control to transmit the control information to the terminal.

Apparatuses, systems, and methods for network interface management for Citizens Broadband Radio Service (CBRS) deployments, e.g., in LTE and / or 5G NR systems and beyond, including methods for coarse selection of CBRS networks and fine selection of CBRS networks as well as support for multiple CBRS networks. Coarse selection of CBRS networks may include various triggers for automatic CBRS profile enabling and / or disabling, user management and overriding of system selections, tiered hierarchy for CBRS network enabling and / or disabling, as well as mechanisms to avoid ping-ponging between network selection. Fine selection of CBRS networks may include data slot switching between mobile network operators (MNOs, e.g., LTE / NR macro cells) and CBRS eSIM as well as prioritization of CBRS networks over Wi-Fi networks. Multiple CBRS networks support may include CBRS network identifier (NID) matching for unique identification as well as user-ranked CBRS priority.

A macro cell layout method and a related apparatus, relating to the technical field of electronic design automation. The method comprises: acquiring connection relationship information and alternative layouts of t macro cells; inputting the connection relationship information and position information into an indicator prediction model so as to output predicted values of evaluation indicators; and obtaining a target layout of the t macro cells on the basis of the predicted values of the evaluation indicators and the alternative layouts. In the present application, the evaluation indicators may be any indicators, such as worst negative slack, total negative slack, half-perimeter wirelength, and degree of congestion. The problem that existing macro cell layout methods mainly focus on optimizing intermediate proxy indicators which are easy to acquire at a current stage and ignore cross-stage indicators which truly reflect final chip quality is solved and the timing performance of a circuit is optimized, ensuring that the circuit has a higher design quality and higher manufacturability. In the present application, the objective of improving evaluation indicators of a circuit in an "end-to-end" manner is achieved, manual intervention is not needed, costs are lower, and efficiency is higher.

Described herein is a system with a first network element and a second network element. The first network element contains a processor configured to synchronize with the second network element; and maintain synchronization with the second network element. The first network element is a small cell eNB and the second network element is one of the following: a macro cell enhanced node-B (eNB); or a small cell eNB.

A method, device and system for performing wireless communication in a wireless communication system that includes a low power node and a macro base station with common baseband and user equipment. The user equipment communicates with the low power node and the macro base station via a plurality of component carriers. The method includes: receiving, by the user equipment, a downlink signal transmitted by the low power node and the macro base station; and transmitting uplink signals to the low power node and the macro base station, wherein the method further includes: transmitting all first uplink signals of the uplink signals to the low power node as a receiving node. Accordingly, efficiency of uplink power control of a terminal may be increased and / or the burden for uplink control channel transmission of a macro cell may be reduced.

The invention discloses an automatic generation method of a macro cell layout with a standard cell structure, belongs to the technical field of automatic generation methods of macro cell layouts, solves the problem that the prior art cannot adapt to automatic generation of layouts, avoids mismatch of symmetrical structures, and optimizes the area of the layouts. The method comprises the following steps of: generating an MOS (Metal Oxide Semiconductor) single-finger Pcell with the same channel size as a target macro cell layout, embedding a power track and a grounding track, reserving a metal shape for a grid electrode pin, a source electrode pin and a drain electrode pin which are arranged on a second metal layer to form an independent unit structure, and performing horizontal mirror image copying to form an independent unit structure; and reconstructing a second metal layer according to the macro-cell schematic diagram to connect the pins to obtain an overall unit structure, then arranging through holes at the pins to connect the different metal layers, arranging buffer structures at the two sides to form a final overall unit structure, and finally exporting a GDS file. The method is used for automatically generating the macro cell layout with the standard cell structure.

A receiver includes at least one detector macro-cell. Each of the at least one detector macro-cell includes a first detector, configured to capture first invisible radiation emitted from a first source and reflected by an object, a second detector, configured to capture first visible radiation reflected by or originating from the object, a third detector, configured to capture second visible radiation reflected by or originating from the object, and a fourth detector, configured to capture third visible radiation reflected by or originating from the object. The first visible radiation, the second visible radiation, and the third visible radiation may be red, green, and blue, respectively; alternatively red, green, and yellow, respectively; or alternatively cyan, magenta, and yellow, respectively. The first detector to the fourth detector are arranged in a first array to constitute one detector macro-cell.

The invention discloses a millimeter wave heterogeneous network hybrid beam forming system and method oriented to cell cooperation, and relates to the technical field of wireless communication, and the system comprises a macro cell oriented to cell cooperation, a plurality of micro cells and a plurality of terminal user equipment which all work on a millimeter wave frequency band; a macro cellular base station MBS is established in the coverage area of the macro cellular cell, a micro cellular base station PBS is established in the coverage area of the micro cellular cell, and the plurality of micro cells are all deployed in the coverage area of the macro cellular cell; cooperative micro-cells are deployed in a macro-cell coverage area, an intelligent relay mechanism is introduced, cross-cell joint transmission and intelligent beam collaboration are realized, the effective coverage range of millimeter wave signals and the link reliability are improved, large-scale MIMO and hybrid beam forming technologies are combined, the sparse characteristic of millimeter wave channels is fully utilized, and the system performance is improved. And multi-user parallel transmission and interference-controllable beam resource allocation are realized.

An epitaxial growth process chamber is described having a component with a macro cell support structure configured with an interconnected solid support defining a fluid communication aperture. A component configured for use in an epitaxial growth processing chamber is also described, the component having a macro cell support structure configured with an interconnected solid support defining a fluid communication aperture. The component is a bottom plate, an exhaust cover, an injection ring, an injection cover, a lower reflector, an upper reflector, a lower heat shield, an upper heat shield, a conical reflector or a combination thereof. In some cases, the component may further include an inlet flow port. In some other cases, the component may further include an inlet flow port, an outlet flow port, and a fluid flow wall, and optionally a fluid flow baffle, and optionally a reflective surface.

Dynamically configuring wireless access points (APs) in wireless local area networks (WLANs). Dynamically determines an AP configuration of cell size and frequency sub-bands of deployed dual-radio WLAN APs for improved network performance. In a first AP configuration, a first AP radio increases the power level of a micro cell while a second AP radio decreases the power level of a macro cell to provide a higher quality of service for the clients connected to the first and second co-located, same-band AP radios. If the increased power of the micro cell causes too much interference between the co-located, same-band AP radios, then a second AP configuration is dynamically applied to lock each AP radio on a different, non-overlapping frequency band, thus minimizing interference between the AP radios and improving network performance.

The invention belongs to the technical field of integrated circuit testing, and discloses an in-memory computing chip testing device and method based on a scan chain architecture, and the method comprises the steps: employing three groups of independent scan chains (input, weight and partial sum) to cooperate with an on-chip configurable controller (Config Regs + FSM), and achieving the automatic testing of a memory Mode and a computing Mode of an in-memory computing macro cell (CIM Macro). According to the technical scheme provided by the invention, the storage and calculation functions of the CIM chip can be comprehensively verified with lower hardware overhead and lower external IO rate.

The application discloses a 3D perception circuit, a sensing and storage integrated macro unit circuit, a system and a data processing method. The 3D perception circuit comprises a 3D light signal perception unit, which is used for converting a light flight time into a time pulse signal; a time conversion analog circuit, which is used for converting the flight time of a photon into an analog current signal or an analog voltage signal according to the time pulse signal; the time conversion analog circuit comprises a control module, an integration module and a readout module, wherein the control module is used for controlling the start integration and the end integration of the integration module, and is used for outputting a start signal when a photon is emitted and outputting a stop signal when the time pulse signal is received; the integration module is used for starting to integrate the current after receiving the start signal, and the integration is ended after receiving the stop signal; and the readout module is used for converting the integrated signal into a voltage signal and a current signal required by a later stage of the system.