75 results about "Macro cell" patented technology

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

The invention provides a high-speed communication chip macro placement method based on reinforcement learning. The high-speed communication chip macro placement method comprises the following steps: extracting static features and dynamic features from a netlist; fusing the static features and the dynamic features, and inputting the fused static features and dynamic features into a shared graph neural network based on a reinforcement learning architecture; the strategy network outputs action probability distribution according to the current environment state, and the legal action with the maximum probability value is selected for execution; the value network outputs accumulated value estimation of the current environment state; after the action is executed, instant rewards and next state information are obtained, and the strategy network and the value network are updated according to the obtained information; and constructing a multi-objective optimization function based on macro placement constraint. According to the method, through deep fusion of reinforcement learning and constraint modeling, the automation level and design quality of macro cell placement are improved, and therefore the requirements of a high-speed communication chip for low power consumption, high performance and compact area are met.

The invention relates to the technical field of storage and calculation integration, in particular to a multi-core storage and calculation integration-oriented routing system and electronic equipment, the system comprises a plurality of storage and calculation integration cores, each storage and calculation integration core comprises a plurality of storage and calculation macro units, a plurality of direction output interfaces, an analysis network-on-chip and a router, and the storage and calculation macro units are bound with the direction output interfaces; the analysis network-on-chip analyzes the header information of the data packet to determine the target transmission direction of the data packet, and when the target transmission direction is the same as the position direction of the target core, the direction output interface outputs data to the target core; and the router is used for generating a target planning path according to the target transmission direction and the position direction of the target core when the target transmission direction is different from the position direction of the target core, and transmitting the data packet to the target core according to the target planning path. Therefore, the problems of congestion of high-parallel signal winding between the memory macro-cell and the route, blockage caused by improper matching of data transmission directions, low path planning efficiency and the like in the prior art are solved.

The invention discloses an in-memory encryption circuit, encryption method and system based on a resistive random access memory, and relates to the technical field of semiconductors and in-memory encryption, the in-memory encryption circuit comprises an in-memory calculation chip integrating a true random number generator, a physical unclonable function, a logic calculation function and a storage function, the computing macro unit is used for storing and processing bit data containing an encrypted plaintext and a key; the master control unit is used for uniformly managing control signals of the computing macro-units and ensuring cooperative work of the computing macro-units; the switch matrix is used for realizing external input and output of logic signals and data interaction among the computing macro units; and the input and output module is used for realizing external driving and internal driving of the in-memory computing chip and completing signal and data butt joint between the in-memory computing chip and external equipment. According to the method, deep integration of encryption algorithms can be realized, and the security of in-memory encryption is improved while the area overhead is reduced.

The embodiment of the invention provides a direction sensing macro cell layout optimization method and device for chip design. The method comprises the steps that population initialization of an evolutionary algorithm is set; calculating fitness scores and candidate solution probabilities of candidate solutions of the population; calculating a quality score of each macro; visual features are extracted from the current layout state through a reinforcement learning agent, an encoder in the reinforcement learning agent extracts multi-scale spatial features of visual feature layout layer by layer, and the encoder and a decoder generate placement probability distribution in a direction position joint action space; outputting the orientation and placement coordinates of the macro-cells; multiple bottlenecks of an existing learning driving frame are broken through, in a layout frame of the reinforcement learning agent, the orientation (rotation and mirror image) and the position of a macro unit are jointly contained in the same action space for the first time, so that the agent can sample at a time and determine the position and direction of the macro unit, an explorable solution space is expanded, and the synergistic effect between the explorable solution space and the macro unit is captured.

One embodiment of the present invention provides an apparatus comprising a transceiving unit and a control unit, and a communication method using the same, wherein the transceiving unit is configured to perform communication with at least one network node in a macro cell, the macro cell comprising at least one small cell and communicating in an FDD mode, and wherein the control unit is configured to control the small cell to communicate in a TDD mode, generate control information for preventing the occurrence of handover when a terminal moves between the small cells within the macro cell, and perform control to transmit the control information to the terminal.

Apparatuses, systems, and methods for network interface management for Citizens Broadband Radio Service (CBRS) deployments, e.g., in LTE and / or 5G NR systems and beyond, including methods for coarse selection of CBRS networks and fine selection of CBRS networks as well as support for multiple CBRS networks. Coarse selection of CBRS networks may include various triggers for automatic CBRS profile enabling and / or disabling, user management and overriding of system selections, tiered hierarchy for CBRS network enabling and / or disabling, as well as mechanisms to avoid ping-ponging between network selection. Fine selection of CBRS networks may include data slot switching between mobile network operators (MNOs, e.g., LTE / NR macro cells) and CBRS eSIM as well as prioritization of CBRS networks over Wi-Fi networks. Multiple CBRS networks support may include CBRS network identifier (NID) matching for unique identification as well as user-ranked CBRS priority.

A macro cell layout method and a related apparatus, relating to the technical field of electronic design automation. The method comprises: acquiring connection relationship information and alternative layouts of t macro cells; inputting the connection relationship information and position information into an indicator prediction model so as to output predicted values of evaluation indicators; and obtaining a target layout of the t macro cells on the basis of the predicted values of the evaluation indicators and the alternative layouts. In the present application, the evaluation indicators may be any indicators, such as worst negative slack, total negative slack, half-perimeter wirelength, and degree of congestion. The problem that existing macro cell layout methods mainly focus on optimizing intermediate proxy indicators which are easy to acquire at a current stage and ignore cross-stage indicators which truly reflect final chip quality is solved and the timing performance of a circuit is optimized, ensuring that the circuit has a higher design quality and higher manufacturability. In the present application, the objective of improving evaluation indicators of a circuit in an "end-to-end" manner is achieved, manual intervention is not needed, costs are lower, and efficiency is higher.

A receiver includes at least one detector macro-cell. Each of the at least one detector macro-cell includes a first detector, configured to capture first invisible radiation emitted from a first source and reflected by an object, a second detector, configured to capture first visible radiation reflected by or originating from the object, a third detector, configured to capture second visible radiation reflected by or originating from the object, and a fourth detector, configured to capture third visible radiation reflected by or originating from the object. The first visible radiation, the second visible radiation, and the third visible radiation may be red, green, and blue, respectively; alternatively red, green, and yellow, respectively; or alternatively cyan, magenta, and yellow, respectively. The first detector to the fourth detector are arranged in a first array to constitute one detector macro-cell.

The invention discloses a millimeter wave heterogeneous network hybrid beam forming system and method oriented to cell cooperation, and relates to the technical field of wireless communication, and the system comprises a macro cell oriented to cell cooperation, a plurality of micro cells and a plurality of terminal user equipment which all work on a millimeter wave frequency band; a macro cellular base station MBS is established in the coverage area of the macro cellular cell, a micro cellular base station PBS is established in the coverage area of the micro cellular cell, and the plurality of micro cells are all deployed in the coverage area of the macro cellular cell; cooperative micro-cells are deployed in a macro-cell coverage area, an intelligent relay mechanism is introduced, cross-cell joint transmission and intelligent beam collaboration are realized, the effective coverage range of millimeter wave signals and the link reliability are improved, large-scale MIMO and hybrid beam forming technologies are combined, the sparse characteristic of millimeter wave channels is fully utilized, and the system performance is improved. And multi-user parallel transmission and interference-controllable beam resource allocation are realized.

An epitaxial growth process chamber is described having a component with a macro cell support structure configured with an interconnected solid support defining a fluid communication aperture. A component configured for use in an epitaxial growth processing chamber is also described, the component having a macro cell support structure configured with an interconnected solid support defining a fluid communication aperture. The component is a bottom plate, an exhaust cover, an injection ring, an injection cover, a lower reflector, an upper reflector, a lower heat shield, an upper heat shield, a conical reflector or a combination thereof. In some cases, the component may further include an inlet flow port. In some other cases, the component may further include an inlet flow port, an outlet flow port, and a fluid flow wall, and optionally a fluid flow baffle, and optionally a reflective surface.

The invention belongs to the technical field of integrated circuit testing, and discloses an in-memory computing chip testing device and method based on a scan chain architecture, and the method comprises the steps: employing three groups of independent scan chains (input, weight and partial sum) to cooperate with an on-chip configurable controller (Config Regs + FSM), and achieving the automatic testing of a memory Mode and a computing Mode of an in-memory computing macro cell (CIM Macro). According to the technical scheme provided by the invention, the storage and calculation functions of the CIM chip can be comprehensively verified with lower hardware overhead and lower external IO rate.

The application discloses a 3D perception circuit, a sensing and storage integrated macro unit circuit, a system and a data processing method. The 3D perception circuit comprises a 3D light signal perception unit, which is used for converting a light flight time into a time pulse signal; a time conversion analog circuit, which is used for converting the flight time of a photon into an analog current signal or an analog voltage signal according to the time pulse signal; the time conversion analog circuit comprises a control module, an integration module and a readout module, wherein the control module is used for controlling the start integration and the end integration of the integration module, and is used for outputting a start signal when a photon is emitted and outputting a stop signal when the time pulse signal is received; the integration module is used for starting to integrate the current after receiving the start signal, and the integration is ended after receiving the stop signal; and the readout module is used for converting the integrated signal into a voltage signal and a current signal required by a later stage of the system.

The invention provides a multi-model fusion memory macro-cell design quality prediction system and method. The system comprises a feature extraction and coding module, a multi-model fusion prediction module and a continuous learning module. By integrating a plurality of AI sub-models and adopting a stacking method or a voting method for result fusion, high-precision prediction of the power consumption, the performance and the area of the memory macro-cell is realized. The system has a closed-loop learning capability, can be adaptively updated along with feedback data, can be integrated into a memory compiler or an EDA process, and provides rapid and accurate PPA prediction and optimization support for the initial stage of chip design.

The invention discloses a method for constructing a rear-end layout data set of a digital integrated circuit based on parameter regulation and control. The method comprises the following steps: acquiring an RTL code of the digital integrated circuit, identifying a physical unit represented by the RTL code, and acquiring a physical layout effect related parameter corresponding to each physical unit; based on a plurality of regulation targets, a plurality of parameters are selected from the physical layout effect related parameters for regulation, and a netlist is formed; adjusting a macro cell, and determining a layout plan; based on the determined layout plan, all physical units in the netlist are placed in corresponding chip areas, clock distribution construction is carried out, wiring is carried out according to the netlist, and a layout file is obtained; and performing feature extraction on the layout file to obtain a layout and layout features, and generating a layout data set based on the layout and the layout features. According to the method, the problems of data scarcity, high generation cost and diversified requirements in the prior art can be solved, and the digital back-end layout data set of the integrated circuit can be efficiently constructed in a diversified manner.

Low-performing cells, serving a telecom deployment in a given geographical area, are commonly identified by the telecom operators based on one or more Network KPIs computed for each of the cells being part of the deployment. However, most of these KPIs describe the overall state of affairs of the cell without any insight into the user usage profile of the cell. The present disclosure proposes a novel method to adjust the network KPIs based on scores of the macro cell or the small cell (101) with the user usage profile of the cell to obtain the user correlated network scores of the cells and prioritize the low-performing cells in the network in order of degree of impact on users and their usage. Another aspect of this disclosure is that it shall predict and compute a realistic user score to get predictive insights into user profiles for solutions and preventive measures.

The application relates to a macro cell layout method, device, medium and product of integrated circuit design. The macro cell layout method is applied to a legalization stage of macro cell layout, and comprises the following steps: obtaining an initialization layout, performing global layout on the initialization layout to obtain an initial layout with a boundary and comprising a plurality of macro cells; providing preset constraint conditions corresponding to the initial layout, wherein the preset constraint conditions comprise minimum spacing constraints and prohibited spacing constraints, whether there is a violation between adjacent macro cells and between the macro cells and the boundary is determined according to the preset constraint conditions, and the types of the violation include repulsion violation and attraction violation; according to the initial layout, idle layout space distribution available for macro cell movement is generated, and the idle layout space of the macro cell in the moving direction is calculated; based on the idle layout space, the violation and the type of the violation, the displacement of the macro cell is calculated, and the initial layout is optimized.

The invention discloses an in-memory multiply-accumulate and similarity calculation circuit based on dynamic logic, which is used for supporting the design of an in-memory calculation macro cell and an accelerator in a digital domain, and provides an in-memory calculation circuit architecture which supports a Booth coding rule for inputting similarity calculation. On the basis, a local input sharing calculation unit and a decoding and addition tree unit are designed, and element-by-element multiply-accumulate calculation and similarity calculation of fixed data are supported. Compared with a traditional multiply-accumulate circuit, the multiply-accumulate circuit disclosed by the invention adopts a calculation mode of firstly carrying out Booth coding on input data, then generating a multiply-accumulate partial product and finally carrying out decoding accumulation, and meanwhile, a partial product generation and similarity calculation circuit is designed based on dynamic logic, so that the partial product is multiplexed, and multiply-accumulate calculation is realized element by element with smaller calculation overhead; the face effect and the energy efficiency are both considered, and the comprehensive performance of the computing architecture and the circuit is improved.

At a high level, the technology disclosed herein relates to methods, systems, media, etc., for cell deployment optimization (e.g., via a cell deployment optimization engine). In embodiments, cell deployment optimization relates to particular technological approaches to deploying a cell (e.g., such as a macro cell or a small cell) based on user experiences (e.g., user device network coverage experiences), home locations for user devices, historical locations for user devices, churn rates, predicted cell deployment coverage data, etc. For example, in embodiments, a user experience for subscribers located within a threshold distance of a proposed cell deployment location may be determined. In addition, one or more user experience adjustments to the user experience for the subscribers may be determined based on deploying a cell at the proposed cell deployment location. A cell deployment prediction may be generated based on the user experience adjustments.

The invention discloses a macro cell legalization method, system and device for an FPGA chip and a medium, and the method comprises the steps: carrying out the global layout of an FPGA design netlist, and determining the initial positions of a macro cell and other design units in a global layout coordinate system; acquiring coordinate positions of other design units directly connected with each macro unit in the global layout coordinate system; respectively sequencing the coordinate positions of all other design units connected with each macro unit along the X-axis direction and the Y-axis direction to obtain an X coordinate sequence and a Y coordinate sequence; determining an anchor point corresponding to the macro cell based on the X coordinate sequence and the Y coordinate sequence; minimizing the distance between the candidate placement position of each macro cell and the corresponding anchor point to determine the legal placement position of each macro cell on the FPGA chip; according to the method and the device, the limitation of determining the anchor point of the macro cell in the global layout can be avoided, the deviation between the position of the macro cell and the anchor point after legalization is reduced, and the layout time sequence performance of the FPGA chip is optimized.

The application provides a high-speed communication chip macro placement method based on reinforcement learning, comprising extracting static features and dynamic features from a netlist; after the static features and the dynamic features are fused, inputting into a shared graph neural network based on a reinforcement learning architecture; a policy network outputs an action probability distribution according to a current environment state, selects a legal action with the maximum probability value and executes; a value network outputs a cumulative value estimation of the current environment state; after the action is executed, instant rewards and next state information are obtained, and the policy network and the value network are updated according to the obtained information; and a multi-objective optimization function based on macro placement constraints is constructed. Through deep fusion of reinforcement learning and constraint modeling, the application improves the automation level and design quality of macro unit placement, so as to meet the needs of low power consumption, high performance and compact area of high-speed communication chips.

The invention discloses an AI-assisted macro cell layout multiplexing method and system, and relates to the technical field of integrated circuit design. The method comprises the following steps: acquiring first position information in a target design environment, wherein the first position information comprises a target placement position of a first macro cell; acquiring second position information in the source design environment, wherein the second position information comprises original coordinates of a plurality of circuit elements in a second macro cell; automatically generating new coordinates of the plurality of circuit elements in the target design environment by utilizing a trained AI model based on the target placement position and the original coordinates; and generating a target layout file of the second macro-cell in the target design environment based on the new coordinates. According to the method, the coordinates are automatically adjusted through the AI, efficient multiplexing of the small macro-cells in the large macro-cells is achieved, manual modification is not needed, errors are remarkably reduced, the iteration period is shortened, PPA income is improved, and design flexibility is enhanced.

The invention belongs to the field of wireless communication in the Internet of Vehicles, and particularly relates to a V2X scene-oriented communication calculation fusion heterogeneous resource allocation method. The method comprises the following steps: firstly, constructing an Internet of Vehicles communication, sensing and calculation integrated system which comprises a vehicle, a base station, a road side unit and an edge calculation node; and secondly, comprehensively considering path loss, a multipath effect and a Doppler effect, and performing channel modeling on a 5G-Uu link, a C-V2X PC5 link and a Wi-Fi link by respectively adopting a macro cellular model, an Internet of Vehicles direct connection channel model and an IEEE 802.11 p model. Then, constructing a reinforcement learning resource optimization framework based on time scale layering, wherein an upper layer realizes proportional dynamic allocation of spectrum resources through dynamic resource pool division; and the lower layer jointly optimizes perception, communication and computing resource allocation in a set resource area. According to the method, on the premise of meeting various service quality constraints, the sum of the calculation cost, the communication cost and the penalty cost can be minimized, the total cost of the communication, sensing and calculation integrated architecture is minimized, and the resource utilization rate is improved.

A macro cell includes one or more vertical die interconnects that vertically span the macro cell to transmit a data signal. The macro cell also includes one or more isolation features configured to manage a power of the macro cell by controlling a transmission of the data signal. Additionally, the macro cell includes one or more flip-flops configured to control a timing of the transmission of the data signal through the one or more vertical die interconnects. Various other apparatuses and systems are also disclosed.

This invention belongs to the field of AI algorithm optimization technology for chip back-end component placement. It discloses a chip thermal placement method based on reinforcement learning. The method includes: obtaining the chip's register transfer level description file and electronic design automation tool output file; mapping the chip's three-dimensional thermal field onto a two-dimensional plane, pre-setting the chip's boundary conditions, initially analyzing the chip's temperature distribution and determining the rectangular shape of each macrocell and the heat source intensity function, further determining the chip's thermal field distribution and performing key optimizations using finite element analysis; modeling the chip placement process, processing the mask based on a policy network, obtaining macrocell placement actions, and determining the optimal thermal placement of the chip. This invention effectively ensures chip performance by simultaneously optimizing heat dissipation and line length, and avoids the local optima and non-convergence problems of traditional algorithms through reinforcement learning algorithms.

One technical scheme of the invention provides a complementary 3T storage unit. Another technical scheme of the invention is to provide a high-density bidirectional content addressable memory and in-memory logic integrated eDRAM macro cell. The invention provides a novel architecture based on an eDRAM (enhanced dynamic random access memory), the storage density is remarkably improved by optimizing a storage unit structure and a reading circuit, and meanwhile, bidirectional CAM (computer-aided memory) search and in-memory logic operation are supported. The technology is suitable for data-intensive applications such as artificial intelligence accelerators, network routers, genome analysis and the like which need efficient parallel search and near-memory calculation.

The invention provides an automatic generation method and system for a memory architecture, a medium, a program and an electronic terminal, and the method comprises the steps: retrieving and extracting at least one candidate storage macro-cell meeting a matching condition from a process library file according to a theoretical process parameter and a theoretical specification of a target memory in a demand information table; and based on a preset generation rule, determining at least one target memory architecture scheme formed by one or more candidate memory macro-units. Therefore, errors caused by human factors such as interface mismatching or signal conflicts are avoided, the efficiency is high, and the labor cost and the time cost of chip debugging and design are substantially reduced.

The application discloses a method and device for determining the staying duration of a target object in a target area. The method comprises: obtaining record time sequence data of the target object within a first preset duration, the record time sequence data being used for indicating the staying time of the target object recorded by a base station, and the record time sequence data comprising staying data of the target object recorded by a base station of an edge macro cell in the target area and staying data of the target object recorded by a base station of a neighboring cell of the edge macro cell; dividing the record time sequence data into a plurality of time sequence data sets in a second preset duration; determining the staying duration of the target object recorded by the base station in the target area in each time sequence data set; and adding the durations of the target object recorded by the base station in the target area in all time sequence data sets to obtain the target staying duration of the target object in the target area. The application solves the technical problem of low accuracy of the obtained staying duration of the target object.

The invention provides a 3D chip module layout method and system supporting autonomous clustering of macro-cells and multi-level modules as seeds. The 3D chip module layout method comprises the following steps: step 1, designating a level instance Hinst in design as a seed; 3, creating a clustering module for each seed in the seed division process; 3, inheriting network connection information of the original design, and constructing a seed-level network based on a pin connection relationship; 4, iteratively generating a 3D initial layout solution; and step 5, based on a simulated annealing algorithm, finally outputting a historical optimal 3D seed layout result, and distributing chip layer information die id in the layout result to each leaf instance in the seed. In the invention, the seed is a basic execution unit of subsequent three-dimensional layout, has the characteristics of compact structure and controllable scale, can effectively reduce the layout problem scale, keeps the local structure consistency, and remarkably improves the efficiency and quality of cross-layer division and space optimization.