5 results about "Custom instruction" patented technology

The application discloses a kind of coprocessing system, it includes: CPU, NPU and custom execution module;The CPU has custom instruction, and is used to send the custom instruction to the custom execution module;The custom execution module is used to convert the custom instruction, and is used to send the custom instruction after conversion to the NPU;The NPU is used to complete corresponding computing operation according to the custom instruction after conversion;Wherein, while the NPU is according to the custom instruction after conversion and carries out corresponding computing operation, the CPU can carry out other operations.The application also discloses a kind of central processing unit.The application in NPU according to the custom instruction after conversion and carries out corresponding computing operation, CPU can carry out other operations, so the characteristics that this CPU and NPU run different program simultaneously, greatly improve the execution efficiency of application.

The application provides an application method and system of a specific accelerator and the specific accelerator, the first processor comprises the specific accelerator, the specific accelerator is an FFT accelerator, the method comprises the following steps: obtaining instruction information, the instruction information is an instruction meeting a custom coding rule of a reduced instruction set; obtaining a required sampling point number and to-be-processed data based on the instruction information; selecting a delay feedback module in a preset delay feedback module set of the specific accelerator according to the sampling point number, and selecting a target twiddle factor storage unit in a twiddle factor storage module; enabling at least two delay feedback modules and the target twiddle factor storage unit to obtain a target accelerator circuit; inputting the to-be-processed data into the target accelerator circuit to obtain a calculation result. Since the specific accelerator can support custom instructions to perform calculation of different sampling point numbers, instruction extension is realized, the instruction extension matches the structure extension of the specific accelerator, and the structural form of the specific accelerator is improved.

A kind of architecture design method of polar code decoder based on custom instruction set, according to custom instruction control the hardware architecture of decoder, utilize instruction to control decoding process, reduce the error probability caused by circuit state in decoding process, so that the work of polar code decoder is more stable;FSC decoding algorithm is used to classify the nodes of SSC decoding tree into multiple different types of sub-nodes, and according to different sub-nodes, corresponding fast decoding is completed, the problems of large decoding delay, low throughput and not easy to realize hardware circuit are solved, the decoding speed and throughput of the decoder are improved, the decoding efficiency of polar code is improved, so that the work of polar code decoder is more stable.

This invention relates to a hardware acceleration method for the SM3 hash algorithm based on a custom RISC-V instruction set, comprising the following steps: Step A: Extending a custom instruction set into the RISC-V instruction set architecture. The custom instruction set includes a first type of instruction and a second type of instruction. The first type of instruction is used to trigger iterative calculation of the message expansion process in the SM3 algorithm, and the second type of instruction is used to trigger iterative calculation of the compression function process in the SM3 algorithm; Step B: Constructing a hardware acceleration unit decoupled from the processor pipeline. The hardware acceleration unit includes a message expansion pipeline module, a compression function pipeline module, a state control module, and a data concatenation unit; Step C: In response to the processor decoding unit recognizing the first type of instruction, loading the message data in the source operand register into the message expansion pipeline module. The message expansion pipeline module divides the message data into multiple message words according to the message expansion rules of the SM3 algorithm. This invention enables better hardware acceleration.

A lattice-based cryptography engine includes an interface configured to receive a lattice-based cryptographic operation request including corresponding operands. A register map is configured to store the operands and response to the request. A controller is coupled to receive the operands and output a sequence of instructions responsive to the request. A plurality of hardware units is coupled to receive and execute the instructions to generate the response. Each instruction is designated for one of the plurality of hardware units. A memory is coupled to the hardware units.