57 results about "Custom instruction" patented technology

The invention discloses an automatic compiling and adapting method for an RISC-V extension instruction, and belongs to the technical field of compilers. According to the method, a dynamic DSL (Digital Subscriber Line) for registering a custom instruction, adding register use constraints and defining a specific code mode is designed. The LLVM plug-in is used for automatically integrating the registered custom instruction in the compiling process. The invention relates to a self-defined instruction rapid adaptation mechanism which is specially provided for a continuously provided RISC-V self-defined instruction expansion scene, and by automatically generating correct assembly codes of registered self-defined instructions, correct registers are automatically distributed and reserved according to register use constraints; the method comprises the following steps of: searching a defined specific code mode and semantics, and automatically generating and inserting a registered custom instruction in a program, so as to realize the rapid adaptation of a compiler to an RISC-V custom extension instruction and the automatic use of a program code to the custom instruction, and the whole process does not need a developer to manually modify the compiler or a program source code.

The invention discloses a multi-modal-based multi-language custom instruction identification method and system, and the method comprises the steps: S1, constructing a multi-modal large model, and training the model, the multi-modal large model constructing a support input processing unit, a query input processing unit and a measurement discriminator; s2, on the basis of the step S1, registering a user-defined voice instruction; wherein a support feature vector of a user registration instruction is acquired and stored through the support input processing unit trained in the step S1; s3, user voice is obtained, and reasoning and instruction recognition are conducted through the model generated in the step S2; wherein the trained query input processing unit is used for processing the user voice to output a query vector, and the matching degree of the query vector and a pre-stored support feature vector is calculated, so that a user voice instruction is recognized. According to the method, efficient and extensible multi-language self-defined instruction recognition is realized based on a multi-modal fusion and metric learning framework.

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

The invention discloses a compiling method for compiling a C language source code into an RISC-V assembly code. The method comprises the following steps: acquiring a C language source code; performing lexical analysis on the C language source code to generate a mark flow; performing syntactic analysis on the mark flow, and constructing an abstract syntax tree; performing semantic analysis on the abstract syntax tree to generate a target abstract syntax tree; constructing a runtime environment of the RISC-V assembly code; generating an intermediate code and a control flow diagram corresponding to the intermediate code according to a rule in the runtime environment and the target abstract syntax tree; generating a target code by using the intermediate code and the control flow diagram corresponding to the intermediate code; according to the technical scheme, the intermediate representation more adaptive to RISC-V custom instruction mapping can be generated, so that the execution efficiency of assembly codes is improved; and meanwhile, by designing a lightweight runtime environment, the performance overhead is further reduced.

Disclosed herein are methods, systems, and computer-readable media for interacting with a language model using custom instructions. In one embodiment a method includes receiving, through an interface, custom instructions, the custom instructions comprising at least one of personal information or a response type preference, storing the custom instructions temporarily within a session specific cache, in response to a trigger event, adding the custom instructions to a system message associated with the language model, the system message being a prompt modifier to the language model, in response to receiving a prompt, retrieving the custom instructions from the session specific cache, determining whether the custom instructions are relevant to the prompt, and in response to determining the custom instructions are relevant to the prompt, generating a response to the prompt based on the custom instructions.

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

The invention belongs to the technical field of chip testing, and discloses a testing device and method for an RISC-V chip instruction cache, and the device comprises a CPU core, a cache controller, a user-defined instruction execution module, and an instruction cache. The CPU core is used for receiving a test starting address and a test ending address; sending a clearing instruction to the instruction buffer; and executing a test step: generating an instruction reading address according to the test starting address, sending the instruction reading address to the cache controller until a test ending address, receiving a test instruction of the cache controller, judging whether the test instruction is a self-defined instruction, and if so, sending the test instruction to a self-defined instruction execution module to obtain an instruction execution result; and executing the test step again, and obtaining an instruction cache test result according to an obtained instruction execution result. The RISC-V chip instruction buffer test method and the RISC-V chip instruction buffer test device can realize comprehensive test of the RISC-V chip instruction buffer under the condition of avoiding increasing a large amount of chip cost area.

Disclosed herein are methods, systems, and computer-readable media for interacting with a language model using custom instructions. In one embodiment a method includes receiving, through an interface, custom instructions, the custom instructions comprising at least one of personal information or a response type preference, storing the custom instructions temporarily within a session specific cache, in response to a trigger event, adding the custom instructions to a system message associated with the language model, the system message being a prompt modifier to the language model, in response to receiving a prompt, retrieving the custom instructions from the session specific cache, determining whether the custom instructions are relevant to the prompt, and in response to determining the custom instructions are relevant to the prompt, generating a response to the prompt based on the custom instructions.

The present invention discloses a method and device for obtaining a custom instruction template. The method includes: obtaining a custom instruction template entry request sent by a target user; based on the custom instruction template entry request, collecting a static period target signal and an instruction entry period target signal; performing quality detection on the static period target signal and the instruction entry period target signal to obtain a signal quality detection result; if the quality detection result meets a preset quality condition, performing feature extraction on the instruction entry period target signal to obtain a signal feature; performing similarity matching between the signal feature and the corresponding signal feature of a pre-stored custom instruction template; if the similarity meets the preset similarity condition, the custom instruction template entry is successful; otherwise, the custom instruction template entry fails and a prompt message is output. The method can effectively screen out low-quality signals due to environmental factors, improve the quality of custom instruction template entry, optimize the personalized interactive experience, and enhance the device response accuracy and execution effect.

A processor includes an instruction decoder configured to provide at least a floating point instruction control signal; performing floating point calculation on a data path; a floating point custom instruction control logic block coupled to the floating point compute data path; a control and status register coupled to the floating point computational data path and the floating point custom instruction control logic block; a first multiplexer configured to provide a floating-point instruction control signal or a custom instruction control signal to the floating-point computational data path based on a state of a selection control signal; and a second multiplexer configured to provide a floating point operand or a custom operand to the floating point computing data path based on a state of the selection control signal. The floating point custom instruction control logic block asserts a select signal while directing the floating point computational data path to assist it in executing custom instructions. The custom instruction may be a floating point exponential function.

This application relates to a pulse modulation control system, device, and method. The system includes a processor based on a RISC-V open-source instruction set architecture and a pulse modulation interface module. The processor is configured to receive an operation instruction of a user, and generate a data signal based on the operation instruction. The pulse modulation interface module is connected to the processor, and is configured to receive the data signal and output a preset waveform based on the data signal. Based on the RISC-V open-source instruction set architecture, the user may customize operations, which improves efficiency and flexibility of a pulse modulation process, and optimizes power consumption.

The present invention relates to a system and method for queuing in custom instruction extension of a hardened processor (203) such as a RISC-V processor implemented on a System-on-Chip (SoC) fabric; which enables high performance for said RISC-V processor (203) when interacting with any custom accelerator (205) via custom instruction extension (207) due to the reduced latency in waiting for a response from said custom accelerator (205). The system and method of the present invention also facilities clock domain crossing between the high frequency hardened processor (203) and the lower frequency custom accelerator (205), thus simplifying the design requirements for the custom accelerator (205) to close the timing gap. Besides that, the system and method of the present invention also supports blocking and non-blocking implementations of the queueing capability without needing for updates to the register transfer level (RTL) design.

The invention discloses a target vehicle control method and device, a medium and electronic equipment, and the method comprises the steps: receiving a voice control instruction of a target user; a target operation library of the target user is obtained, the target operation library comprises a user-defined operation library and a preset operation library, the user-defined operation library comprises at least one set of user-defined instructions and user-defined operations with the corresponding relation, and the preset operation library comprises at least one set of preset instructions and preset operations with the corresponding relation; determining a first instruction matched with the voice control instruction and a first operation corresponding to the first instruction from a user-defined operation library; controlling the target vehicle to execute the first operation; if the first instruction does not exist in the user-defined operation library, determining a second instruction matched with the voice control instruction and a second operation corresponding to the second instruction from a preset operation library; and controlling the target vehicle to execute the second operation. Through the technical scheme provided by the invention, the control efficiency of the target vehicle can be improved.

This application relates to a method and an apparatus for determining a cooker hood operating strategy, a device, a storage medium, and a program product. The method includes: controlling a cooker hood to enter a user-oriented engineering mode, and in the engineering mode, receiving a customization instruction issued by a user is received through a human-computer interaction interface, to determine a primary evaluation indicator and a secondary evaluation indicator of a cooker hood operating parameter customized by the user; and adjusting the cooker hood operating parameter according to the primary evaluation indicator and the secondary evaluation indicator, to obtain a target operating parameter satisfying a user customization condition, and configuring a target operating level according to the target operating parameter. In this application, in the user-oriented engineering mode, an evaluation indicator during operation of a cooker hood is determined according to the customization instruction of the user, and operation of the cooker hood is controlled according to the evaluation indicator customized by the user. For users with different requirements, in the control method of this application, a cooker hood operating state that balances performance and user satisfaction can be achieved, to reduce operating noise of the cooker hood, thereby improving user experience.

The invention relates to the technical field of research and development frameworks, and provides an exposure point burying method and device, computer equipment and a readable storage medium, and the method comprises the steps: generating a user-defined instruction according to preset exposure point burying logic; binding the custom instruction to the target DOM element, and dynamically binding the burying point data through the attribute of the target DOM element; constructing a viewport detection module based on a native intersection observer application program interface of the browser, and monitoring the intersection state of the target DOM element and a viewport in real time; when the target DOM element enters a viewport and meets a preset exposure condition, executing burying point reporting through a delay trigger mechanism, and recording reported burying point data through a cache list to realize duplicate removal processing; the preset exposure condition comprises a residence time threshold value of the element in the viewport. According to the method, the problem of pain points of a traditional point burying technology in the vertical field is effectively solved through technical innovation, and an efficient and reliable exposure point burying solution is provided for the industries of finance, medical health, old-age care and the like.

The invention relates to a network processor and a chip, and the method comprises the steps: an instruction assembly line receives and analyzes a customer-defined instruction, reads a source data list and a command list from a storage module according to instruction analysis information, and transmits the source data list and the command list to a finite-state machine; in the finite-state machine, a data buffer stores source data and a command execution result, a command buffer stores a command list, a state controller reads a target command from the command list in sequence, obtains target source data from the data buffer according to the target command, then generates a task request and sends the task request to an execution unit, and the execution unit executes the task request. A command result returned by the execution unit is received and written into the data buffer, and finally, after the command list is executed, a write-back data write-back storage module is generated according to data in the data buffer. According to the method and the device, a customer can customize the custom instruction according to own requirements in the chip use process, and the utilization rate of the execution unit in the instruction assembly line is improved.

Provided is a method for performing computations near memory. The method includes receiving, at a storage device, first data associated with a first data set, the first data having a first format. The method further includes receiving, at a processor core of the storage device, a request to perform a function on the first data, the function including a first operation and a second operation. The method further includes performing, by a first processor-core acceleration engine of the storage device, the first operation on the first data, based on first processor-core custom instructions, to generate first result data. The method further includes performing, by a first extra-processor-core circuit of the storage device, the second operation on the first result data, based on the first processor-core custom instructions.

The present invention provides a vehicle control information processing method, a remote control method, an apparatus, and a storage medium. The vehicle control information processing method includes: displaying a control condition set and an execution object set in response to an instruction creation operation; establishing a correspondence between each target control condition in the control condition set and each target object in the execution object set; wherein each target object corresponds to at least one target control condition; generating a target control instruction for each target object based on the correspondence; and generating object control information based on the target control instruction corresponding to each target object. The technical solution of the present application, by establishing a correspondence between each target control condition in the control condition set and each target object in the execution object set, allows the user to pre-define a number of custom instructions through the client and implement remote control of objects in the vehicle computer, thereby improving the user's flexibility and convenience in controlling the vehicle and increasing the fun of human-computer interaction.

The embodiment of the invention provides a code protection method, electronic equipment and a storage medium, and the method comprises the steps: analyzing a preset program, and determining a target code in the preset program; designing a custom instruction based on the target code; and adjusting a tool chain based on the custom instruction, and generating an executable file corresponding to the target code based on the adjusted tool chain. According to the embodiment of the invention, by designing the custom instruction of the key code, the difficulty of reverse engineering of the code is increased, so that the source code is effectively protected, and key confidential information in the code is prevented from being leaked.

The invention discloses an image processing method and device, a nonvolatile storage medium and computer equipment. The method comprises the following steps: acquiring an original image, a background image of the original image and an initial effect image; based on a preset custom instruction, parameters in the fragment shader are set, and the custom instruction is an expansion instruction used for generating a target effect for the original image; based on the fragment shader after parameter setting, extracting color values of a plurality of pixel points of the original image; determining gray values of the plurality of pixel points of the original image based on the color values of the plurality of pixel points of the original image; based on the gray values of the plurality of pixel points of the original image, adjusting the transparency of the plurality of pixel points of the initial effect image to obtain a target effect image; and superposing the target effect image on the background image to obtain a target image under the leaf hollow-out effect. The technical problems of manual design cost and high efficiency of the leaf hollowing effect in the traditional image processing flow are solved.

The invention discloses a communication interface simulation system, a data transmission method, equipment and a medium. The communication interface simulation system comprises a user-defined instruction set kernel and a user-defined instruction execution unit, the user-defined instruction set kernel and the user-defined instruction execution unit are connected through a plurality of user-defined instruction interfaces, and a task driving unit controls a target clock line sub-interface and a first data sub-interface in a target universal interface group in the user-defined instruction execution unit to be in an access state. The user-defined instruction execution unit executes a first user-defined instruction selected by the user-defined instruction set kernel, so that the clock structure outputs a first time sequence signal through a target clock line sub-interface after executing automatic flipping, and meanwhile, a target output shift register performs shift processing on first data to obtain a first shift result; outputting a first shift result through the first data sub-interface; therefore, each component in the communication interface simulation system is indicated to work through a user-defined instruction so as to simulate the communication interface, the instruction interaction can be reduced, and the simulation efficiency of the communication interface is improved.

The application discloses a kind of coprocessing system, it includes: CPU, NPU and custom execution module;The CPU has custom instruction, and is used to send the custom instruction to the custom execution module;The custom execution module is used to convert the custom instruction, and is used to send the custom instruction after conversion to the NPU;The NPU is used to complete corresponding computing operation according to the custom instruction after conversion;Wherein, while the NPU is according to the custom instruction after conversion and carries out corresponding computing operation, the CPU can carry out other operations.The application also discloses a kind of central processing unit.The application in NPU according to the custom instruction after conversion and carries out corresponding computing operation, CPU can carry out other operations, so the characteristics that this CPU and NPU run different program simultaneously, greatly improve the execution efficiency of application.

The application provides an application method and system of a specific accelerator and the specific accelerator, the first processor comprises the specific accelerator, the specific accelerator is an FFT accelerator, the method comprises the following steps: obtaining instruction information, the instruction information is an instruction meeting a custom coding rule of a reduced instruction set; obtaining a required sampling point number and to-be-processed data based on the instruction information; selecting a delay feedback module in a preset delay feedback module set of the specific accelerator according to the sampling point number, and selecting a target twiddle factor storage unit in a twiddle factor storage module; enabling at least two delay feedback modules and the target twiddle factor storage unit to obtain a target accelerator circuit; inputting the to-be-processed data into the target accelerator circuit to obtain a calculation result. Since the specific accelerator can support custom instructions to perform calculation of different sampling point numbers, instruction extension is realized, the instruction extension matches the structure extension of the specific accelerator, and the structural form of the specific accelerator is improved.

The invention provides a data processing method and device based on a vector processor and a user-defined instruction accelerator, and relates to the technical field of satellite positioning and navigation. The method comprises the following steps of: extracting components with data-level parallel processing characteristics and components capable of being accelerated through a custom instruction based on calculation-intensive operation in a baseband tracking algorithm, and respectively mapping the components on a vector processor and a custom instruction accelerator to obtain a target vector processor and a target custom instruction accelerator; performing correlation operation on the baseband signals of the plurality of channels by using a tracking engine to generate correlation values of the plurality of channels; dumping the correlation values of the plurality of channels based on the timing period of the intermediate frequency sampling clock to obtain multi-channel correlation values with aligned time; recombining the multi-channel correlation values based on the variable names to obtain a plurality of continuous vector data blocks; and performing tracking acceleration on the plurality of vector data blocks by using a target vector processor and a target custom instruction accelerator to obtain a target tracking result.

The present application relates to the field of computation acceleration. Provided is an architectural method for a variable instruction of a processor. The method comprises: executing a custom instruction to specify an FPGA to complete a custom operation, wherein the custom instruction comprises configuration data or a data address pointing to the configuration data; when the custom instruction comprises the configuration data, the FPGA loading the configuration data to complete the custom operation; and when the custom instruction comprises the data address, the FPGA accessing the data address to load the configuration data, so as to complete the custom operation; and in response to the custom instruction, the FPGA storing a result of the custom operation in a register or a memory. A custom instruction carries configuration data or a data address pointing to the configuration data, and the custom instruction is executed to specify an FPGA to complete a custom operation, and thus the FPGA is used for completing a custom operation task.

The invention belongs to the technical field of computer system simulation, and particularly relates to a heterogeneous prototype verification system and method based on a transaction-level model, and the method comprises the steps: operating a virtual machine monitor and the transaction-level model on a host machine; instantiating a client host and a client slave through a virtual machine monitor, and respectively simulating a universal processor and acceleration equipment; the execution of the standard instructions in the client slave is accelerated through the instruction set simulator; executing the self-defined instruction in the client and the slave through the hardware accelerator; bus transaction logic is simulated by using the transaction-level model, and communication between the virtual machine monitor and the transaction-level model is realized through a unified communication protocol; state spaces of a virtual machine monitor, an instruction set emulator, and a hardware accelerator are synchronized. The problem that a traditional simulation tool cannot effectively integrate different types of simulation components is effectively solved, a unified verification platform is provided for a heterogeneous system, and the system-level verification efficiency is improved.

The invention provides a high-order sparse matrix LDL efficient decomposition calculation acceleration method, which can be used for a high-order sparse matrix linear equation set solving calculation scene. The accelerator is constructed based on an FPGA platform, and efficient decomposition of a high-order sparse matrix is achieved through a software and hardware cooperative computing mechanism. The software level realizes symbolic analysis of a sparse positive definite matrix, calculation sequence dependency modeling and LDL decomposition hardware customization instruction generation; and the hardware acceleration unit realizes streamlined execution of decomposition tasks by performing instruction fetching, decoding and execution of customized instructions, and completes high-order matrix numerical calculation. The system comprises an instruction generation unit, an instruction analysis unit, a calculation module, a data access module and a control scheduling module, and all the modules work cooperatively to improve the degree of parallelism and the storage access efficiency. Matrix data types support fp16, fp32 and fp64, matrix compression is realized by adopting a sparse column (CSC) format and a matrix rearrangement method, and storage overhead and memory access delay are remarkably reduced while high calculation precision is ensured. Experiments show that compared with traditional CPU and GPU platforms, the sparse matrix solution performance and energy efficiency of the method are remarkably improved by one order of magnitude, and the method is suitable for high-precision engineering calculation and edge real-time solution scenes such as engineering simulation, structural mechanics, electromagnetic analysis and attitude calculation.

The invention provides a customizable interactive video production method and system based on an AI technology. The method comprises the following steps: receiving an interactive customization instruction of a user for a target material segment; comparing the interactive customization instruction with the description tag of the target material segment, generating a customization instruction feature set, and generating a customization data stream based on the customization instruction feature set; performing compatibility verification on a new material fragment in the customized data stream and an original context material to obtain a consistency score, when the consistency score is greater than a preset compatibility threshold, updating the material mapping relation table, and binding the new material fragment to a description node in an interaction logic description file, meanwhile, the directions of the affected branch paths are adjusted; and generating an interactive video project file package of the video engine by using the updated interactive logic description file, the material mapping relation table and all the associated material fragments. By adopting the scheme, conditional generation and automatic logic adaptation of the interactive video content can be realized.

The invention relates to a DSP enhancement system based on RISC-V vector extension, which enhances RISC-V vector extension by using a customized DSP instruction, integrates data buffer layer automatic cycle addressing and hardware switching logic, replaces traditional DMA explicit handling or software address updating, reduces data handling delay reduction and bus bandwidth occupancy rate, realizes zero-overhead data flow management, and improves the reliability of the system. Finally, the complex signal processing cycle number performance and energy efficiency of the embedded system are remarkably improved, meanwhile, backward compatibility is kept, software reuse is fully achieved, the efficient signal processing capacity is achieved, the requirements of various end side AI inference signal processing workloads are met, and the application in complex signal processing is greatly improved.

The invention discloses a PID control optimization method based on an RVV, and the method comprises the following steps: reasonably dividing data according to the calculation demands of PID multi-loop control, and mapping the data to an RISCV vector register file; key parameters of multi-loop PID control are calculated and stored in a global data structure; core calculation operations related to PID control are expanded and optimized by using an RISCV instruction, such as error calculation, proportional operation and the like; a compiler is customized to support an extended instruction set, and it is ensured that data calculation in the PID control process can make full use of the parallel capacity of an RISCV hardware architecture; the PID calculation process is further accelerated through parallel calculation, and the real-time response capability is improved; the invention aims to provide an efficient PID parallel computing method based on RISCV vector extension (RVV) aiming at the defects in the current PID computing optimization, through vector computing, customized instruction optimization and multi-loop data flow optimization, the computing efficiency of PID control is greatly improved, the power consumption of a system is reduced, and the system performance is improved. And an efficient calculation solution is provided for intelligent control, industrial automation and robot control in the future.