37 results about "Custom instruction" patented technology

The invention discloses an automatic compiling and adapting method for an RISC-V extension instruction, and belongs to the technical field of compilers. According to the method, a dynamic DSL (Digital Subscriber Line) for registering a custom instruction, adding register use constraints and defining a specific code mode is designed. The LLVM plug-in is used for automatically integrating the registered custom instruction in the compiling process. The invention relates to a self-defined instruction rapid adaptation mechanism which is specially provided for a continuously provided RISC-V self-defined instruction expansion scene, and by automatically generating correct assembly codes of registered self-defined instructions, correct registers are automatically distributed and reserved according to register use constraints; the method comprises the following steps of: searching a defined specific code mode and semantics, and automatically generating and inserting a registered custom instruction in a program, so as to realize the rapid adaptation of a compiler to an RISC-V custom extension instruction and the automatic use of a program code to the custom instruction, and the whole process does not need a developer to manually modify the compiler or a program source code.

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

The invention discloses a compiling method for compiling a C language source code into an RISC-V assembly code. The method comprises the following steps: acquiring a C language source code; performing lexical analysis on the C language source code to generate a mark flow; performing syntactic analysis on the mark flow, and constructing an abstract syntax tree; performing semantic analysis on the abstract syntax tree to generate a target abstract syntax tree; constructing a runtime environment of the RISC-V assembly code; generating an intermediate code and a control flow diagram corresponding to the intermediate code according to a rule in the runtime environment and the target abstract syntax tree; generating a target code by using the intermediate code and the control flow diagram corresponding to the intermediate code; according to the technical scheme, the intermediate representation more adaptive to RISC-V custom instruction mapping can be generated, so that the execution efficiency of assembly codes is improved; and meanwhile, by designing a lightweight runtime environment, the performance overhead is further reduced.

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

Disclosed herein are methods, systems, and computer-readable media for interacting with a language model using custom instructions. In one embodiment a method includes receiving, through an interface, custom instructions, the custom instructions comprising at least one of personal information or a response type preference, storing the custom instructions temporarily within a session specific cache, in response to a trigger event, adding the custom instructions to a system message associated with the language model, the system message being a prompt modifier to the language model, in response to receiving a prompt, retrieving the custom instructions from the session specific cache, determining whether the custom instructions are relevant to the prompt, and in response to determining the custom instructions are relevant to the prompt, generating a response to the prompt based on the custom instructions.

This application relates to a method and an apparatus for determining a cooker hood operating strategy, a device, a storage medium, and a program product. The method includes: controlling a cooker hood to enter a user-oriented engineering mode, and in the engineering mode, receiving a customization instruction issued by a user is received through a human-computer interaction interface, to determine a primary evaluation indicator and a secondary evaluation indicator of a cooker hood operating parameter customized by the user; and adjusting the cooker hood operating parameter according to the primary evaluation indicator and the secondary evaluation indicator, to obtain a target operating parameter satisfying a user customization condition, and configuring a target operating level according to the target operating parameter. In this application, in the user-oriented engineering mode, an evaluation indicator during operation of a cooker hood is determined according to the customization instruction of the user, and operation of the cooker hood is controlled according to the evaluation indicator customized by the user. For users with different requirements, in the control method of this application, a cooker hood operating state that balances performance and user satisfaction can be achieved, to reduce operating noise of the cooker hood, thereby improving user experience.

The invention relates to the technical field of research and development frameworks, and provides an exposure point burying method and device, computer equipment and a readable storage medium, and the method comprises the steps: generating a user-defined instruction according to preset exposure point burying logic; binding the custom instruction to the target DOM element, and dynamically binding the burying point data through the attribute of the target DOM element; constructing a viewport detection module based on a native intersection observer application program interface of the browser, and monitoring the intersection state of the target DOM element and a viewport in real time; when the target DOM element enters a viewport and meets a preset exposure condition, executing burying point reporting through a delay trigger mechanism, and recording reported burying point data through a cache list to realize duplicate removal processing; the preset exposure condition comprises a residence time threshold value of the element in the viewport. According to the method, the problem of pain points of a traditional point burying technology in the vertical field is effectively solved through technical innovation, and an efficient and reliable exposure point burying solution is provided for the industries of finance, medical health, old-age care and the like.

The invention relates to a network processor and a chip, and the method comprises the steps: an instruction assembly line receives and analyzes a customer-defined instruction, reads a source data list and a command list from a storage module according to instruction analysis information, and transmits the source data list and the command list to a finite-state machine; in the finite-state machine, a data buffer stores source data and a command execution result, a command buffer stores a command list, a state controller reads a target command from the command list in sequence, obtains target source data from the data buffer according to the target command, then generates a task request and sends the task request to an execution unit, and the execution unit executes the task request. A command result returned by the execution unit is received and written into the data buffer, and finally, after the command list is executed, a write-back data write-back storage module is generated according to data in the data buffer. According to the method and the device, a customer can customize the custom instruction according to own requirements in the chip use process, and the utilization rate of the execution unit in the instruction assembly line is improved.

Provided is a method for performing computations near memory. The method includes receiving, at a storage device, first data associated with a first data set, the first data having a first format. The method further includes receiving, at a processor core of the storage device, a request to perform a function on the first data, the function including a first operation and a second operation. The method further includes performing, by a first processor-core acceleration engine of the storage device, the first operation on the first data, based on first processor-core custom instructions, to generate first result data. The method further includes performing, by a first extra-processor-core circuit of the storage device, the second operation on the first result data, based on the first processor-core custom instructions.

The embodiment of the invention provides a code protection method, electronic equipment and a storage medium, and the method comprises the steps: analyzing a preset program, and determining a target code in the preset program; designing a custom instruction based on the target code; and adjusting a tool chain based on the custom instruction, and generating an executable file corresponding to the target code based on the adjusted tool chain. According to the embodiment of the invention, by designing the custom instruction of the key code, the difficulty of reverse engineering of the code is increased, so that the source code is effectively protected, and key confidential information in the code is prevented from being leaked.

The invention discloses an image processing method and device, a nonvolatile storage medium and computer equipment. The method comprises the following steps: acquiring an original image, a background image of the original image and an initial effect image; based on a preset custom instruction, parameters in the fragment shader are set, and the custom instruction is an expansion instruction used for generating a target effect for the original image; based on the fragment shader after parameter setting, extracting color values of a plurality of pixel points of the original image; determining gray values of the plurality of pixel points of the original image based on the color values of the plurality of pixel points of the original image; based on the gray values of the plurality of pixel points of the original image, adjusting the transparency of the plurality of pixel points of the initial effect image to obtain a target effect image; and superposing the target effect image on the background image to obtain a target image under the leaf hollow-out effect. The technical problems of manual design cost and high efficiency of the leaf hollowing effect in the traditional image processing flow are solved.

The application discloses a kind of coprocessing system, it includes: CPU, NPU and custom execution module;The CPU has custom instruction, and is used to send the custom instruction to the custom execution module;The custom execution module is used to convert the custom instruction, and is used to send the custom instruction after conversion to the NPU;The NPU is used to complete corresponding computing operation according to the custom instruction after conversion;Wherein, while the NPU is according to the custom instruction after conversion and carries out corresponding computing operation, the CPU can carry out other operations.The application also discloses a kind of central processing unit.The application in NPU according to the custom instruction after conversion and carries out corresponding computing operation, CPU can carry out other operations, so the characteristics that this CPU and NPU run different program simultaneously, greatly improve the execution efficiency of application.

The application provides an application method and system of a specific accelerator and the specific accelerator, the first processor comprises the specific accelerator, the specific accelerator is an FFT accelerator, the method comprises the following steps: obtaining instruction information, the instruction information is an instruction meeting a custom coding rule of a reduced instruction set; obtaining a required sampling point number and to-be-processed data based on the instruction information; selecting a delay feedback module in a preset delay feedback module set of the specific accelerator according to the sampling point number, and selecting a target twiddle factor storage unit in a twiddle factor storage module; enabling at least two delay feedback modules and the target twiddle factor storage unit to obtain a target accelerator circuit; inputting the to-be-processed data into the target accelerator circuit to obtain a calculation result. Since the specific accelerator can support custom instructions to perform calculation of different sampling point numbers, instruction extension is realized, the instruction extension matches the structure extension of the specific accelerator, and the structural form of the specific accelerator is improved.

The invention belongs to the technical field of computer system simulation, and particularly relates to a heterogeneous prototype verification system and method based on a transaction-level model, and the method comprises the steps: operating a virtual machine monitor and the transaction-level model on a host machine; instantiating a client host and a client slave through a virtual machine monitor, and respectively simulating a universal processor and acceleration equipment; the execution of the standard instructions in the client slave is accelerated through the instruction set simulator; executing the self-defined instruction in the client and the slave through the hardware accelerator; bus transaction logic is simulated by using the transaction-level model, and communication between the virtual machine monitor and the transaction-level model is realized through a unified communication protocol; state spaces of a virtual machine monitor, an instruction set emulator, and a hardware accelerator are synchronized. The problem that a traditional simulation tool cannot effectively integrate different types of simulation components is effectively solved, a unified verification platform is provided for a heterogeneous system, and the system-level verification efficiency is improved.

The invention provides a high-order sparse matrix LDL efficient decomposition calculation acceleration method, which can be used for a high-order sparse matrix linear equation set solving calculation scene. The accelerator is constructed based on an FPGA platform, and efficient decomposition of a high-order sparse matrix is achieved through a software and hardware cooperative computing mechanism. The software level realizes symbolic analysis of a sparse positive definite matrix, calculation sequence dependency modeling and LDL decomposition hardware customization instruction generation; and the hardware acceleration unit realizes streamlined execution of decomposition tasks by performing instruction fetching, decoding and execution of customized instructions, and completes high-order matrix numerical calculation. The system comprises an instruction generation unit, an instruction analysis unit, a calculation module, a data access module and a control scheduling module, and all the modules work cooperatively to improve the degree of parallelism and the storage access efficiency. Matrix data types support fp16, fp32 and fp64, matrix compression is realized by adopting a sparse column (CSC) format and a matrix rearrangement method, and storage overhead and memory access delay are remarkably reduced while high calculation precision is ensured. Experiments show that compared with traditional CPU and GPU platforms, the sparse matrix solution performance and energy efficiency of the method are remarkably improved by one order of magnitude, and the method is suitable for high-precision engineering calculation and edge real-time solution scenes such as engineering simulation, structural mechanics, electromagnetic analysis and attitude calculation.

The invention provides a customizable interactive video production method and system based on an AI technology. The method comprises the following steps: receiving an interactive customization instruction of a user for a target material segment; comparing the interactive customization instruction with the description tag of the target material segment, generating a customization instruction feature set, and generating a customization data stream based on the customization instruction feature set; performing compatibility verification on a new material fragment in the customized data stream and an original context material to obtain a consistency score, when the consistency score is greater than a preset compatibility threshold, updating the material mapping relation table, and binding the new material fragment to a description node in an interaction logic description file, meanwhile, the directions of the affected branch paths are adjusted; and generating an interactive video project file package of the video engine by using the updated interactive logic description file, the material mapping relation table and all the associated material fragments. By adopting the scheme, conditional generation and automatic logic adaptation of the interactive video content can be realized.

The invention relates to a DSP enhancement system based on RISC-V vector extension, which enhances RISC-V vector extension by using a customized DSP instruction, integrates data buffer layer automatic cycle addressing and hardware switching logic, replaces traditional DMA explicit handling or software address updating, reduces data handling delay reduction and bus bandwidth occupancy rate, realizes zero-overhead data flow management, and improves the reliability of the system. Finally, the complex signal processing cycle number performance and energy efficiency of the embedded system are remarkably improved, meanwhile, backward compatibility is kept, software reuse is fully achieved, the efficient signal processing capacity is achieved, the requirements of various end side AI inference signal processing workloads are met, and the application in complex signal processing is greatly improved.

The invention discloses an RISC-V processor, subsystem and method for accelerating sparse left view LU decomposition, and aims to solve the problem of low discontinuous memory access efficiency in sparse matrix calculation. The processor comprises a processor control unit, a scalar core, a vector processing unit and an input / output interface. The scalar core is based on an RV32IMF instruction set and supports ZFINX expansion; the vector processing unit is provided with a 128-bit vector register file, supports four-channel vector operation, integrates a self-defined instruction GmacS, and is used for merging vector aggregation loading, scalar-vector multiply-accumulate and disperse storage operations and reducing instruction overhead. And the subsystems cooperate with the main CPU through DMA to efficiently unload computation-intensive tasks. Experiments show that compared with an original algorithm, the performance of the scheme is improved by 3.8 times at most, and the scheme is suitable for sparse matrix calculation scenes such as circuit simulation and has the advantages of high energy efficiency and low delay.

1. The name of the design product: smart application generation graphical user interface of electronic device. 2. The use of the design product: an electronic device. 3. The design points of the design product: the part of the graphical user interface in the electronic device is claimed. 4. The picture or photo that best indicates the design points: design 1 front view. 5. Design 1 is designated as the basic design. 6. The use of the graphical user interface: the graphical user interface is used for smart conversation. The part of the graphical user interface claimed is used to generate applications. The graphical user interface can be interacted with by the user clicking on the graphical user interface or by mouse operation. The user inputs initial instructions in the input box below the graphical user interface and sends them, while displaying associated content, the user hovers the mouse over the associated content to be selected, the graphical user interface is as shown in design 1 front view, clicks to select the associated content and sends the selected associated content as the first instruction, the graphical user interface changes from design 1 front view to design 1 change state diagram 1 to display automatically generated function options, clicks to select the function option and sends the selected function as the second instruction, the graphical user interface changes from design 1 change state diagram 1 to design 1 change state diagram 2 to display automatically generated application type options, clicks the target application type option, the graphical user interface changes from design 1 change state diagram 2 to design 1 change state diagram 3 to display application module options generated according to historical instructions. The user inputs initial instructions in the input box below the graphical user interface and sends them, while displaying associated content, the graphical user interface is as shown in design 2 front view, inputs custom instructions in the input box below the graphical user interface and clicks to send, the graphical user interface changes from design 2 front view to design 2 change state diagram 1 to display automatically generated function options, inputs custom function requirements in the input box and clicks to send, the graphical user interface changes from design 2 change state diagram 1 to design 2 change state diagram 2 to display automatically generated application type options, inputs custom application type in the input box and clicks to send, the graphical user interface changes from design 2 change state diagram 2 to design 2 change state diagram 3 to display application module options generated according to historical instructions. The user inputs an initial instruction in the input box below the graphical user interface as shown in Design 3 Home View and sends it, while the associated content is displayed. The user inputs a custom instruction in the input box below the graphical user interface and clicks Send, and the graphical user interface changes from Design 3 Home View to Design 3 Change State Figure 1 to display automatically generated function options. The user inputs a custom function requirement in the input box and clicks Send, and the graphical user interface changes from Design 3 Change State Figure 1 to Design 3 Change State Figure 2 to display application module options generated according to historical instructions. 7. Other conditions requiring explanation Other explanation: The dashed lines in each view of Design 1 to Design 3 show part of the graphical user interface, which does not constitute part of the appearance design claimed.

The invention provides a throttling implementation method and system based on a Vue custom instruction, a medium and equipment, and the method comprises the steps: creating a throttling core function based on a Vue framework, returning a target function of throttling packaging according to the target function, and determining the Vue-based custom instruction; based on a throttling core function in the Vue custom instruction, a preset timestamp comparison algorithm is adopted to control the execution frequency of a target function; constructing an instruction definition object based on the Vue custom instruction; and controlling the execution frequency of the original event processing function by adopting a Vue-based custom instruction. Through the application, throttling control is realized based on the Vue custom instruction, code redundancy is reduced, complex configuration is reduced, development efficiency is improved, millisecond-level precision control and 100% context binding accuracy are realized, and the risk of memory leakage is reduced.

The invention provides a ripple animation implementation method and system based on a Vue custom instruction. The method comprises the following steps: creating a ripple animation Vue instruction; creating a ripple animation click event processing function in the ripple animation Vue instruction, and determining a ripple effect of the target element according to configuration parameters of the ripple animation click event processing function; a ripple animation Vue instruction is registered in the Vue application; and dynamically updating the ripple animation according to the update state of the target element based on the ripple animation Vue instruction. According to the application, a reusable, configurable and automatically managed Vue ripple animation instruction is realized based on a ripple animation binding technology of a Vue custom instruction, and the problems of complex realization of ripple animation, high code repetition, inflexible configuration and difficult resource management are solved.

The invention provides a simple editing method and system capable of rapidly inputting a tagged text, and the method comprises the steps: monitoring the input of an editable region through a (at) input event, and obtaining a dom node where a cursor is located and a natural language text input by a user; the system detects the shortcut identification symbol, calculates the position of the shortcut instruction panel according to the position of the shortcut identification symbol and displays the position of the shortcut instruction panel; the method comprises the following steps: in response to a natural language text input by a user, monitoring a keyboard event by a system through (at) keydown, selecting a tag instruction in a shortcut instruction panel according to a value of event.key, and converting the tag instruction into a structured tag element; and the system receives the parameters of the tag instruction through a se lectSuggest ion method, and inserts the structured tag element into a specified position of the text stream. According to the method, the operation is rapid, the user-defined instruction can be rapidly inserted, and after the component is introduced, only the label instruction needs to be injected in the form of the object array and can be simply integrated into a webpage or an application interface which needs dialogue input and label functions.

A kind of architecture design method of polar code decoder based on custom instruction set, according to custom instruction control the hardware architecture of decoder, utilize instruction to control decoding process, reduce the error probability caused by circuit state in decoding process, so that the work of polar code decoder is more stable;FSC decoding algorithm is used to classify the nodes of SSC decoding tree into multiple different types of sub-nodes, and according to different sub-nodes, corresponding fast decoding is completed, the problems of large decoding delay, low throughput and not easy to realize hardware circuit are solved, the decoding speed and throughput of the decoder are improved, the decoding efficiency of polar code is improved, so that the work of polar code decoder is more stable.

The application relates to a chip for convolution calculation, comprising a memory, a processor and a convolution calculation module, wherein the memory is used for storing convolution parameter data and convolution calculation results; the processor is connected with the memory and is used for receiving a self-customized instruction of a user, generating a control instruction based on the self-customized instruction based on a RISC-V open source instruction set architecture; the convolution calculation module is connected with the processor and the memory and is used for receiving the control instruction and the convolution parameter data, performing calculation based on the control instruction and the convolution parameter data, and outputting convolution calculation results. The chip for convolution calculation adopts the most simple architecture RISC-V, can discard a large number of redundant instructions, makes the kernel design simple, and reduces power consumption. Meanwhile, the convolution acceleration calculation is realized by the convolution calculation module instead of a software application in the kernel, so that the convolution acceleration calculation speed is greatly improved.

The utility model discloses a verification parameter self-defining device and a vehicle, and relates to the technical field of vehicles, and the verification parameter self-defining device specifically comprises a message self-defining module, a verification self-defining module and a parameter receiving and transmitting module. The parameter transceiving module is electrically connected with the message custom module and the verification custom module respectively, and is used for generating custom setting parameters according to a custom instruction triggered by a user and sending the custom setting parameters to the message custom module and the verification custom module; the message custom module is electrically connected with the verification custom module, and is used for processing the initial collision message according to the custom setting parameters to obtain a custom collision message, and sending the custom collision message to the verification custom module; and the verification custom module is used for generating custom verification parameters according to the custom setting parameters, and injecting the custom verification parameters into the custom collision message to obtain a target collision message. According to the invention, the technical effect of enabling the collision message to carry the verification parameter is achieved.

A method for implementing extended instructions in a RISC-V processor includes: marking the instructions according to their type and / or the type of registers used; and allocating the instructions to different pipelines for execution based on the markings. The method provided by this invention achieves modular expansion of custom instruction decoding and execution units during instruction parsing, facilitating instruction expansion and optimization; it separates and tracks instructions based on register type, making the processing of various instructions relatively independent, convenient, and fast; simultaneously, it reduces the pipeline occupancy impact of instructions with long execution times, thereby improving instruction execution efficiency.

Techniques related to a hybrid approach for measuring statistical drift and data quality on large datasets are provided. In one technique, a data monitoring definition is accessed that includes predefined configuration data and a custom configuration data that is specified by a user, wherein the custom configuration data includes custom instructions pertaining to one or more of data reading, metrics generation, or data writing. Based on the data monitoring definition, executable code is generated that comprises a data reading portion, a metrics generation portion, and a data writing portion. Executing the executable code comprises: based on the data reading portion, reading a dataset based on location data specified in the monitoring definition; based on the metrics generation portion, generating a set of metrics based on the dataset; and based on the data writing portion, writing a result that is based on the set of metrics.

A lattice-based cryptography engine includes an interface configured to receive a lattice-based cryptographic operation request including corresponding operands. A register map is configured to store the operands and response to the request. A controller is coupled to receive the operands and output a sequence of instructions responsive to the request. A plurality of hardware units is coupled to receive and execute the instructions to generate the response. Each instruction is designated for one of the plurality of hardware units. A memory is coupled to the hardware units.

The application discloses an NVMe controller, a user API interface provides a custom interface for operating the NVMe controller, and after being called, a custom instruction encapsulated in the custom interface is stored in a user command queue; queue processing logic checks and maintains the command state of each slot of the user command queue in real time, and according to the command type, is transferred into NVMe command processing logic or custom command processing logic for standardized processing; the NVMe command processing logic controls DMA transmission logic, write data buffer control, read data buffer control, write data PRP cache, read data PRP cache, NVMe command sending queue, NVMe command completion queue, PCIe sending engine and PCIe receiving engine according to the specific requirements of NVMe standard commands to complete initialization, data reading and data writing. The application reduces the interaction frequency between a user program and the NVMe controller, and maximizes the performance of the NVMe protocol.

This invention relates to a hardware acceleration method for the SM3 hash algorithm based on a custom RISC-V instruction set, comprising the following steps: Step A: Extending a custom instruction set into the RISC-V instruction set architecture. The custom instruction set includes a first type of instruction and a second type of instruction. The first type of instruction is used to trigger iterative calculation of the message expansion process in the SM3 algorithm, and the second type of instruction is used to trigger iterative calculation of the compression function process in the SM3 algorithm; Step B: Constructing a hardware acceleration unit decoupled from the processor pipeline. The hardware acceleration unit includes a message expansion pipeline module, a compression function pipeline module, a state control module, and a data concatenation unit; Step C: In response to the processor decoding unit recognizing the first type of instruction, loading the message data in the source operand register into the message expansion pipeline module. The message expansion pipeline module divides the message data into multiple message words according to the message expansion rules of the SM3 algorithm. This invention enables better hardware acceleration.