95 results about "Custom instruction" patented technology

The invention discloses an automatic compiling and adapting method for an RISC-V extension instruction, and belongs to the technical field of compilers. According to the method, a dynamic DSL (Digital Subscriber Line) for registering a custom instruction, adding register use constraints and defining a specific code mode is designed. The LLVM plug-in is used for automatically integrating the registered custom instruction in the compiling process. The invention relates to a self-defined instruction rapid adaptation mechanism which is specially provided for a continuously provided RISC-V self-defined instruction expansion scene, and by automatically generating correct assembly codes of registered self-defined instructions, correct registers are automatically distributed and reserved according to register use constraints; the method comprises the following steps of: searching a defined specific code mode and semantics, and automatically generating and inserting a registered custom instruction in a program, so as to realize the rapid adaptation of a compiler to an RISC-V custom extension instruction and the automatic use of a program code to the custom instruction, and the whole process does not need a developer to manually modify the compiler or a program source code.

The disclosure is directed to various ways of improving the functioning of computer systems, information networks, data stores, search engine systems and methods, and other advantages. Among other things, provided herein are methods, systems, components, processes, modules, blocks, circuits, sub-systems, articles, and other elements (collectively referred to in some cases as the “platform” or the “system”) that collectively enable, in one or more datastores and systems. A system and method (e.g., a custom workflow actions system and related processes) for creating and using a custom action (e.g., custom code action). The custom code action may be created and added to a workflow. The workflow may be executed based on the occurrence of one or more events such that the new custom code action may be triggered as part of the workflow (e.g., resulting in an occurrence of a customized action corresponding with a custom instruction code).

The invention discloses a multi-modal-based multi-language custom instruction identification method and system, and the method comprises the steps: S1, constructing a multi-modal large model, and training the model, the multi-modal large model constructing a support input processing unit, a query input processing unit and a measurement discriminator; s2, on the basis of the step S1, registering a user-defined voice instruction; wherein a support feature vector of a user registration instruction is acquired and stored through the support input processing unit trained in the step S1; s3, user voice is obtained, and reasoning and instruction recognition are conducted through the model generated in the step S2; wherein the trained query input processing unit is used for processing the user voice to output a query vector, and the matching degree of the query vector and a pre-stored support feature vector is calculated, so that a user voice instruction is recognized. According to the method, efficient and extensible multi-language self-defined instruction recognition is realized based on a multi-modal fusion and metric learning framework.

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

The invention discloses a method, a processor and a system for realizing RISC-V architecture to run an X86 instruction set through hardware, and the method comprises the steps: judging whether there is an equivalent RISC-V standard instruction for replacing an X86 instruction, and if there is an equivalent RISC-V standard instruction, determining the X86 instruction and the equivalent RISC-V standard instruction as a first instruction and a second instruction respectively; if the X86 instruction does not exist, whether a non-equivalent RISC-V standard instruction replacing the X86 instruction exists or not is judged, if yes, whether the execution efficiency of the non-equivalent RISC-V standard instruction meets a preset requirement or not is judged, and if yes, it is determined that the X86 instruction and the non-equivalent RISC-V standard instruction are a third instruction and a fourth instruction respectively; if not, an RISC-V custom instruction replacing the X86 instruction is determined, and the X86 instruction and the RISC-V custom instruction are determined to be a fifth instruction and a sixth instruction respectively; and obtaining an instruction processing result which takes the first or third or fifth instruction as input and correspondingly takes the second or fourth or sixth instruction as output, and storing the instruction processing result in a hardware device. According to the method, the X86 instruction set can be quickly and efficiently operated by the RISC-V architecture.

The invention relates to a heterogeneous neural network acceleration device based on cooperation of a DSP (Digital Signal Processor) and a memristor, which adopts a hybrid computing architecture design of a DSP and memristor cross array, such as dynamic precision switching, a real-time closed-loop feedback mechanism based on a Lyapunov stability theory, a self-adaptive cross-domain quantization module, hardware instruction set optimization and the like. The hybrid architecture has good balance performance and universality, stability is remarkably improved through conductivity monitoring, self-adaptive PWM pulse generation and quantization table updating, a higher signal-to-noise ratio is achieved at lower cost through combination of a self-adaptive cross-domain quantization module and noise reduction, hardware level optimization is achieved through customization of an instruction set, the hybrid architecture is more suitable for an HNN calculation task, and the method is suitable for the HNN calculation task. The energy efficiency ratio and the anti-drifting capability of the HNN acceleration circuit are improved, and the acceleration performance is improved.

The invention provides a method for accessing customized protocol equipment to an IoT (Internet of Things) platform based on BLE (Bluetooth Low Energy), which comprises the following steps of: S1, configuring product function definition of the equipment and a corresponding standard instruction format table and a supplier customized instruction format table at a cloud end, and sending the standard instruction format table and the supplier customized instruction format table to a vehicle terminal; s2, Bluetooth connection is established between the device and the vehicle-mounted terminal, and a user clicks a control button at the vehicle-mounted terminal to generate a control page and a standard protocol instruction for the vehicle-mounted terminal application according to the product function definition and the standard instruction format table; through the scheme, the equipment of the supplier custom protocol can access the IoT platform more conveniently, the efficiency of product access to the platform is greatly improved, the willingness of supplier access is also improved, the equipment which can only access a standard protocol instruction in the past is transformed into the equipment which can be adapted to access the supplier custom protocol, and the user experience is improved. The diversity of platform product styles is greatly enriched, and the access quantity of platform equipment is improved.

The invention discloses a compiling method for compiling a C language source code into an RISC-V assembly code. The method comprises the following steps: acquiring a C language source code; performing lexical analysis on the C language source code to generate a mark flow; performing syntactic analysis on the mark flow, and constructing an abstract syntax tree; performing semantic analysis on the abstract syntax tree to generate a target abstract syntax tree; constructing a runtime environment of the RISC-V assembly code; generating an intermediate code and a control flow diagram corresponding to the intermediate code according to a rule in the runtime environment and the target abstract syntax tree; generating a target code by using the intermediate code and the control flow diagram corresponding to the intermediate code; according to the technical scheme, the intermediate representation more adaptive to RISC-V custom instruction mapping can be generated, so that the execution efficiency of assembly codes is improved; and meanwhile, by designing a lightweight runtime environment, the performance overhead is further reduced.

Disclosed herein are methods, systems, and computer-readable media for interacting with a language model using custom instructions. In one embodiment a method includes receiving, through an interface, custom instructions, the custom instructions comprising at least one of personal information or a response type preference, storing the custom instructions temporarily within a session specific cache, in response to a trigger event, adding the custom instructions to a system message associated with the language model, the system message being a prompt modifier to the language model, in response to receiving a prompt, retrieving the custom instructions from the session specific cache, determining whether the custom instructions are relevant to the prompt, and in response to determining the custom instructions are relevant to the prompt, generating a response to the prompt based on the custom instructions.

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

The invention belongs to the technical field of chip testing, and discloses a testing device and method for an RISC-V chip instruction cache, and the device comprises a CPU core, a cache controller, a user-defined instruction execution module, and an instruction cache. The CPU core is used for receiving a test starting address and a test ending address; sending a clearing instruction to the instruction buffer; and executing a test step: generating an instruction reading address according to the test starting address, sending the instruction reading address to the cache controller until a test ending address, receiving a test instruction of the cache controller, judging whether the test instruction is a self-defined instruction, and if so, sending the test instruction to a self-defined instruction execution module to obtain an instruction execution result; and executing the test step again, and obtaining an instruction cache test result according to an obtained instruction execution result. The RISC-V chip instruction buffer test method and the RISC-V chip instruction buffer test device can realize comprehensive test of the RISC-V chip instruction buffer under the condition of avoiding increasing a large amount of chip cost area.

The disclosure is directed to various ways of improving the functioning of computer systems, information networks, data stores, search engine systems and methods, and other advantages. Among other things, provided herein are methods, systems, components, processes, modules, blocks, circuits, sub-systems, articles, and other elements (collectively referred to in some cases as the “platform” or the “system”) that collectively enable, in one or more datastores and systems. A system and method (e.g., a custom workflow actions system and related processes) for creating and using a custom action (e.g., custom code action). The custom code action may be created and added to a workflow. The workflow may be executed based on the occurrence of one or more events such that the new custom code action may be triggered as part of the workflow (e.g., resulting in an occurrence of a customized action corresponding with a custom instruction code).

The invention relates to a message processing module, a data processing method, a processor and a chip, and the method comprises the steps: an instruction decoding module decodes a network acceleration instruction to obtain a first read address and a first operation code, and transmits the first read address and the first operation code to an instruction pipeline processing logic module; the network acceleration instruction refers to a self-defined instruction generated based on an RISC-V standard instruction; the instruction pipeline processing logic module sends the first read address to a Fast RegFile module; the Fast RegFile module outputs data corresponding to the first read address to the Inbuffer; the Fast RegFile module is a data storage unit realized by adopting a register; the Inbuffer outputs a first source operand stored in the Inbuffer to an instruction pipeline processing logic module according to data corresponding to the first read address; the instruction pipeline processing logic module operates the first source operand according to the first operation code; the network acceleration instruction can be efficiently processed, and the performance of the network processor is improved.

Disclosed herein are methods, systems, and computer-readable media for interacting with a language model using custom instructions. In one embodiment a method includes receiving, through an interface, custom instructions, the custom instructions comprising at least one of personal information or a response type preference, storing the custom instructions temporarily within a session specific cache, in response to a trigger event, adding the custom instructions to a system message associated with the language model, the system message being a prompt modifier to the language model, in response to receiving a prompt, retrieving the custom instructions from the session specific cache, determining whether the custom instructions are relevant to the prompt, and in response to determining the custom instructions are relevant to the prompt, generating a response to the prompt based on the custom instructions.

The present invention discloses a method and device for obtaining a custom instruction template. The method includes: obtaining a custom instruction template entry request sent by a target user; based on the custom instruction template entry request, collecting a static period target signal and an instruction entry period target signal; performing quality detection on the static period target signal and the instruction entry period target signal to obtain a signal quality detection result; if the quality detection result meets a preset quality condition, performing feature extraction on the instruction entry period target signal to obtain a signal feature; performing similarity matching between the signal feature and the corresponding signal feature of a pre-stored custom instruction template; if the similarity meets the preset similarity condition, the custom instruction template entry is successful; otherwise, the custom instruction template entry fails and a prompt message is output. The method can effectively screen out low-quality signals due to environmental factors, improve the quality of custom instruction template entry, optimize the personalized interactive experience, and enhance the device response accuracy and execution effect.

A processor includes an instruction decoder configured to provide at least a floating point instruction control signal; performing floating point calculation on a data path; a floating point custom instruction control logic block coupled to the floating point compute data path; a control and status register coupled to the floating point computational data path and the floating point custom instruction control logic block; a first multiplexer configured to provide a floating-point instruction control signal or a custom instruction control signal to the floating-point computational data path based on a state of a selection control signal; and a second multiplexer configured to provide a floating point operand or a custom operand to the floating point computing data path based on a state of the selection control signal. The floating point custom instruction control logic block asserts a select signal while directing the floating point computational data path to assist it in executing custom instructions. The custom instruction may be a floating point exponential function.

1. Name of the Design Product: Instruction Addition Area of the Graphical User Interface for Information Search of Electronic Devices. 2. Use of the Design Product: An electronic device. 3. Design Key Points of the Design Product: The part of the graphical user interface in the electronic device that is claimed. 4. Picture or Photograph Most Indicating the Design Key Points: State Change Diagram 3 of Design 1. 5. Design 1 is designated as the basic design. 6. Use of the Graphical User Interface: The graphical user interface is used for information search, and the claimed part of the graphical user interface is used for adding custom instructions. In response to the user touching or clicking on the input box in the main view of Design 1, the graphical user interface changes from the main view of Design 1 to State Change Diagram 1 of Design 1 to display the list of historical search instructions; in response to the user hovering the cursor over a certain historical search instruction, the graphical user interface changes from State Change Diagram 1 of Design 1 to State Change Diagram 2 of Design 1 to display the operation buttons for that historical search instruction; in response to the user touching or clicking on the "Existing Instruction" button, the graphical user interface changes from State Change Diagram 2 of Design 1 to State Change Diagram 3 of Design 1 to display the custom instruction addition pop-up window; in response to the user touching or clicking on the "Save" button, the graphical user interface changes from State Change Diagram 3 of Design 1 to State Change Diagram 4 of Design 1 to display the added custom instructions; in response to the user touching or clicking on the custom instruction, the graphical user interface changes from State Change Diagram 4 of Design 1 to State Change Diagram 5 of Design 1 to input the custom instruction into the information search box. In response to the user touching or clicking on the input box in the main view of Design 2, the graphical user interface changes from the main view of Design 2 to State Change Diagram 1 of Design 2 to display the list of historical search instructions and the operation buttons for the historical search instructions; in response to the user touching or clicking on the "Existing Instruction" button, the graphical user interface changes from State Change Diagram 1 of Design 2 to State Change Diagram 2 of Design 2 to display the custom instruction addition pop-up window; in response to the user touching or clicking on the "Save" button, the graphical user interface changes from State Change Diagram 2 of Design 2 to State Change Diagram 3 of Design 2 to display the added custom instructions; in response to the user touching or clicking on the custom instruction, the graphical user interface changes from State Change Diagram 3 of Design 2 to State Change Diagram 4 of Design 2 to input the custom instruction into the information search box. In response to the user touching or clicking on the input box in the main view of Design 3, the graphical user interface changes from the main view of Design 3 to the change state diagram 1 of Design 3 to display the list of historical search instructions; in response to the user hovering the cursor over a certain historical search instruction, the graphical user interface changes from the change state diagram 1 of Design 3 to the change state diagram 2 of Design 3 to display the operation buttons for that historical search instruction; in response to the user touching or clicking on the "Existing Instruction" button, the graphical user interface changes from the change state diagram 2 of Design 3 to the change state diagram 3 of Design 3 to display the custom instruction addition pop-up window; in response to the user touching or clicking on the "Save" button, the graphical user interface changes from the change state diagram 3 of Design 3 to the change state diagram 4 of Design 3 to display the added custom instructions. In response to the user touching or clicking on the input box in the main view of Design 4, the graphical user interface changes from the main view of Design 4 to the change state diagram 1 of Design 4 to display the list of historical search instructions; in response to the user hovering the cursor over a certain historical search instruction, the graphical user interface changes from the change state diagram 1 of Design 4 to the change state diagram 2 of Design 4 to display the operation buttons for that historical search instruction; in response to the user touching or clicking on the "Existing Instruction" button, the graphical user interface changes from the change state diagram 2 of Design 4 to the change state diagram 3 of Design 4 to display the custom instruction addition pop-up window. In response to the user touching or clicking on the input box in the main view of Design 5, the graphical user interface changes from the main view of Design 5 to the change state diagram 1 of Design 5 to display the list of historical search instructions and the operation buttons for the historical search instructions; in response to the user touching or clicking on the "Existing Instruction" button, the graphical user interface changes from the change state diagram 1 of Design 5 to the change state diagram 2 of Design 5 to display the custom instruction addition pop-up window. 7. Other situations that need to be explained Other explanations: The parts of the graphical user interface shown by the dashed lines in each view of Design 1-Design 5 do not constitute the parts protected by this design patent.

This application relates to a pulse modulation control system, device, and method. The system includes a processor based on a RISC-V open-source instruction set architecture and a pulse modulation interface module. The processor is configured to receive an operation instruction of a user, and generate a data signal based on the operation instruction. The pulse modulation interface module is connected to the processor, and is configured to receive the data signal and output a preset waveform based on the data signal. Based on the RISC-V open-source instruction set architecture, the user may customize operations, which improves efficiency and flexibility of a pulse modulation process, and optimizes power consumption.

The present invention relates to a system and method for queuing in custom instruction extension of a hardened processor (203) such as a RISC-V processor implemented on a System-on-Chip (SoC) fabric; which enables high performance for said RISC-V processor (203) when interacting with any custom accelerator (205) via custom instruction extension (207) due to the reduced latency in waiting for a response from said custom accelerator (205). The system and method of the present invention also facilities clock domain crossing between the high frequency hardened processor (203) and the lower frequency custom accelerator (205), thus simplifying the design requirements for the custom accelerator (205) to close the timing gap. Besides that, the system and method of the present invention also supports blocking and non-blocking implementations of the queueing capability without needing for updates to the register transfer level (RTL) design.

The invention discloses a target vehicle control method and device, a medium and electronic equipment, and the method comprises the steps: receiving a voice control instruction of a target user; a target operation library of the target user is obtained, the target operation library comprises a user-defined operation library and a preset operation library, the user-defined operation library comprises at least one set of user-defined instructions and user-defined operations with the corresponding relation, and the preset operation library comprises at least one set of preset instructions and preset operations with the corresponding relation; determining a first instruction matched with the voice control instruction and a first operation corresponding to the first instruction from a user-defined operation library; controlling the target vehicle to execute the first operation; if the first instruction does not exist in the user-defined operation library, determining a second instruction matched with the voice control instruction and a second operation corresponding to the second instruction from a preset operation library; and controlling the target vehicle to execute the second operation. Through the technical scheme provided by the invention, the control efficiency of the target vehicle can be improved.

The present invention discloses a system for cross-thread reading and writing of inter-thread operands, and relates to the technical field of cross-thread data sharing of GPGPU. Aiming at the problems of read and write delay and cache occupancy caused by synchronous operation in data sharing scenario of GPGPU, a scheme is adopted, including a decoding unit, a transmitting unit and a writing back unit, and these three units cooperate with each other to form a complete cross-thread data reading and writing path, wherein: the decoding unit is responsible for decoding custom instructions and remapping thread indexes; the transmitting unit undertakes the tasks of instruction caching, data synchronization control and cross-thread data reading; the writing back unit is responsible for writing the instruction execution results back to the storage space and updating the status of related registers. The present invention can improve the parallel performance of GPGPU in multi-threaded parallel computing scenarios.

This application relates to a method and an apparatus for determining a cooker hood operating strategy, a device, a storage medium, and a program product. The method includes: controlling a cooker hood to enter a user-oriented engineering mode, and in the engineering mode, receiving a customization instruction issued by a user is received through a human-computer interaction interface, to determine a primary evaluation indicator and a secondary evaluation indicator of a cooker hood operating parameter customized by the user; and adjusting the cooker hood operating parameter according to the primary evaluation indicator and the secondary evaluation indicator, to obtain a target operating parameter satisfying a user customization condition, and configuring a target operating level according to the target operating parameter. In this application, in the user-oriented engineering mode, an evaluation indicator during operation of a cooker hood is determined according to the customization instruction of the user, and operation of the cooker hood is controlled according to the evaluation indicator customized by the user. For users with different requirements, in the control method of this application, a cooker hood operating state that balances performance and user satisfaction can be achieved, to reduce operating noise of the cooker hood, thereby improving user experience.

The present invention relates to the technical field of computer algorithms, and particularly to a coprocessor for the replacement process in a data fusion algorithm based on an auction algorithm. The coprocessor includes a coprocessor, and the internal circuit of the coprocessor contains a control logic and a computing unit. The control logic unit is used to control the data flow control of the entire computing unit and the data reading and writing with the storage cache. The computing unit is responsible for calculating a pair of data transmitted from a custom instruction, comparing whether the values read from two storage caches are the same, and sending the comparison result to the control logic. For an algorithm with repeated and regular operation steps, implementing it using a finite state machine saves a large amount of time compared to implementing it using a processor. At the same time, through reasonable design, the two data retrievals and comparisons of each group of numbers are synchronized, and optimization is carried out at the algorithm level, doubling the efficiency. By utilizing the characteristics of a dual-port cache, a direct interaction method between the peripheral device and the coprocessor is achieved, rather than accessing the on-chip storage through an ROCC interface.

The invention relates to a processing method, device and system, and the method comprises the steps: providing a target processor and a user-defined instruction execution module, analyzing the instruction type of a to-be-executed instruction by the target processor for the received to-be-executed instruction, and when the to-be-executed instruction is a user-defined instruction adaptive to the user-defined instruction execution module, executing the user-defined instruction by the target processor; the target processor sends the current instruction to be executed and the corresponding source register data to the self-defined execution module; the user-defined execution module decodes the received instruction to be executed so as to determine the execution type of the instruction to be executed after decoding, and the user-defined instruction execution module performs instruction operation processing matched with the instruction to be executed on the source register data based on the instruction type of the instruction to be executed so as to execute the instruction to be executed. And generating an instruction operation result after the instruction operation processing, and sending the instruction operation result to the target processor. According to the method, the extension of the custom instruction can be flexibly realized, and the instruction execution efficiency of the CPU is improved.

The invention provides a test script generation method, electronic equipment, a readable storage medium and a computer program product. The test script generation method comprises the steps that a request message about an interface is analyzed into a plurality of first type parameters and a plurality of second type parameters, the interface is used for defining an interaction rule between a requesting party and a requested party, the first type parameters represent the interaction rule, and the second type parameters represent attribute information of the requesting party; the parameter value of the second type parameter indicated by the customization instruction is replaced with a customization interval in the customization instruction, a customization parameter is obtained, the customization instruction comprises a parameter identifier with a customization requirement and the customization interval, and the customization interval represents a parameter value change range which can be supported by the interface and is related to the corresponding second type parameter; and according to the customization interval of the customization parameters, configuring the plurality of first type parameters, the second type parameters and the customization parameters to a script template, and generating a test script meeting the customization instruction.

The invention relates to the technical field of research and development frameworks, and provides an exposure point burying method and device, computer equipment and a readable storage medium, and the method comprises the steps: generating a user-defined instruction according to preset exposure point burying logic; binding the custom instruction to the target DOM element, and dynamically binding the burying point data through the attribute of the target DOM element; constructing a viewport detection module based on a native intersection observer application program interface of the browser, and monitoring the intersection state of the target DOM element and a viewport in real time; when the target DOM element enters a viewport and meets a preset exposure condition, executing burying point reporting through a delay trigger mechanism, and recording reported burying point data through a cache list to realize duplicate removal processing; the preset exposure condition comprises a residence time threshold value of the element in the viewport. According to the method, the problem of pain points of a traditional point burying technology in the vertical field is effectively solved through technical innovation, and an efficient and reliable exposure point burying solution is provided for the industries of finance, medical health, old-age care and the like.

The present invention claims protection for an audio noise reduction accelerator system and method based on the expansion of RISC v custom instruction set, which belongs to the field of integrated circuit technology, and mainly includes: E203_CORE, NICE_CORE, NICE_Interface, E203_SOC, audio codec WM8731 module, and audio noise reduction FxLMS algorithm. Among them, E203_CORE is connected to NICE_CORE through NICE_Interface, E203_CORE, NICE_CORE and related peripheral ports together form E203_SOC, E203_SOC is connected to the audio codec WM8731 module, and the audio noise reduction FxLMS algorithm is downloaded to the RISC v processor core through software programming for operation. The innovation point is that compared with the processor of ARM instruction set architecture, the processor using RISC v custom instruction set can accelerate the specific operation part of the audio noise reduction FxLMS algorithm; the present invention can further optimize the problems of area, power consumption, granularity, etc., while improving the flexibility and feasibility of the algorithm.

The invention relates to a network processor and a chip, and the method comprises the steps: an instruction assembly line receives and analyzes a customer-defined instruction, reads a source data list and a command list from a storage module according to instruction analysis information, and transmits the source data list and the command list to a finite-state machine; in the finite-state machine, a data buffer stores source data and a command execution result, a command buffer stores a command list, a state controller reads a target command from the command list in sequence, obtains target source data from the data buffer according to the target command, then generates a task request and sends the task request to an execution unit, and the execution unit executes the task request. A command result returned by the execution unit is received and written into the data buffer, and finally, after the command list is executed, a write-back data write-back storage module is generated according to data in the data buffer. According to the method and the device, a customer can customize the custom instruction according to own requirements in the chip use process, and the utilization rate of the execution unit in the instruction assembly line is improved.

Provided is a method for performing computations near memory. The method includes receiving, at a storage device, first data associated with a first data set, the first data having a first format. The method further includes receiving, at a processor core of the storage device, a request to perform a function on the first data, the function including a first operation and a second operation. The method further includes performing, by a first processor-core acceleration engine of the storage device, the first operation on the first data, based on first processor-core custom instructions, to generate first result data. The method further includes performing, by a first extra-processor-core circuit of the storage device, the second operation on the first result data, based on the first processor-core custom instructions.

The present application provides an interactive method, device and storage medium based on custom instructions, which are applied to a client and relate to the technical field of human-computer interaction. The method requests to load an attribute value editing interface through trigger information of a custom instruction of a client. When the attribute value editing interface is successfully loaded, an interface function of the listening editing end is registered on the client. The interface function is equivalent to the communication interface between the two ends. When the editing end is monitored to be called, parameter information transmitted by the interface function from the editing end is obtained, and corresponding interactive logic is executed according to the parameter information, so that intuitive attribute value setting can be realized from the attribute value editing interface displayed on the editing end into the client, thereby improving fault tolerance and development efficiency.