ARINC 659 protocol based instruction decoding circuit implementation method

A technology of instruction decoding and implementation method, which is applied in the direction of machine execution devices, etc., and can solve problems such as no similar technology

Active Publication Date: 2014-02-12
西安翔腾微电子科技有限公司
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  • Abstract
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  • Claims
  • Application Information

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  • ARINC 659 protocol based instruction decoding circuit implementation method
  • ARINC 659 protocol based instruction decoding circuit implementation method
  • ARINC 659 protocol based instruction decoding circuit implementation method

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Embodiment Construction

[0022] The present invention provides a kind of realization method based on the instruction decoding circuit of ARINC659 agreement, and this method comprises the following steps:

[0023] 1) Define machine codes for different system parameters stipulated in the ARINC659 protocol, and each system parameter occupies several 32 bits. Taking the parameter GAP as an example, the machine code format is:

[0024]

[0025] 2) The general static memory SRAM with a data bit width of 32 bits is used to store the machine codes of all instructions;

[0026] 3) Define one-to-one corresponding instruction codes for the instructions stipulated in the ARINC659 protocol, define the machine code format of each instruction, and each instruction occupies a number of 32 bits (a maximum of 4 32 bits are required).

[0027] Take the FREE command as an example, the command code is 4’b0000, and the machine code format is:

[0028]

[0029] 4) Divide the SRAM address space into 16 parts, which c...

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Abstract

The invention relates to an ARINC 659 protocol based instruction decoding circuit implementation method. The method comprises 1) defining machine codes to different system parameters specified in the ARINC 659 protocol and storing the machine codes corresponding to the different system parameters in a register corresponding to the machine codes in bit wide; 2) encoding the instructions corresponding to instruction definitions specified in the ARINC 659 protocol; 3) storing the machine codes of all instructions by using a general static random access memory (SRAM); 4) decoding all instruction machine codes through a state machine; 5) storing all the decoded instruction machine codes in a general synchronous FIFO, the data bit wide of which is 256 bits. According to the method, the problem of analysis of frame description language instructions by BIU on an ARINC 659 bus is effectively solved, and the method can be promoted to complete works like bus custom instruction set machine code definition, instruction decoding.

Description

technical field [0001] The invention belongs to the technical field of computer control, relates to a circuit realization method, in particular to a realization method of an instruction decoding circuit based on the ARINC659 protocol. Background technique [0002] The ARINC659 backplane data bus is a serial fault-tolerant bus standard that meets high reliability requirements. The ARINC659 protocol specifies the frame description language, which defines the timing of communication data between online replaceable modules on the bus. As a BIU developer, it is necessary to define the machine code format of the frame description language, and analyze the machine code to complete the communication with other BIUs on the bus. There is currently no such technology. Contents of the invention [0003] In order to solve the above-mentioned technical problems existing in the background technology, the present invention provides a method that effectively solves the problem of parsing...

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Application Information

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IPC IPC(8): G06F9/30
Inventor 田泽刘宁宁郭亮许宏杰杨峰马宁张玲
Owner 西安翔腾微电子科技有限公司
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