96 results about "256-bit" patented technology

The invention relates to an image encryption method and an image decryption method with visual security and data security based on compressed sensing. The image encryption method comprises the steps of: firstly, utilizing an SHA 256 hash function to obtain a 256-bit hash value of a plaintext image as an image secret key, and calculating initial numerical values of one-dimensional skew tent chaotic mapping and zigzag scrambling; carrying out sparse processing on the plaintext image, and carrying out zigzag scrambling on a coefficient matrix; and then utilizing the one-dimensional skew tent chaotic mapping to generate a measurement matrix, measuring and quantifying a scrambling matrix to obtain a compressed and encrypted image, and embedding the image into a carrier image with visual significance to obtain a final ciphertext image with visual significance. The image encryption method realizes the visual security and data security of the plaintext image, has large secret key space, is highly sensitive to plaintext, has higher capacity of resisting brute-force attack, chosen-plaintext attack and known-plaintext attack, does not need an additional storage space, and can transmit and store the ciphertext image quickly and effectively.

The invention relates to a high speed arithmetic device and a method of elliptic curve codes. The invention mainly aims to a master curve, the elliptic curve of which is 160-256 bit of die length and the prime field of which is on Fp. The high speed arithmetic device is a special hardware structure based on a water running pulsate double modular multiplier; the hardware structure comprises an operation part, a control part and a storage part, wherein the operation part comprises two parallel water running pulsate modular multipliers and two groups of adders. Based on the specific hardware structure, point addition and point double water running operation sequences of modified Jacobi coordinate projective joints are rearranged, and point addition and point double operations which sequentially appear in succession are connected end to end; and the vacant times of the double modular multipliers are mutually complemented, thus increasing the hardware efficiency of the water running pulsate modular multipliers and causing the point addition operation to only occupy seven modular multiplication operation cycles and the point double operation to occupy four modular multiplication operation cycles, and drastically reducing clock periodic numbers of the point addition and/or point double and point multiplication operation.

An improvement to split-architecture audio codecs such as those defined by the Audio Codec '97 specification (AC '97) includes an interrupt mechanism which allows an event at an analog peripheral device such as an incoming call to be sensed by the AC analog sub-system and initiate a wake up procedure in the split-architecture audio codec system. The interrupt mechanism includes a masked interrupt register which is responsive to an interrupt signal from an audio source, such as a ring detect from an incoming telephone line. Either the AC controller sub-system or the peripheral analog device via the AC analog sub-system can initiate a wake up procedure. The AC controller sub-system includes a static divide by 256 counter responsive to a bit clock signal. The bit clock signal is sensed at the AC controller sub-system to determine an operating mode. Upon detection of at least 256 bit clock cycles after a predetermined minimum time for the AC analog sub-system to be in a halted or sleep mode, a wake up interrupt register is enabled in the AC controller sub-system. The interrupt sensor is opto-coupled to the AC analog sub-system, and the interrupt signal from the interrupt sensor is communicated to the AC controller sub-system via the five-wire TDM serial bus between the AC analog sub-system and the AC controller sub-system.

A method for implementing one-to-one binary functions defined on the Galois field GF(2⁸) is very useful for forming fast and low power hardware devices regardless of the binary function. The method includes decoding an input byte for generating at least one bit string that contains only one active bit, and logically combining the bits of the bit string according to the binary function for generating a 256-bit string representing a corresponding output byte. The 256-bit string is then encoded in a byte for obtaining the output byte.

A method for realizing coprocessor of oval curve cipher system includes dividing functions of complete coprocessor first and then detailing divided functions to be each bottom layer module in design, realizing each bottom layer module first and testing then separately then integrating them to be complete ECC coprocessor in realization. The 256 position universal coprocessor for solving point multiplication problem in ECC calculation is also disclosed.

The invention discloses a device compatible with three SHA standards, which comprises a data filling module, a Wt generation module and an Hash operation module, which are connected in order. The invention also discloses a realization method of the device compatible with three SHA standards, which comprises the following steps: (I) receiving cleartext data by the data filling module to generate filling data and outputting the data to the Wt generation module; (II) generating new Wt operators by the Wt generation module and inputting the new Wt operators into the Hash operation module; and (III) generating a data abstract with 160 bits under an SHA-a mode, generating a data abstract with 256 bits under SHA-256 mode or generating a data abstract with 512 bits under an SHA-512 mode by the Hash operation module. The invention has the advantages of common practicality, good compatibility, low power consumption, less occupation of extra resources and the like.

The invention discloses an RSA key pair fast generation system and an RSA key pair fast generation method. The system comprises a CPU core, a cipher coprocessor, a prime number generator, and a memory. The prime number generator is used for filtering composite numbers, is implemented in hardware form, supports 256-bit, 512-bit, 1024-bit, 2048-bit and 4096-bit composite number filtering, and completes modular redundancy, calculation and identification table setting. According to the RSA key pair fast generation method, in order to realize fast key pair retrieving, filtering and judging in an asymmetric algorithm, a hardware-based composite number filtering scheme is adopted, optimized modular exponentiation and improved Montgomery modular multiplication are employed, and the existing prime number decision algorithm is optimized. Thus, efficient prime number screening is realized, the key pair generation speed is increased, and the problem that the generation of an RSA key pair takes long in the existing encryption and decryption technology is solved.

The invention discloses a light-weight dual-mode-compatible AES encryption and decryption module and a method thereof. The encryption and decryption module comprises a data and control signal reading module, a determination selection module, and an AES calculation module. The data and control signal reading module is used for reading a corresponding control signal and reading to-be-encrypted data and an encryption secret key after being triggered by a data reading-in control signal; the determination selection module is used for determining an encryption and decryption control signal and a mode selection control signal to select whether a current operation is an encryption operation or decryption operation and whether a current operation is a 256-bit secret key encryption and decryption operation or a 128-bit secret key encryption and decryption operation; and the AES calculation module is used for carrying out encryption and decryption on the to-be-encrypted/decrypted data by using round calculation based on selection by the determination selection module. According to the invention, under control of the control signal, the encryption and decryption operations with the 128-bit-length and 256-bit-length secret keys can be realized; and the partial structure multiplexing is realized. Therefore, the realization result of a ten-thousand equivalent gate level and the throughput capacity with the tens-of Mbps level can be realized.

A digital image watermarking method based on visual perception characteristics provided by the invention relates to the technical field of information hiding and digital watermarking in multimedia information security, and mainly comprises the following five steps: preprocessing a digital image watermark; extracting an important region; creating a visual perceptual model; embedding the digital image watermark; and detecting the digital image watermark. A specific flow comprises the following steps: firstly, mapping a carrier image into a geometrical invariant space by using an image normalization method based on moment, and determining the important region in the normalized image by combining an invariant centroid theory; and then, establishing the visual perceptual model according to the visual perception characteristics; and finally, combining the visual perceptual model, and using a special adaptive quantization modulation policy to adaptively embed a 256-bit readable watermark in a DFT (discrete Fourier transformation) area of the important region. An original carrier is unnecessary for extracting out the watermark, so that blind detection is realized well. The method is not only good in transparency, but also has better robustness.

The invention discloses a data check method and device and electronic equipment. The method includes the steps that 256-bit data are obtained; 13-bit first checksum data related to the obtained data and generated according to a first checksum algorithm are obtained; the obtained data are subjected to checksum calculation according to the first checksum algorithm, and 13-bit second checksum data are generated; the first checksum data and the second checksum data are compared, and a comparison result is obtained; the correctness of the obtained 256-bit data is determined according to the comparison result.

The invention is a process and apparatus for securing and retrieving digital data with a Portable Data Storage Device (PDSD) and Playback Device (PD). The PDSD-PD employs software and hardware security and encryption as barriers to those desiring illicit access to the stored data. Data is prepared with a Digital Rights Management (DRM) application which assigns a license object to the data and encrypts it using a Private Key managed Advanced Encryption Standard (AES) algorithm with 256-bit complexity. Private Keys are stored inside secured Field PGAs, PDSD, or PD. Another layer of AES encryption with 256-bit complexity is applied to the DRM license object using Public Key Infrastructure. Initial docking between a PDSD and PD initiates a sequence of routines and authentication. Interruption of the key exchange, authentication, or physical security measures may result in a lockout and/or the deletion of PDSD data. Potential applicable physical security measures are described.

The invention relates to a stream cipher based secure communication protocol. The communication is one-time pad, keys are owned by both parties and are synchronous, the generation speed is fast, the fault-tolerant capacity is achieved, a 128-bit original text is processed every time, digital signature and data encryption are performed on the original text, and subsequently, 256-bit processed data are sent; firstly, original text grouping and hashed value calculation are performed, secondly, the data are encrypted, and finally, data decryption is achieved. According to the stream cipher based secure communication protocol, a method is designed on the basis of a stream cipher system, a grouping encryption processing structure is used for reference, the 256-bit data can be processed every time, high encryption and decryption efficiency is achieved, a random number generator is used for generating the keys which are owned by both communication parties and are synchronous, and the occupation space of the keys is small.

The invention discloses a password remote lock control system based on the AES cryptographic algorithm, which comprises a key unit and a lock unit. The key unit is composed of a timer A, a keyboard and a receiver A, a decoder A, a processor A, a random number generator A, an encipher A and a transmitter A connected in sequence; the lock unit is composed of a timer B and a transmitter B, an encipher B, a random number generator B, a processor B, a decoder B and a receiver B connected in sequence. By adopting the 256-bit key AES cryptographic algorithm, the password remote lock control system encrypts the time-variant random numbers and carries out the bidirectional communication transmission between the key and the lock, thereby avoiding being decoded by the prior various decoding manners, maximizing security, reliability and compatibility of the password remote lock and protecting a user's property.

The invention discloses an AES (Advanced Encryption Standard) key extension method, and belongs to the technical field of information security. Regarding a condition in which lengths of AES keys are 128 bits and 192 bits, a specific key interception rule is given; and by using the key interception rule, a key with a corresponding length can be intercepted from an output abstract of a sha256 hash function. Regarding an AES encryption algorithm for 128-bit, 192-bit and 256-bit keys, even though an attacker knows a corresponding interception rule, the attacker first needs to obtain an abstract generated by a key via a sha256 hash abstract function; and according to characteristics of the sha256, unless otherwise an output abstract is guessed by traversing, abstract information cannot be obtained by collision; and moreover, the complexity of the output abstract guessed by traversing is as shown in the specification and is obviously higher than the complexity of a 128-bit key and a 192-bitkey. By using the irreversibility of the sha256 hash abstract function, the unidirectionality of the AES key extension method is guaranteed; with the non-collision capability of the sha256, the difficulty of cracking a key violently is improved; and thus, the security of AES key extension is improved.

The invention relates to a digital in-memory computing array device, which comprises 256 row * 64 column in-memory computing modules, each in-memory computing module comprises a bit cell, a tube T7, a tube 8 and an XNOR gate, and the tube T7 and the tube 8 form a transmission gate; the weight storage point Q of the bit cell is connected with the input end of the transmission gate, the output end of the transmission gate is connected with the first input end of the XNOR gate, the second input end of the XNOR gate is connected with an input signal, the output of the XNOR gate serves as the output of the bit cell, the grid electrode of the tube T7 is connected with a control signal RE, and the grid electrode of the tube T8 is connected with a control signal REN; an input signal input by each bit unit and the weight storage point Q are subjected to XNOR operation through an XNOR gate; and a column of bit cells is calculated each time, and thus accumulating 1bit outputs of 256 bit cells and then outputting a 9bit multiply-accumulate result. According to the invention, the calculation precision is improved.

The invention discloses a handset NFC safety payment method based on integrated voiceprint and face characteristic encryption. The method is characterized by comprising steps that, image acquisition and voice acquisition are carried out; the acquired image and the acquired voice are respectively processed; integrated processing on a face characteristic vector and a voice characteristic vector is carried out to acquire a characteristic vector P; the characteristic vector P is compressed to be in 256-bit bytes, and a characteristic vector T is acquired; the characteristic vector T is taken as a secret key and is stored in a handset as an initiation end, and the characteristic vector T is transmitted by utilizing a Diffie-Hellman key exchange algorithm to a target end; the characteristic vector T is taken as a symmetric secret key by two communication parties to carry out encryption communication. The method is carried out in an NFC point-to-point mode, and through the method, information safety interaction during handset NFC payment can be realized.

The invention discloses a method for establishing a channel in a TLS1_3 protocol based on a national cryptographic algorithm. The method comprises a key exchange stage, a server parameter stage and anidentity authentication stage. In the key exchange phase, an SM2 key exchange algorithm is introduced to negotiate a shared key, and compared with international algorithms such as ECDH and ECDSA, a safer mechanism is adopted; in the identity authentication stage, compared with an RSA algorithm, the SM2 algorithm has the advantages that the encryption strength is similar to the safety performanceof a 3072-bit RSA algorithm when the key length of the SM2 algorithm is 256 bits, two message words are used in each round of a compression function of the SM3 algorithm, and the SM3 algorithm has higher word completeness than an existing SHA256 algorithm. In a symmetric encryption algorithm, an SM4 algorithm is introduced, a 32-round nonlinear iterative structure is adopted, the number of roundsof calculation is far larger than that of an AES algorithm, and safety is higher. According to the method, by improving the encryption algorithm serving as a data transmission safety core, secret keyleakage in the transmission process is avoided, and the safety of establishing a TLS1_3 channel is improved to a great extent.

The invention provides a method for realizing high performance of a radix-2 one-dimensional FFT (Fast Fourier Transform) based on a domestic SW 26010 processor. Based on the domestic processor SW26010 platform, various optimization technologies such as a row or column register communication mechanism in an auxiliary core, an access memory-calculation overlapping double-buffer mechanism and a vector operation of a 256-bit single-instruction stream multiple-data stream are designed, meanwhile a two-layer decomposition-based Stockham FFT calculation framework is provided and a decomposition rule is a Cooley-Turkey algorithm, a four-layer structure framework of an interface layer, a main core layer, an auxiliary core layer and a kernel layer is designed for calculation of the radix-2 one-dimensional FFT, and thus the problem of limitation of an access memory bandwidth for the FFT calculation is effectively solved and the calculation performance of the radix-2 one-dimensional FFT is effectively improved. Compared with an open source FFTW (Fastest Fourier Transform in the West) library, the calculation performance of the radix-2 one-dimensional FFT based on the platform is rapidly improved; and a floating-point operation per second of the FFT calculation is taken as an example, an average speed-up ratio of the FFT calculation is 34.4 and a maximum speed-up ratio reaches 50.3.

The invention discloses a block chain recording method based on hierarchical heterogeneous dynamic topology slicing, the method constructs a hierarchical heterogeneous dynamic topological slice for each block chain data record by using a simulated plant growth algorithm (PGSA) in a local network, the constructed two-layer heterogeneous dynamic topology consists of two parts, the common link and the main net, and the common link bears no more than 49% of the total number of nodes, and the main net bears no less than 51% of the total number of nodes. The nodes of the main network slice are usedto store data in a distributed manner, and the nodes of the common network slice are used to record the 256-bit Hash value after a specific encryption method (such as MD5, SHA 256, SHA 512, etc.). A layered heterogeneous dynamic topology slicing algorithm is combined with block chain recording to effectively solve that problem of 'ternary paradox' commonly faced by block chain data recording on the premise that the block chain technology is guarantee to be used for realizing the existing distributed recording technology.

The invention provides an encrypted storage method of bank card information and an encrypted storage system thereof. The system comprises: a terminal, which is used for initiating an encryption request and storing encrypted bank card information; a card reader, which is connected with the terminal and is used for reading magnetic track information of the bank card; a hardware encryption device, which is used for carrying out coding on the bank card information; and a third party service platform, which is used for reading the device number of the terminal, submitting the bank card information that applies for encryption to the hardware encryption device and carrying out association on the encrypted bank card information and the terminal device number and returning the information to the terminal. Therefore, according to the invention, a mobile phone user is helped to realize hardware encryption on the bank card information with low price, and a professional AES standard of over 256 bits is reached. Meanwhile, when the user carries out secondary payment, it is only needed to directly invoke the bank card information and there is no need to use a card reader or the bank card again. Therefore, payment experience and security of the user can be substantially enhanced.

The frame structure is a rectangle structure: 64 rows/frame, 34 columns, 139264 kb/s. the first and second columns are the overhead. 3th-34th columns are affluent information. Under control of synchronous clock, each affluent is queuing. First row of first frame is written into 256 bits of first frame of first affluent, and second row of first frame is written into 256 bits of first frame of second affluent and so on. In multiple connection procedure, with decoded to NRZ code, under control of main clock, each affluent is written to own buffer register. Then, under control of synchronous multiple connection clock, the procedure is continued to enter each queue equipment, mixer and encoder to output codes. The method overcomes the shortcomings of PDH and is better than SDH, providing features of less investment, good compatibility and lower technical difficulties.

The invention discloses an expansion system and a method for 256-bit keys based on an advanced encryption standard (AES), and mainly solves the problems of low efficiency and high power consumption in a key expansion process in the existing 256-bit AES. The process includes storing an initial key in the first round of key expansion, taking the first four rows as a round key of the key expansion in the first round, and performing word cycle, byte replacement, and bitwise XOR operations; executing a new byte replacement and a secondary bitwise XOR operation according to serial number n; taking results of the two bitwise XOR operations as a round key and storing in a local register and an external storage cell for the usage of encryption process reading; and repeating the operations for round keys obtained in a former round in following rounds until 14 round keys are obtained, and finishing key expansion. According to the expansion system and the method for the 256-bit keys, instantaneity of key expansion and reusability of round keys are achieved simultaneously, key expansion with high efficiency and low power consumption is achieved, and the expansion system and the method are suitable for key expansion processes of the 256-bit AES.