13 results about "Composite number" patented technology

The invention discloses an outsourcing decryption method for protecting revocable user attributes based on cloud environment data, and belongs to the technical field of cloud computing security. The method comprises an initialization algorithm, an encryption algorithm, a key generation algorithm, an outsourcing decryption algorithm and an attribute revocation algorithm. The method is based on the cloud environment, public parameters are composed of a fixed number of group elements, an attribute set used for encryption is not limited, user revocation can be executed at each attribute level instead of a system level, and finer-grained user access control is achieved. In addition, user information is not leaked when whether the user is revoked or not and outsourcing decryption is judged, the scheme is proved to be safe under the complexity hypothesis of a composite number order group, and the result shows that the scheme is more efficient and more flexible under the scene of user management in the cloud environment through comparative analysis of the performance of similar schemes.

The invention provides a music time coding method for artificial neural network modeling. The method aims at the coding requirement of music beat time, molecules are decomposed according to a fixed denominator for multi-bit independent classification coding, and the method comprises the following steps: setting the fixed denominator as a composite number and decomposing the composite number into a prime factor combination; the molecules are mapped into vectors, the value range of each bit is determined by a cardinal number of a prime factor combination, and the vectors are converted into one-hot coding sub-vectors with redundant components removed. The technical scheme of the invention solves the problem that the traditional mean square error (MSE) ignores the internal correlation of scores and has high sparsity in the topology recognition task of an optical music recognition system (OMR), and compared with a traditional coding method adopting floating point numerical output and a mean square error loss function under the conditions of the same data set, model architecture and training hyper-parameters, the method provided by the invention has the advantages that the coding efficiency is greatly improved; according to the method, the comprehensive error index is reduced by about 21%, and the model precision and the training efficiency are improved.

The invention provides a security method and device based on homomorphic encryption, and belongs to the technical field of security. In the method, the modulus of a first bootstrap key in an outer product operation is improved from a prime number modulus Q to a composite number modulus, namely the product of the prime number modulus Q and a modulus P, so that the matrix dimension representing the first bootstrap key in the outer product operation can be reduced; therefore, the calculation overhead of outer product operation in the homomorphic calculation process can be reduced. Besides, the modulus of the first bootstrap key in the outer product operation is improved from a prime digital modulus Q to a composite digital modulus, that is, g () in an expression structure of the first bootstrap key can be replaced by P (), so that under the condition, the outer product operation does not need to decompose the first homomorphic message ciphertext gadget, and the calculation overhead is further reduced.

The embodiment of the invention provides a method and device for processing hypercomplex numbers. The present application proposes a new data type that combines a number of at least two components into a local CPU data word. According to the new data type, an m-bit-to-even number or an m-bit complex number is regarded as a composite number comprising two components, rather than an m-bit number, so that an operation can be performed directly on the two components of the pair of even number or the complex number using a single instruction. In addition, a hardware implementation mode of even multiplication and a combined hardware implementation mode of even and complex multiplication are also provided, so that the processing speed and the utilization rate of hardware resources can be improved, and the power consumption is reduced.

The invention provides a task decomposition method and device, a task arrangement method and device and related equipment, and relates to the technical field of data processing, the task decomposition method comprises the steps that an initial task file sent by second equipment is received, and the initial task file comprises a plurality of initial tasks and a number corresponding to each initial task; under the condition that multiple first tasks exist in the multiple initial tasks, the numbers corresponding to the multiple first tasks are decomposed, a first prime number corresponding to each first task is obtained, and the number of each first task is a composite number; the multiple first tasks are classified based on the first prime numbers, multiple parallel tasks and / or multiple serial tasks are obtained, and the first prime numbers corresponding to the multiple parallel tasks are prime numbers of the first set; and adding the plurality of parallel tasks to a first sub-list in the first task list, adding the plurality of serial tasks to a second sub-list in the first task list, and adding the second task to the second task list. The task arrangement effect can be improved.

The invention discloses a composite number length mutual Z-complementary set generation method based on an FPGA (Field Programmable Gate Array) and a communication device, and belongs to the field of wireless communication. The method comprises the following specific steps: data preparation: randomly taking an initial sequence X with the length of q * p, and setting a twiddle factor sequence W with the same length; cyclic shift: continuously executing p-1 times of q-bit cyclic shift on the sequence X to form a set containing p sequences; and DFT operation: performing DFT operation on the sequence set generated after cyclic shift processing to obtain a new sequence set which is a mutual Z-complementary set. A communication device comprises a data input module, a DFT calculation module and a data output module, and the data input module is responsible for data preparation and execution of cyclic shift; the DFT calculation module is used for carrying out DFT operation on an input sequence; and the data output module outputs the generated mutual Z-complementary set under the control of a specific clock signal. The generated mutual Z-complementary set is suitable for a spatial modulation multiple-input-multiple-output system.

The technical concept of the present invention relates to an RSA accumulator-based lookup argument method for performing lookup argument on a composite number and duplicated element. According to an embodiment of the present disclosure, RSA accumulator-based lookup argument method performed by at least one processor may include obtaining a table vector including a plurality of table values, generating a plurality of prime number random values, generating a plurality of prime number table values respectively corresponding to the plurality of table values by using the plurality of prime number random values, generating a prime number table vector by using the plurality of prime number table values and the plurality of prime number random values, publishing the prime number table vector, and performing RSA accumulator-based lookup argument by using the prime number table vector to check whether an index value is included in the table vector.

The technical concept of the present invention relates to an RSA accumulator-based lookup argument method for performing lookup argument on a composite number and duplicated element. According to an embodiment of the present disclosure, RSA accumulator-based lookup argument method performed by at least one processor may include obtaining a table vector including a plurality of table values, generating a plurality of prime number random values, generating a plurality of prime number table values respectively corresponding to the plurality of table values by using the plurality of prime number random values, generating a prime number table vector by using the plurality of prime number table values and the plurality of prime number random values, publishing the prime number table vector, and performing RSA accumulator-based lookup argument by using the prime number table vector to check whether an index value is included in the table vector.

The application discloses a reconfigurable cryptographic accelerator based on a modulo-30 two-dimensional sieve table and an FPGA implementation method thereof, and belongs to the technical field of FPGA hardware acceleration and cryptographic chips. The application constructs an 8-column and multi-row two-dimensional sieve table structure by using a modulo-30 reduction residue system, and compresses a candidate prime number space by 73.3%; a modulo-30 address generation unit is adopted to generate a storage address by using a 3-bit state machine and a row counter, only shift and addition operations are needed, and division and modulus are completely replaced; a matrix deletion operation unit is used to realize parallel screening of multiple processing units, and address iteration and bit operation are used to complete composite marking; a reconfigurable multi-mode application module is used to dynamically distribute prime number streams to different functional modules such as prime number direct output, random number generation, key derivation, hash calculation and the like, and supports runtime mode switching. The application realizes high-speed, low-resource and deterministic prime number generation and multi-mode cryptographic acceleration on an FPGA, and can be applied to cryptographic chips, blockchain nodes, post-quantum cryptographic systems and secure terminal devices.

The application provides a task decomposition method, a task arrangement method, a device and related equipment, and relates to the technical field of data processing. The task decomposition method comprises the following steps: receiving an initial task file sent by a second device, wherein the initial task file comprises multiple initial tasks and the number corresponding to each initial task; in the case that multiple first tasks exist in the multiple initial tasks, decomposing the numbers corresponding to the multiple first tasks to obtain the first prime number corresponding to each first task, and the number of each first task is a composite number; classifying the multiple first tasks based on the first prime number to obtain multiple parallel tasks and / or multiple serial tasks, wherein the first prime numbers corresponding to the multiple parallel tasks are the prime numbers of a first set; adding the multiple parallel tasks to a first sub-list in a first task list, adding the multiple serial tasks to a second sub-list in the first task list, and adding a second task to a second task list. The application can improve the task arrangement effect.

A system is provided which includes a first communications network including first nodes and a second communications network including a group of second nodes. Each of the first nodes is configured to transmit a multi-destination packet to two or more second nodes among the group of second nodes based on numerical identifiers which respectively correspond to the second nodes and are different from one another and a composite number corresponding to the group of second nodes. The composite number is a product of the numerical identifiers.

We provide a Rivest-Shamir-Adleman (RSA) accumulator-based index proof method that provides a prime number table vector by converting composite numbers included in the table vector into prime numbers in the setup stage. [Solution] In an index proof system in which a setup module, a prover, and a verifier are connected via a network that allows them to communicate with each other, an RSA accumulator-based index proof method obtains a table vector including a plurality of table values, generates a plurality of prime random values, generates a plurality of prime table values ​​corresponding to the plurality of table values ​​using the prime random values, generates a prime table vector using the plurality of prime table values ​​and the plurality of prime random values, publishes the prime table vector, and performs RSA accumulator-based index proof to verify whether an index value is included in the table vector using the prime table vector.

A parameter generation device (10) generates a seed. A pre-calculation unit (11) calculates, as a composite number condition, an integer condition such that at least one of a first integer and a second integer obtained by substituting an integer into each of a first polynomial p (x) and a second polynomial r (x) becomes a composite number. A seed candidate generation unit (12) searches for an integer in which a Hamming weight expressed by a signed binary system expressed in a non-contiguous form is included in a weight range (W). A seed candidate generation unit (12) deletes integers satisfying a composite number condition from the set of integers obtained by the search, and sets the deleted integers as a set (T) of seed candidates. A prime number determination unit (13) extracts, from a set (T) of seed candidates, integers that are substituted so that both a first polynomial and a second polynomial become prime numbers, and sets the extracted integers as a set (S).