3 results about "Composite number" patented technology

The technical concept of the present invention relates to an RSA accumulator-based lookup argument method for performing lookup argument on a composite number and duplicated element. According to an embodiment of the present disclosure, RSA accumulator-based lookup argument method performed by at least one processor may include obtaining a table vector including a plurality of table values, generating a plurality of prime number random values, generating a plurality of prime number table values respectively corresponding to the plurality of table values by using the plurality of prime number random values, generating a prime number table vector by using the plurality of prime number table values and the plurality of prime number random values, publishing the prime number table vector, and performing RSA accumulator-based lookup argument by using the prime number table vector to check whether an index value is included in the table vector.

The application discloses a reconfigurable cryptographic accelerator based on a modulo-30 two-dimensional sieve table and an FPGA implementation method thereof, and belongs to the technical field of FPGA hardware acceleration and cryptographic chips. The application constructs an 8-column and multi-row two-dimensional sieve table structure by using a modulo-30 reduction residue system, and compresses a candidate prime number space by 73.3%; a modulo-30 address generation unit is adopted to generate a storage address by using a 3-bit state machine and a row counter, only shift and addition operations are needed, and division and modulus are completely replaced; a matrix deletion operation unit is used to realize parallel screening of multiple processing units, and address iteration and bit operation are used to complete composite marking; a reconfigurable multi-mode application module is used to dynamically distribute prime number streams to different functional modules such as prime number direct output, random number generation, key derivation, hash calculation and the like, and supports runtime mode switching. The application realizes high-speed, low-resource and deterministic prime number generation and multi-mode cryptographic acceleration on an FPGA, and can be applied to cryptographic chips, blockchain nodes, post-quantum cryptographic systems and secure terminal devices.