RSA key pair fast generation system and RSA key pair fast generation method

A technology for generating a system and a key pair, which is applied to the cryptographic field in the field of information security, and can solve the problem of long generation time of RSA keys, and achieve the effect of increasing the speed, improving the speed and reducing the generation time.

Inactive Publication Date: 2017-03-08
BEIJING TONGFANG MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0023] The purpose of the present invention is to provide a system and method for fast generation of RSA key pairs, which can realize fast retrieval, filtering and determination of RSA key pairs, and optimize the existing prim

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  • RSA key pair fast generation system and RSA key pair fast generation method
  • RSA key pair fast generation system and RSA key pair fast generation method
  • RSA key pair fast generation system and RSA key pair fast generation method

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Embodiment Construction

[0067] In order to facilitate the understanding of those skilled in the art, the present invention will be further described below in conjunction with the accompanying drawings, but it cannot be used to limit the protection scope of the present invention.

[0068] First of all, the RSA algorithm is an asymmetric cryptographic algorithm. The so-called asymmetric means that the algorithm requires a pair of keys. If one of them is used for encryption, the other is required for decryption.

[0069] The algorithm of RSA involves three parameters, assumed to be n, e1, e2. Among them, n is the product of two large prime numbers p and q, and the number of bits occupied by the binary representation of n is the so-called key length. e1 and e2 are a pair of related values, e1 can be taken arbitrarily, but e1 and (p-1)*(q-1) are required to be mutually prime; then choose e2, and require (e2*e1) mod((p-1) *(q-1))=1. (n, e1), (n, e2) is the key pair. Where (n, e1) is the public key and (...

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Abstract

The invention discloses an RSA key pair fast generation system and an RSA key pair fast generation method. The system comprises a CPU core, a cipher coprocessor, a prime number generator, and a memory. The prime number generator is used for filtering composite numbers, is implemented in hardware form, supports 256-bit, 512-bit, 1024-bit, 2048-bit and 4096-bit composite number filtering, and completes modular redundancy, calculation and identification table setting. According to the RSA key pair fast generation method, in order to realize fast key pair retrieving, filtering and judging in an asymmetric algorithm, a hardware-based composite number filtering scheme is adopted, optimized modular exponentiation and improved Montgomery modular multiplication are employed, and the existing prime number decision algorithm is optimized. Thus, efficient prime number screening is realized, the key pair generation speed is increased, and the problem that the generation of an RSA key pair takes long in the existing encryption and decryption technology is solved.

Description

technical field [0001] The present invention relates to cryptography technology in the field of information security, especially for the rapid generation of asymmetric algorithm RSA key pairs in cryptography, which can be applied to various fields such as security chips, payment terminals, and network security. Generate large prime numbers within the specified range, and use the found large prime numbers to perform operations such as encryption and decryption, digital signature verification, etc., to improve the security and reliability of system transmission. Background technique [0002] The information industry is the fastest and most dynamic emerging industry in today's world economic development. With the rapid development of information technology and the rapid popularization and application of information products, especially financial bank cards, resident health cards, financial social security cards, USBKey, mobile With the advent of security chips such as payment c...

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Application Information

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IPC IPC(8): H04L9/32H04L9/30H04L9/08H04L29/06
Inventor 郭耀华黄金煌岳超丁义民乔瑛黄钧许秋林马迁张满新陈雪煜
Owner BEIJING TONGFANG MICROELECTRONICS
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