18 results about "Montgomery reduction" patented technology

The application discloses a Montgomery multiplication method and device and a reduction method. A 2M-bit product value is obtained through arithmetic multiplication of a first multiplier and a second multiplier; the first multiplier and the second multiplier are two M-bit multipliers of Montgomery multiplication; the product value is stored in adjacent second registers and first registers, the second registers are used for storing high M bits of the product value, and the first registers are used for storing low M bits of the product value; an M-bit all-1 value is used as an M-bit accumulation value of Montgomery reduction, and the first registers are accumulated to obtain a carry value; the first registers are subjected to two continuous arithmetic multiplications to obtain a high-bit accumulation value required by Montgomery reduction; the obtained carry value and high-bit accumulation value are accumulated to the second registers to obtain a result after reduction, and the Montgomery multiplication result of the first multiplier and the second multiplier is determined according to the result after reduction.

Disclosed in the present invention are a general-purpose zk-SNARK zero-knowledge-proof optimization system and method. The system comprises: a trusted device, a prover and a verifier, wherein the prover uses a bucket algorithm to implement a multi-scalar multiplication operation, and the prover includes a window splitting unit, an in-bucket point reduction unit, an in-window reduction unit and a window aggregation unit, the window splitting unit splitting the multi-scalar multiplication operation into a plurality of subtasks on the basis of a set window, which is dynamically set on the basis of the computational cost of Montgomery modular multiplication, the in-bucket point reduction unit reducing each point on an elliptic-curve finite field into a bucket, so as to obtain a result of each subtask, the in-window reduction unit being used for point-multiplying a bucket number by a reduced bucket and accumulating buckets within the same window to reduce same into one bucket, so as to obtain the window value of each window, and the window aggregation unit obtaining a computational result of the multi-scalar multiplication on the basis of the window value of each window. The present invention effectively optimizes the execution efficiency of multi-scalar multiplication, and is conducive to realizing the efficient operation of a zk-SNARK proof generation process.

The invention discloses an x86-64 platform-oriented full-pipeline universal Montgomery modular multiplication operation method, which comprises the following steps of: realizing universal Montgomery modular multiplication operation and modular square operation of a 256-bit elliptic curve cryptographic algorithm by utilizing a BMI2 instruction set and an ADX instruction set and combining a pipeline and a multi-emission mechanism of an x86-64 platform through allocating registers and adjusting calculation steps; wherein the general Montgomery modular multiplication operation comprises multiplication operation, the general Montgomery modular square operation comprises square operation, and both the two operations comprise general Montgomery modular reduction operation; the calculation steps of multiplication and square operation are adjusted, so that two addition chains in the operation are executed in parallel; and adjusting the calculation step of the Montgomery module reduction operation, extending the previous round of additive operation of the cycle calculation step in the operation to the next round, and executing the previous round of additive operation and the next round of multiplication operation in parallel. According to the method, the universal Montgomery modular multiplication operation of the x86-64 platform can be realized, and the operation performance is optimized.

An encryption and decryption device, an encryption method, a decryption method and related products. The device comprises an encryption and decryption module and a modular multiplication operation module. The encryption and decryption module is configured to send first data and second data in a constant domain to the modular multiplication operation module. The modular multiplication operation module is configured to multiply the first data and the second data to obtain a first multiplication result, perform Montgomery reduction on the first multiplication result to obtain third data, multiply the third data and a pre-computed parameter to obtain a second multiplication result, and perform Montgomery reduction on the second multiplication result to obtain a modular multiplication operation result in the constant domain and return the result. The encryption and decryption module performs ECC operation based on the modular multiplication operation result to obtain a key, and uses the key to encrypt or decrypt data. The modular multiplication operation module only needs to perform two times of reduction to realize modular multiplication calculation, optimizes the calculation process of the Montgomery modular multiplication algorithm, reduces the calculation overhead, and further improves the overall operation efficiency of ECC encryption and decryption.

The invention discloses a hardware accelerator, and relates to the technical field of integrated circuits and hardware acceleration, and the hardware accelerator comprises a register configuration module which is used for receiving configuration parameters sent by a processor chip and generating a calculation starting signal; the cache module is used for receiving and caching target operation data input by the processor chip based on configuration parameters; the modular multiplication calculation module is respectively connected with the register configuration module and the cache module, and is used for splitting the target operation data into a plurality of data segments according to the configuration parameters, and performing Montgomery modular multiplication operation on each data segment based on a pipeline structure comprising a master control unit and a plurality of slave calculation units; wherein the slave computing units are arranged in a cascading manner, and different data segments are processed in parallel under the scheduling of the master control unit. In the large number operation process, the working frequency of the accelerator is improved, and the operation throughput rate is improved.

This invention discloses an optimal modular multiplication algorithm selection method, encryption / decryption method, and related apparatus. In the optimal modular multiplication algorithm selection method, if the operand type is a constant multiplied by a variable or a variable multiplied by a constant, or if the operand type is a variable multiplied by a variable and the bit width of the modulus is less than or equal to a preset threshold (i.e., for resource-constrained embedded devices or scenarios requiring frequent NTT / INTT transformations in the algorithm), the Plantard modular multiplication algorithm is used to perform modular multiplication on the two multipliers. For operand types of variable multiplication with an odd modulus and a bit width less than or equal to the preset threshold, the Montgomery modular multiplication algorithm is used. For operand types of variable multiplication with an even modulus and a bit width less than or equal to the preset threshold, the Barrett modular multiplication algorithm is used. Using this invention facilitates dynamic evaluation and switching to the optimal modular multiplication implementation path for the current scenario based on the bit width of the input modulus and the operand type.

This invention discloses a fully pipelined general Montgomery modular multiplication method for the x86-64 platform. Utilizing the BMI2 and ADX instruction sets, combined with the pipelined and multi-issue mechanisms of the x86-64 platform, and through register allocation and adjustment of computation steps, it implements general Montgomery modular multiplication and modular squaring operations for 256-bit elliptic curve cryptography algorithms. Specifically, the general Montgomery modular multiplication operation includes multiplication, and the general Montgomery modular squaring operation includes squaring; both operations also include general Montgomery modular reduction. The computation steps for multiplication and squaring are adjusted to allow the two addition chains in the operation to execute in parallel. The computation steps for Montgomery modular reduction are also adjusted to extend the previous round of addition in the loop calculation step to the next round, and execute it in parallel with the next round of multiplication. This invention enables general Montgomery modular multiplication on the x86-64 platform, optimizing computational performance.

An apparatus and a method for performing a Montgomery reduction of an input C modulo a modulus N, in particular in the framework of a Montgomery multiplication, comprising: (i) performing a multiplication to obtain an approximated product Y on the basis of a value D and the modulus N, wherein only a higher-order part of the approximated product Y is computed and / or approximated on the basis of an incomplete execution of the multiplication, and wherein the value D is derived from the input C and an auxiliary integer N′ of the Montgomery reduction, (ii) determining a sum by adding a word or partial word of the input C to a word or partial word of the approximated product Y, (iii) determining a carry on the basis of the sum, and (iv) adding the carry to the input C or to a value derived from the input C.

Provided are a method, device and equipment for storing data. The method comprises: obtaining a target operation result of a Montgomery modular multiplication operation; if the target operation result is a real operation result, storing the target operation result in a first memory or a second memory based on a target random number, the target random number being used to select a memory for storing the target operation result from the first memory and the second memory, the first memory being different from the second memory. By randomly storing the real operation result in the first memory or the second memory according to the target random number, the storage result of the real operation result can be randomized, so that an attacker cannot distinguish the storage position of the real operation result, thereby not only resisting side channel attacks, but also resisting electromagnetic attacks, and the security of the chip can be improved.

This application discloses a high-level Montgomery modular multiplication circuit and its parallel operation method. The circuit includes: a loop control module, comprising m sets of loop control units for parallel operation of loop calculations to complete k+1 rounds of loop calculations, and for buffering intermediate data during the loop calculation process, reading data required for loop calculations from a storage module, and transmitting the corresponding data to the operation module according to the loop calculation steps; a core state machine module, responsible for controlling the start and end of each first-level loop calculation in the k+1 rounds of loop calculations run by the m sets of loop control units in the loop control module; an operation module, for receiving data transmitted by the loop control module, and performing multiplication and addition operations based on the received data; and a storage module, for storing data required for loop calculations for the loop control device to read and call. This application achieves a reduction in circuit area while maintaining high efficiency in loop calculations based on the parallel operation of m sets of loop control units.

The approaches proposed here relate to apparatus and method for performing a Montgomery reduction of an input C modulo a modulo N, in particular within the framework of a Montgomery multiplication, comprising: (i) performing a multiplication to obtain an approximate product Y based on a value D and the modulo N, wherein only a higher-order part of the approximate product Y is computed and / or approximated by means of an incomplete execution of the multiplication and wherein the value D is derived from the input C and an auxiliary number N' of the Montgomery reduction, (ii) determining a sum by adding a word or part of the input C with a word or part of the approximate product Y, (iii) determining a carry depending on the sum, and (iv) adding the carry to the input C or to a value derived from the input C.

The application discloses a Montgomery modular multiplier based on parallel structure and coding, comprising a pre-computation storage unit, a control unit and two groups of iterative computation modules, the iterative computation module comprising an input selection control unit, a multiplexer, a CSA addition unit, an output shift unit and a register group. The Montgomery modular multiplier adds an additional shift compensation operation, decomposes the cyclic iterative computation of the partial product into two groups of parallel computation, realizes two-way parallel of 2-base Montgomery modular multiplication, and reduces the cycle delay of the original 2-base Montgomery modular multiplication to 1 / 2 of the original. In combination with the characteristics of the two-way parallel design, the input data is re-encoded, the additional shift compensation operation and the partial product are pre-computed, the original three additions are converted into a multiplexing and an addition, the additional area overhead caused by the parallel of the circuit module is optimized, the critical path of the overall operation is shortened, and the Montgomery modular multiplier can be better deployed in a lightweight application scenario.

The application provides a modular multiplier applied to SM9, comprising: a multiplication circuit configured to perform a multiplication operation on two operators in the SM9 to obtain a product of the two operators, wherein the product is a binary number, and the number of bits of the product is m, and the m is an integer multiple of 2; and a modulus calculator connected with the multiplication circuit and configured to perform n times of modulus operation on the product in n clock cycles to obtain a final modular multiplication result, wherein each time of the modulus operation is performed in one clock cycle to obtain one modulus result, and the n is a positive integer less than m / 2. The application also provides a corresponding secure chip and encryption algorithm. The above scheme of the application avoids using the Montgomery modular multiplication algorithm, reduces unnecessary repeated modular multiplication, improves the speed of the entire modular multiplication operation in the SM9, and thus improves the overall performance of the SM9.

The invention provides a data encryption method and device, a storage medium and electronic equipment, and relates to the technical field of encryption, and the method comprises the steps: obtaining to-be-encrypted target data and an encryption key in a data encryption request under the condition that the data encryption request is received; determining a target modular multiplication operation length of a modular exponentiation operation task corresponding to the target data based on the length of the modulus of the encryption key; under the condition that the target modular multiplication operation length is larger than the maximum operation length of the encryption module, based on the Montgomery modular multiplication algorithm, a modular exponentiation operation task corresponding to the target data is decomposed, a sub-operation task sequence is obtained, and the sub-operation task sequence comprises a plurality of sub-operation tasks; each sub-operation task is one of a sub-modular multiplication operation task and a sub-modular addition operation task, and the operation length of each sub-operation task is matched with the maximum operation length of the encryption module; and executing the sub-operation task sequence through an encryption module to obtain encrypted data corresponding to the target data. And the data encryption requirement can be met.

This invention discloses a Montgomery modular multiplication implementation apparatus and method, a chip startup method, an electronic device, and a storage medium. The Montgomery modular multiplication implementation apparatus includes: a control module configured to output control signals based on the operational logic of modular multiplication to manage the execution flow of modular multiplication operations; and a calculation module configured to read source operands from a storage module in response to the control signals from the control module to perform corresponding operational operations. The calculation module includes: a multiply-add module configured to perform high-radix multiplication and multi-level accumulation operations on the source operands to generate intermediate modular multiplication results; and a reduction module configured to perform reduction operations on the intermediate modular multiplication results to generate a final modular multiplication result within a predetermined range. This invention can adapt to modular multiplication operations of arbitrary bit widths, effectively improving the accuracy and efficiency of modular multiplication operations.

The invention relates to a device and a method for performing a Montgomery reduction on an input C, in particular in the scope of Montgomery multiplications modulo N, comprising: (i) performing a multiplication based on a value D and modulo N to obtain an approximate product Y, wherein only the higher part of the approximated product Y is calculated and / or approximated according to the incomplete implementation of the multiplication, and wherein the value D is derived from the input C and the auxiliary number N'of the Montgomery reduction; (ii) determining a sum value by adding the word or partial word of the input C to the word or partial word of the approximate product Y; (iii) determining a carry according to the sum value; and (iv) adding the carry to the input C or to a value derived from the input C.

The invention provides a password operation method and device, a chip and computer equipment. The method comprises the steps of obtaining to-be-operated data and algorithm parameters corresponding to a Montgomery modular multiplication algorithm; the algorithm parameters comprise a cardinal number and a modulus; the cardinal number is a power of 2; the cardinal number and the modulus are co-prime; determining a first parameter obtained after the cardinal number performs modulus operation on the modulus; calling a Montgomery modular multiplication algorithm for at least one time, and calculating the first parameter to obtain a first calculation result; calling a Montgomery modular multiplication algorithm once based on the first calculation result and the to-be-calculated data to obtain a second calculation result; and calling a Montgomery modular multiplication algorithm for at least one time based on the second calculation result and the to-be-calculated data to obtain a password operation result. According to the embodiment of the invention, the cryptographic operation efficiency is improved.

The invention discloses a method and a device for realizing Montgomery multiplication and a reduction method. The method comprises the following steps of: obtaining a 2M-bit product value through arithmetic multiplication of a first multiplier and a second multiplier; wherein the first multiplier and the second multiplier are two M-bit multipliers of Montgomery multiplication; the product value is stored in the adjacent second register and first register, the second register is used for storing high M bits of the product value, and the first register is used for storing low M bits of the product value; the M-bit all-one value is adopted as an M-bit accumulated value of Montgomery reduction, and accumulation is conducted on the first register to obtain a carry value; performing two continuous arithmetic multiplications on the first register to obtain a high-order accumulated value required by Montgomery reduction; and accumulating the obtained carry value and the high-order accumulated value to the second register to obtain a reduced result, and determining a Montgomery multiplication result of the first multiplier and the second multiplier according to the reduced result.