99results about How to "High-speed execution" patented technology

A flash memory includes a data bank having a plurality of banks, a merge bank, and an update data bank. A file system using the flash memory includes a unit storing update data corresponding to a data rewrite command into the update data bank, a unit selecting the latest update data for each block from update data stored in the update data bank when the update data bank becomes full, and a processing unit processing the latest update data. The processing unit includes a unit storing latest update data into a merge bank, a unit selecting data associated with the latest update data from the data bank to store the selected data into the merge bank, and a unit setting the merge bank as a new data bank.

An instruction for an arithmetic/logic operation to a main processing circuit is stored in the form of a micro program in a micro instruction memory, and the operation of the main processing circuit is controlled in accordance with the micro program, under the control of a controller. In the main processing circuit, a memory mat is divided into entries each storing data of a plurality of bits, and for each entry, a processor (ALU) is arranged. Arithmetic/logic operations are performed entry-parallel and in bit-serial manner between each entry and the associated ALU. In accordance with the micro program control method, a large amount of data can be processed efficiently. Thus, a processing device that efficiently performs an arithmetic/logic operation on a large amount of data at high speed is provided.

A multi-word arithmetic device, capable of executing a variety of types of multi-word arithmetic required for elliptic curve cryptology, includes the following. A memory 40, formed from two dual-port memories 41 and 42, temporarily stores n-word integers on which calculation is performed, and a calculation result. An arithmetic unit 20 executes two or more types of calculation, including addition and multiplication, on each word, and outputs a one-word result. A memory input/output unit 30 supplies a maximum of three pieces of one-word data from the memory 40 to the arithmetic unit 20, while simultaneously storing a one-word calculation result from the arithmetic unit 20 in the memory 40. A control unit 10 controls the arithmetic unit 20 and the memory input/output unit 30 so as to have the arithmetic unit execute one of modular addition and Montgomery reduction on n words.

Image dividing means of an RPU divides raw image data into divided image data A1 having 2048 horizontal pixels and A2 having 1024 horizontal pixels. The divided image data A1 is continuously processed in single pixel processing means and multiple pixel processing means and thereafter transferred to and stored in a buffer. The divided image data A2 is processed in the single pixel processing means and thereafter transferred to and temporarily stored in another buffer. The multiple pixel processing means reads and processes divided image data A2a stored in this buffer and thereafter transfers and stores the same to and in still another buffer. Image combining means reads divided image data A1b and A2b stored in the buffers and combines the same with each other. Thus, an image processing time and a cost can be reduced even if raw image data having horizontal pixels in a number exceeding the capacity of a line memory is received.

After a skew of a sheet as a recording medium is corrected by correcting a sheet curve, exposure writing on a photosensitive drum is started synchronously with re-driving of resist rollers. When a sheet front edge is detected by a sensor, sheet conveyance is continued while adjusting a sheet conveying speed when an exposure start position reaches a transfer position at a pressure contact point between the drum and a transfer roller, thereby adjusting the time of arrival at the transfer position. A time/distance interval between the preceding and subsequent sheets are shortened, a conveying path is shortened, and the whole apparatus is miniaturized. Print processing efficiency is raised and stable printing without a variation is executed. A transfer start position of the sheet is made to accurately coincide with the exposure start position of the drum, thereby realizing a high print processing speed.

In an image processing method of determining the positional relationship among virtual objects in virtual space and generating a virtual shadow of the virtual objects, a plurality of virtual objects are rendered in a first plane to which a first axis passing through a virtual light source is normal, and the positional relationship among the plurality of virtual objects is determined based upon the result of rendering acquired. Shadow information of the plurality of virtual objects is generated using the result of acquired rendering.

In an exclusive OR circuit (XOR gate) constituting an ECC circuit, the drivability of P channel MOS transistors is set larger than the drivability of N channel MOS transistors. Accordingly, the speed of the logic level of an output node being set to an H level from an L level identified as a reset state is increased than the case where the drivability is set equal. Thus, the time required to output a syndrome from a plurality of stages of XOR gates can be reduced to allow execution of error correction processing at high speed.

A landmark search apparatus includes a position obtaining unit configured to obtain a current position of the object, a first storage unit configured to store landmark information including a name of a landmark and position information of the landmark related to the name, an retrieving unit configured to retrieve the landmark information from the first storage unit based on the obtained current position, a second storage unit configured to store the retrieved landmark information as retrieved landmark information, and a determining unit configured to determine whether the retrieved landmark information is valid, based on the current position of the object, and a distance between a position of the subject at the time of storing the retrieved landmark information in the second storage unit and the landmark indicated by the retrieved landmark information.

An appearance inspection apparatus is composed of a memory 14, a thread generator and a plurality of CPUs 10 to 13. The memory 14 stores image data of an appearance of an IC. The thread generator generates a thread in which a procedure is described for independently processing the image data stored in the memory 14 and storing the processing result into the memory 14. The plurality of CPUs 10 to 13 for executing the plurality of threads generated by the thread generator, in parallel. Thus, this can provide an appearance inspection apparatus and an appearance inspection method that can execute an appearance inspection at a high speed, irrespectively of a simple configuration.

A cryptographic processing method in which dependence of cryptographic processing process and secret information on each other is cut off; and in which, when a scalar multiplied point is calculated from a scalar value and a point on an elliptic curve in an elliptic curve cryptosystem, a value of a bit of the scalar value is judged; and in which operations on the elliptic curve are executed a predetermined times and in a predetermined order without depending on the judged value of the bit.

A heating/cooling method, a manufacturing method of an image displaying apparatus, a heating/cooling apparatus, and a heating/cooling processing apparatus, in which the heating and cooling of a substrate can be executed at a high speed are provided.

The present invention provides a processor which has a small-scale circuit and is capable of executing loop processing at a high speed while consuming a small amount of power. When the processor decodes an instruction “jloop C6,C1:C4,TAR,Ra”, the processor (i) sets a conditional flag C4 to 0 when the value of a register Ra is smaller than 0, (ii) moves the value of a conditional flag C2 to a conditional flag C1, moves the value of a conditional flag C3 to the conditional flag C2, and moves the value of the conditional flag C4 to the conditional flags C3 and C6, (iii) adds −1 to the register Ra and stores the result into the register Ra, and (iv) branches to an address specified by a branch register (TAR). When not filled with a branch target instruction, the jump buffer will be filled with a branch target instruction.

A pattern correction apparatus for performing both of optical proximity effect correction and process proximity effect correction with regard to a design pattern includes: a correction calculation means configured to perform correction calculation by two-dimensional model-based optical proximity effect correction for each of sampling points set on pattern edges which form the design pattern; the correction calculation means performing the correction calculation which involves weighting with a two-dimensional distribution of the pattern edges around the sampling point taken into consideration; the weighting being performed such that a high weight is applied to a region in which reaction products which can have an influence on the sampling point are produced but a low weight is applied to any other region.

An image-reading apparatus, includes a variation acquiring unit that acquires a variation of a distance or an angle between a medium to be read and an imaging unit or a light source, and a color shift correcting unit that calculates a color shift between the medium and the imaging unit or the light source based on the variation acquired by the variation acquiring unit and corrects the color shift.

For the entropy coding of image data after subjected to orthogonal transforation and quantization, a plurality of entropy coding units are provided in parallel. The plurality of entropy coding units can be operated efficiently and the entropy coding can be executed at high speed. In order to realize these operations, for example, an entropy coding apparatus has: an orthogonal transformation unit for performing an orthogonal transformation of image data; a quantization unit for quantizing coefficients obtained by the orthogonal transformation; N entropy coding units for entropy-coding the quantized coefficients output from the quantization unit; a distribution unit for selecting one of the N entropy coding units for each quantized coefficient and supplying the quantized coefficient to the selected entropy coding unit; and a prediction unit for monitoring a coding state of each of the N entropy coding units and predicting an optimum one of the N entropy coding units for a succeeding quantized coefficient in accordance with monitor results.

An information recording and/or reproduction processing apparatus is provided. The information recording and/or reproduction processing apparatus is provided by which additional information such as copy protection information is recorded as encrypted data on an information recording medium and also a cryptographic key is recorded such that the difficulty in analysis thereof is promoted. Where additional information such as copy protection information is encrypted and recorded and also a cryptographic key for the encrypted additional information is recorded together, a seed is generated based on an error correction code set corresponding to the additional information. Then, a scrambling or bit position conversion process in which random numbers generated based on the seed are applied is executed for the cryptographic key data, and resulting cryptographic key data is recorded on an information recording medium. Upon such recording, the additional information is recorded as pit information while the cryptographic key data is recorded as wobble data. The cryptographic key has an increased difficulty in analysis and allows achievement of an efficient data reproduction process.

A circuit description is separated into sequential-circuit descriptions as a sequential-circuit-description part and combinational-circuit descriptions as a combinational-circuit-description part. The sequential-circuit-description part is modified and converted into combinational-circuit descriptions. A simulation description is configured with the combinational-circuit-description part and the combinational-circuit descriptions converted from the sequential-circuit-description part. This arrangement can generate a simulation description that does not contain a sequential-circuit description requiring an arithmetic operation at each clock event and that allows the number of arithmetic operations to be reduced. This is because, during simulation, the arithmetic operation is triggered by an update of input variables other than a clock, rather than being triggered by a clock event.

The invention provides a hardware method for building a TCP data stream connection. A hardware module is used to make deep analysis for the data packet, and in term of quintuple and state information to build communication connection for the packet. When using the hardware connection, each functional module works independently so that opening the TCP connection doesn't reduce the efficiency of other modules. Meanwhile RAM read writing speed by hardware is also very high to make the data format of read writing able to be simplified.

A storage control apparatus controls physical disks according to the host access using a pair of controllers, while mirroring processing is decreased when data is written to a cache memory and high-speed operation is enabled. The mirror management table is created with allocating the mirror area of the cache memory of the other controller, and acquisition of a mirror page of the cache memory of the other controller is executed referring to the mirror management table without an exchange of mirror page acquisition messages between the controllers.